1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6#include <dt-bindings/clock/imx8ulp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/imx8ulp-power.h> 10 11#include "imx8ulp-pinfunc.h" 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 gpio0 = &gpiod; 20 gpio1 = &gpioe; 21 gpio2 = &gpiof; 22 mmc0 = &usdhc0; 23 mmc1 = &usdhc1; 24 mmc2 = &usdhc2; 25 serial0 = &lpuart4; 26 serial1 = &lpuart5; 27 serial2 = &lpuart6; 28 serial3 = &lpuart7; 29 }; 30 31 cpus { 32 #address-cells = <2>; 33 #size-cells = <0>; 34 35 A35_0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a35"; 38 reg = <0x0 0x0>; 39 enable-method = "psci"; 40 next-level-cache = <&A35_L2>; 41 }; 42 43 A35_1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a35"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 next-level-cache = <&A35_L2>; 49 }; 50 51 A35_L2: l2-cache0 { 52 compatible = "cache"; 53 }; 54 }; 55 56 gic: interrupt-controller@2d400000 { 57 compatible = "arm,gic-v3"; 58 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ 59 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0"; 67 method = "smc"; 68 }; 69 70 timer { 71 compatible = "arm,armv8-timer"; 72 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 73 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 74 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 75 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 76 }; 77 78 frosc: clock-frosc { 79 compatible = "fixed-clock"; 80 clock-frequency = <192000000>; 81 clock-output-names = "frosc"; 82 #clock-cells = <0>; 83 }; 84 85 lposc: clock-lposc { 86 compatible = "fixed-clock"; 87 clock-frequency = <1000000>; 88 clock-output-names = "lposc"; 89 #clock-cells = <0>; 90 }; 91 92 rosc: clock-rosc { 93 compatible = "fixed-clock"; 94 clock-frequency = <32768>; 95 clock-output-names = "rosc"; 96 #clock-cells = <0>; 97 }; 98 99 sosc: clock-sosc { 100 compatible = "fixed-clock"; 101 clock-frequency = <24000000>; 102 clock-output-names = "sosc"; 103 #clock-cells = <0>; 104 }; 105 106 sram@2201f000 { 107 compatible = "mmio-sram"; 108 reg = <0x0 0x2201f000 0x0 0x1000>; 109 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0 0x0 0x2201f000 0x1000>; 113 114 scmi_buf: scmi-buf@0 { 115 compatible = "arm,scmi-shmem"; 116 reg = <0x0 0x400>; 117 }; 118 }; 119 120 firmware { 121 scmi { 122 compatible = "arm,scmi-smc"; 123 arm,smc-id = <0xc20000fe>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 shmem = <&scmi_buf>; 127 128 scmi_devpd: protocol@11 { 129 reg = <0x11>; 130 #power-domain-cells = <1>; 131 }; 132 133 scmi_sensor: protocol@15 { 134 reg = <0x15>; 135 #thermal-sensor-cells = <0>; 136 }; 137 }; 138 }; 139 140 soc@0 { 141 compatible = "simple-bus"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges = <0x0 0x0 0x0 0x40000000>; 145 146 per_bridge3: bus@29000000 { 147 compatible = "simple-bus"; 148 reg = <0x29000000 0x800000>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges; 152 153 wdog3: watchdog@292a0000 { 154 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; 155 reg = <0x292a0000 0x10000>; 156 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 158 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 159 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; 160 timeout-sec = <40>; 161 }; 162 163 cgc1: clock-controller@292c0000 { 164 compatible = "fsl,imx8ulp-cgc1"; 165 reg = <0x292c0000 0x10000>; 166 clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; 167 clock-names = "rosc", "sosc", "frosc", "lposc"; 168 #clock-cells = <1>; 169 }; 170 171 pcc3: clock-controller@292d0000 { 172 compatible = "fsl,imx8ulp-pcc3"; 173 reg = <0x292d0000 0x10000>; 174 #clock-cells = <1>; 175 }; 176 177 tpm5: tpm@29340000 { 178 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; 179 reg = <0x29340000 0x1000>; 180 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&pcc3 IMX8ULP_CLK_TPM5>, 182 <&pcc3 IMX8ULP_CLK_TPM5>; 183 clock-names = "ipg", "per"; 184 status = "disabled"; 185 }; 186 187 lpi2c4: i2c@29370000 { 188 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 189 reg = <0x29370000 0x10000>; 190 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, 192 <&pcc3 IMX8ULP_CLK_LPI2C4>; 193 clock-names = "per", "ipg"; 194 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; 195 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 196 assigned-clock-rates = <48000000>; 197 status = "disabled"; 198 }; 199 200 lpi2c5: i2c@29380000 { 201 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 202 reg = <0x29380000 0x10000>; 203 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, 205 <&pcc3 IMX8ULP_CLK_LPI2C5>; 206 clock-names = "per", "ipg"; 207 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; 208 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 209 assigned-clock-rates = <48000000>; 210 status = "disabled"; 211 }; 212 213 lpuart4: serial@29390000 { 214 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 215 reg = <0x29390000 0x1000>; 216 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; 218 clock-names = "ipg"; 219 status = "disabled"; 220 }; 221 222 lpuart5: serial@293a0000 { 223 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 224 reg = <0x293a0000 0x1000>; 225 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; 227 clock-names = "ipg"; 228 status = "disabled"; 229 }; 230 231 lpspi4: spi@293b0000 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 235 reg = <0x293b0000 0x10000>; 236 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, 238 <&pcc3 IMX8ULP_CLK_LPSPI4>; 239 clock-names = "per", "ipg"; 240 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; 241 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 242 assigned-clock-rates = <16000000>; 243 status = "disabled"; 244 }; 245 246 lpspi5: spi@293c0000 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 250 reg = <0x293c0000 0x10000>; 251 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, 253 <&pcc3 IMX8ULP_CLK_LPSPI5>; 254 clock-names = "per", "ipg"; 255 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; 256 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 257 assigned-clock-rates = <16000000>; 258 status = "disabled"; 259 }; 260 }; 261 262 per_bridge4: bus@29800000 { 263 compatible = "simple-bus"; 264 reg = <0x29800000 0x800000>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges; 268 269 pcc4: clock-controller@29800000 { 270 compatible = "fsl,imx8ulp-pcc4"; 271 reg = <0x29800000 0x10000>; 272 #clock-cells = <1>; 273 }; 274 275 lpi2c6: i2c@29840000 { 276 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 277 reg = <0x29840000 0x10000>; 278 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, 280 <&pcc4 IMX8ULP_CLK_LPI2C6>; 281 clock-names = "per", "ipg"; 282 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; 283 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 284 assigned-clock-rates = <48000000>; 285 status = "disabled"; 286 }; 287 288 lpi2c7: i2c@29850000 { 289 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 290 reg = <0x29850000 0x10000>; 291 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, 293 <&pcc4 IMX8ULP_CLK_LPI2C7>; 294 clock-names = "per", "ipg"; 295 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; 296 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; 297 assigned-clock-rates = <48000000>; 298 status = "disabled"; 299 }; 300 301 lpuart6: serial@29860000 { 302 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 303 reg = <0x29860000 0x1000>; 304 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; 306 clock-names = "ipg"; 307 status = "disabled"; 308 }; 309 310 lpuart7: serial@29870000 { 311 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 312 reg = <0x29870000 0x1000>; 313 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; 315 clock-names = "ipg"; 316 status = "disabled"; 317 }; 318 319 iomuxc1: pinctrl@298c0000 { 320 compatible = "fsl,imx8ulp-iomuxc1"; 321 reg = <0x298c0000 0x10000>; 322 }; 323 324 usdhc0: mmc@298d0000 { 325 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 326 reg = <0x298d0000 0x10000>; 327 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 329 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, 330 <&pcc4 IMX8ULP_CLK_USDHC0>; 331 clock-names = "ipg", "ahb", "per"; 332 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 333 fsl,tuning-start-tap = <20>; 334 fsl,tuning-step= <2>; 335 bus-width = <4>; 336 status = "disabled"; 337 }; 338 339 usdhc1: mmc@298e0000 { 340 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 341 reg = <0x298e0000 0x10000>; 342 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 344 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 345 <&pcc4 IMX8ULP_CLK_USDHC1>; 346 clock-names = "ipg", "ahb", "per"; 347 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 348 fsl,tuning-start-tap = <20>; 349 fsl,tuning-step= <2>; 350 bus-width = <4>; 351 status = "disabled"; 352 }; 353 354 usdhc2: mmc@298f0000 { 355 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 356 reg = <0x298f0000 0x10000>; 357 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 359 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 360 <&pcc4 IMX8ULP_CLK_USDHC2>; 361 clock-names = "ipg", "ahb", "per"; 362 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 363 fsl,tuning-start-tap = <20>; 364 fsl,tuning-step= <2>; 365 bus-width = <4>; 366 status = "disabled"; 367 }; 368 }; 369 370 gpioe: gpio@2d000000 { 371 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 372 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, 379 <&pcc4 IMX8ULP_CLK_PCTLE>; 380 clock-names = "gpio", "port"; 381 gpio-ranges = <&iomuxc1 0 32 24>; 382 }; 383 384 gpiof: gpio@2d010000 { 385 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 386 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, 393 <&pcc4 IMX8ULP_CLK_PCTLF>; 394 clock-names = "gpio", "port"; 395 gpio-ranges = <&iomuxc1 0 64 32>; 396 }; 397 398 per_bridge5: bus@2d800000 { 399 compatible = "simple-bus"; 400 reg = <0x2d800000 0x800000>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges; 404 405 cgc2: clock-controller@2da60000 { 406 compatible = "fsl,imx8ulp-cgc2"; 407 reg = <0x2da60000 0x10000>; 408 clocks = <&sosc>, <&frosc>; 409 clock-names = "sosc", "frosc"; 410 #clock-cells = <1>; 411 }; 412 413 pcc5: clock-controller@2da70000 { 414 compatible = "fsl,imx8ulp-pcc5"; 415 reg = <0x2da70000 0x10000>; 416 #clock-cells = <1>; 417 }; 418 }; 419 420 gpiod: gpio@2e200000 { 421 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 422 reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; 423 gpio-controller; 424 #gpio-cells = <2>; 425 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, 429 <&pcc5 IMX8ULP_CLK_RGPIOD>; 430 clock-names = "gpio", "port"; 431 gpio-ranges = <&iomuxc1 0 0 24>; 432 }; 433 }; 434}; 435