1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6#include <dt-bindings/clock/imx8ulp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/imx8ulp-power.h> 10 11#include "imx8ulp-pinfunc.h" 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 ethernet0 = &fec; 20 gpio0 = &gpiod; 21 gpio1 = &gpioe; 22 gpio2 = &gpiof; 23 mmc0 = &usdhc0; 24 mmc1 = &usdhc1; 25 mmc2 = &usdhc2; 26 serial0 = &lpuart4; 27 serial1 = &lpuart5; 28 serial2 = &lpuart6; 29 serial3 = &lpuart7; 30 }; 31 32 cpus { 33 #address-cells = <2>; 34 #size-cells = <0>; 35 36 A35_0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a35"; 39 reg = <0x0 0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&A35_L2>; 42 }; 43 44 A35_1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x0 0x1>; 48 enable-method = "psci"; 49 next-level-cache = <&A35_L2>; 50 }; 51 52 A35_L2: l2-cache0 { 53 compatible = "cache"; 54 cache-level = <2>; 55 }; 56 }; 57 58 gic: interrupt-controller@2d400000 { 59 compatible = "arm,gic-v3"; 60 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ 61 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 62 #interrupt-cells = <3>; 63 interrupt-controller; 64 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 65 }; 66 67 pmu { 68 compatible = "arm,cortex-a35-pmu"; 69 interrupt-parent = <&gic>; 70 interrupts = <GIC_PPI 7 71 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 72 interrupt-affinity = <&A35_0>, <&A35_1>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 timer { 81 compatible = "arm,armv8-timer"; 82 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 83 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 84 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 85 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 86 }; 87 88 frosc: clock-frosc { 89 compatible = "fixed-clock"; 90 clock-frequency = <192000000>; 91 clock-output-names = "frosc"; 92 #clock-cells = <0>; 93 }; 94 95 lposc: clock-lposc { 96 compatible = "fixed-clock"; 97 clock-frequency = <1000000>; 98 clock-output-names = "lposc"; 99 #clock-cells = <0>; 100 }; 101 102 rosc: clock-rosc { 103 compatible = "fixed-clock"; 104 clock-frequency = <32768>; 105 clock-output-names = "rosc"; 106 #clock-cells = <0>; 107 }; 108 109 sosc: clock-sosc { 110 compatible = "fixed-clock"; 111 clock-frequency = <24000000>; 112 clock-output-names = "sosc"; 113 #clock-cells = <0>; 114 }; 115 116 sram@2201f000 { 117 compatible = "mmio-sram"; 118 reg = <0x0 0x2201f000 0x0 0x1000>; 119 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0x0 0x2201f000 0x1000>; 123 124 scmi_buf: scmi-sram-section@0 { 125 compatible = "arm,scmi-shmem"; 126 reg = <0x0 0x400>; 127 }; 128 }; 129 130 firmware { 131 scmi { 132 compatible = "arm,scmi-smc"; 133 arm,smc-id = <0xc20000fe>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 shmem = <&scmi_buf>; 137 138 scmi_devpd: protocol@11 { 139 reg = <0x11>; 140 #power-domain-cells = <1>; 141 }; 142 143 scmi_sensor: protocol@15 { 144 reg = <0x15>; 145 #thermal-sensor-cells = <1>; 146 }; 147 }; 148 }; 149 150 soc: soc@0 { 151 compatible = "simple-bus"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges = <0x0 0x0 0x0 0x40000000>; 155 156 s4muap: mailbox@27020000 { 157 compatible = "fsl,imx8ulp-mu-s4"; 158 reg = <0x27020000 0x10000>; 159 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 160 #mbox-cells = <2>; 161 }; 162 163 per_bridge3: bus@29000000 { 164 compatible = "simple-bus"; 165 reg = <0x29000000 0x800000>; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 ranges; 169 170 mu: mailbox@29220000 { 171 compatible = "fsl,imx8ulp-mu"; 172 reg = <0x29220000 0x10000>; 173 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 174 #mbox-cells = <2>; 175 status = "disabled"; 176 }; 177 178 mu3: mailbox@29230000 { 179 compatible = "fsl,imx8ulp-mu"; 180 reg = <0x29230000 0x10000>; 181 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; 183 #mbox-cells = <2>; 184 status = "disabled"; 185 }; 186 187 wdog3: watchdog@292a0000 { 188 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; 189 reg = <0x292a0000 0x10000>; 190 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 192 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 193 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; 194 timeout-sec = <40>; 195 }; 196 197 cgc1: clock-controller@292c0000 { 198 compatible = "fsl,imx8ulp-cgc1"; 199 reg = <0x292c0000 0x10000>; 200 #clock-cells = <1>; 201 }; 202 203 pcc3: clock-controller@292d0000 { 204 compatible = "fsl,imx8ulp-pcc3"; 205 reg = <0x292d0000 0x10000>; 206 #clock-cells = <1>; 207 #reset-cells = <1>; 208 }; 209 210 tpm5: tpm@29340000 { 211 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; 212 reg = <0x29340000 0x1000>; 213 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&pcc3 IMX8ULP_CLK_TPM5>, 215 <&pcc3 IMX8ULP_CLK_TPM5>; 216 clock-names = "ipg", "per"; 217 status = "disabled"; 218 }; 219 220 lpi2c4: i2c@29370000 { 221 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 222 reg = <0x29370000 0x10000>; 223 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, 225 <&pcc3 IMX8ULP_CLK_LPI2C4>; 226 clock-names = "per", "ipg"; 227 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; 228 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 229 assigned-clock-rates = <48000000>; 230 status = "disabled"; 231 }; 232 233 lpi2c5: i2c@29380000 { 234 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 235 reg = <0x29380000 0x10000>; 236 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, 238 <&pcc3 IMX8ULP_CLK_LPI2C5>; 239 clock-names = "per", "ipg"; 240 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; 241 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 242 assigned-clock-rates = <48000000>; 243 status = "disabled"; 244 }; 245 246 lpuart4: serial@29390000 { 247 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 248 reg = <0x29390000 0x1000>; 249 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; 251 clock-names = "ipg"; 252 status = "disabled"; 253 }; 254 255 lpuart5: serial@293a0000 { 256 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 257 reg = <0x293a0000 0x1000>; 258 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; 260 clock-names = "ipg"; 261 status = "disabled"; 262 }; 263 264 lpspi4: spi@293b0000 { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 268 reg = <0x293b0000 0x10000>; 269 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, 271 <&pcc3 IMX8ULP_CLK_LPSPI4>; 272 clock-names = "per", "ipg"; 273 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; 274 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 275 assigned-clock-rates = <48000000>; 276 status = "disabled"; 277 }; 278 279 lpspi5: spi@293c0000 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 283 reg = <0x293c0000 0x10000>; 284 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, 286 <&pcc3 IMX8ULP_CLK_LPSPI5>; 287 clock-names = "per", "ipg"; 288 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; 289 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 290 assigned-clock-rates = <48000000>; 291 status = "disabled"; 292 }; 293 }; 294 295 per_bridge4: bus@29800000 { 296 compatible = "simple-bus"; 297 reg = <0x29800000 0x800000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges; 301 302 pcc4: clock-controller@29800000 { 303 compatible = "fsl,imx8ulp-pcc4"; 304 reg = <0x29800000 0x10000>; 305 #clock-cells = <1>; 306 #reset-cells = <1>; 307 }; 308 309 lpi2c6: i2c@29840000 { 310 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 311 reg = <0x29840000 0x10000>; 312 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, 314 <&pcc4 IMX8ULP_CLK_LPI2C6>; 315 clock-names = "per", "ipg"; 316 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; 317 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 318 assigned-clock-rates = <48000000>; 319 status = "disabled"; 320 }; 321 322 lpi2c7: i2c@29850000 { 323 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 324 reg = <0x29850000 0x10000>; 325 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, 327 <&pcc4 IMX8ULP_CLK_LPI2C7>; 328 clock-names = "per", "ipg"; 329 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; 330 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 331 assigned-clock-rates = <48000000>; 332 status = "disabled"; 333 }; 334 335 lpuart6: serial@29860000 { 336 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 337 reg = <0x29860000 0x1000>; 338 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; 340 clock-names = "ipg"; 341 status = "disabled"; 342 }; 343 344 lpuart7: serial@29870000 { 345 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 346 reg = <0x29870000 0x1000>; 347 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; 349 clock-names = "ipg"; 350 status = "disabled"; 351 }; 352 353 iomuxc1: pinctrl@298c0000 { 354 compatible = "fsl,imx8ulp-iomuxc1"; 355 reg = <0x298c0000 0x10000>; 356 }; 357 358 usdhc0: mmc@298d0000 { 359 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 360 reg = <0x298d0000 0x10000>; 361 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 363 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, 364 <&pcc4 IMX8ULP_CLK_USDHC0>; 365 clock-names = "ipg", "ahb", "per"; 366 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 367 fsl,tuning-start-tap = <20>; 368 fsl,tuning-step = <2>; 369 bus-width = <4>; 370 status = "disabled"; 371 }; 372 373 usdhc1: mmc@298e0000 { 374 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 375 reg = <0x298e0000 0x10000>; 376 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 378 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 379 <&pcc4 IMX8ULP_CLK_USDHC1>; 380 clock-names = "ipg", "ahb", "per"; 381 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 382 fsl,tuning-start-tap = <20>; 383 fsl,tuning-step = <2>; 384 bus-width = <4>; 385 status = "disabled"; 386 }; 387 388 usdhc2: mmc@298f0000 { 389 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 390 reg = <0x298f0000 0x10000>; 391 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 393 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 394 <&pcc4 IMX8ULP_CLK_USDHC2>; 395 clock-names = "ipg", "ahb", "per"; 396 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 397 fsl,tuning-start-tap = <20>; 398 fsl,tuning-step = <2>; 399 bus-width = <4>; 400 status = "disabled"; 401 }; 402 403 fec: ethernet@29950000 { 404 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; 405 reg = <0x29950000 0x10000>; 406 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "int0"; 408 fsl,num-tx-queues = <1>; 409 fsl,num-rx-queues = <1>; 410 status = "disabled"; 411 }; 412 }; 413 414 gpioe: gpio@2d000080 { 415 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 416 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; 417 gpio-controller; 418 #gpio-cells = <2>; 419 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, 423 <&pcc4 IMX8ULP_CLK_PCTLE>; 424 clock-names = "gpio", "port"; 425 gpio-ranges = <&iomuxc1 0 32 24>; 426 }; 427 428 gpiof: gpio@2d010080 { 429 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 430 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; 431 gpio-controller; 432 #gpio-cells = <2>; 433 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, 437 <&pcc4 IMX8ULP_CLK_PCTLF>; 438 clock-names = "gpio", "port"; 439 gpio-ranges = <&iomuxc1 0 64 32>; 440 }; 441 442 per_bridge5: bus@2d800000 { 443 compatible = "simple-bus"; 444 reg = <0x2d800000 0x800000>; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 ranges; 448 449 cgc2: clock-controller@2da60000 { 450 compatible = "fsl,imx8ulp-cgc2"; 451 reg = <0x2da60000 0x10000>; 452 #clock-cells = <1>; 453 }; 454 455 pcc5: clock-controller@2da70000 { 456 compatible = "fsl,imx8ulp-pcc5"; 457 reg = <0x2da70000 0x10000>; 458 #clock-cells = <1>; 459 #reset-cells = <1>; 460 }; 461 }; 462 463 gpiod: gpio@2e200080 { 464 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 465 reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, 472 <&pcc5 IMX8ULP_CLK_RGPIOD>; 473 clock-names = "gpio", "port"; 474 gpio-ranges = <&iomuxc1 0 0 24>; 475 }; 476 }; 477}; 478