188f7f6bcSTeresa Remmet// SPDX-License-Identifier: GPL-2.0 288f7f6bcSTeresa Remmet/* 388f7f6bcSTeresa Remmet * Copyright (C) 2020 PHYTEC Messtechnik GmbH 488f7f6bcSTeresa Remmet * Author: Teresa Remmet <t.remmet@phytec.de> 588f7f6bcSTeresa Remmet */ 688f7f6bcSTeresa Remmet 788f7f6bcSTeresa Remmet#include <dt-bindings/net/ti-dp83867.h> 888f7f6bcSTeresa Remmet#include "imx8mp.dtsi" 988f7f6bcSTeresa Remmet 1088f7f6bcSTeresa Remmet/ { 1188f7f6bcSTeresa Remmet model = "PHYTEC phyCORE-i.MX8MP"; 1288f7f6bcSTeresa Remmet compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 1388f7f6bcSTeresa Remmet 1488f7f6bcSTeresa Remmet aliases { 1588f7f6bcSTeresa Remmet rtc0 = &rv3028; 1688f7f6bcSTeresa Remmet rtc1 = &snvs_rtc; 1788f7f6bcSTeresa Remmet }; 1888f7f6bcSTeresa Remmet 1988f7f6bcSTeresa Remmet memory@40000000 { 2088f7f6bcSTeresa Remmet device_type = "memory"; 2188f7f6bcSTeresa Remmet reg = <0x0 0x40000000 0 0x80000000>; 2288f7f6bcSTeresa Remmet }; 2388f7f6bcSTeresa Remmet}; 2488f7f6bcSTeresa Remmet 2588f7f6bcSTeresa Remmet&A53_0 { 2688f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 2788f7f6bcSTeresa Remmet}; 2888f7f6bcSTeresa Remmet 2988f7f6bcSTeresa Remmet&A53_1 { 3088f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 3188f7f6bcSTeresa Remmet}; 3288f7f6bcSTeresa Remmet 3388f7f6bcSTeresa Remmet&A53_2 { 3488f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 3588f7f6bcSTeresa Remmet}; 3688f7f6bcSTeresa Remmet 3788f7f6bcSTeresa Remmet&A53_3 { 3888f7f6bcSTeresa Remmet cpu-supply = <&buck2>; 3988f7f6bcSTeresa Remmet}; 4088f7f6bcSTeresa Remmet 4188f7f6bcSTeresa Remmet/* ethernet 1 */ 4288f7f6bcSTeresa Remmet&fec { 4388f7f6bcSTeresa Remmet pinctrl-names = "default"; 4488f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_fec>; 4588f7f6bcSTeresa Remmet phy-mode = "rgmii-id"; 4688f7f6bcSTeresa Remmet phy-handle = <ðphy1>; 4788f7f6bcSTeresa Remmet fsl,magic-packet; 4888f7f6bcSTeresa Remmet status = "okay"; 4988f7f6bcSTeresa Remmet 5088f7f6bcSTeresa Remmet mdio { 5188f7f6bcSTeresa Remmet #address-cells = <1>; 5288f7f6bcSTeresa Remmet #size-cells = <0>; 5388f7f6bcSTeresa Remmet 5488f7f6bcSTeresa Remmet ethphy1: ethernet-phy@0 { 5588f7f6bcSTeresa Remmet compatible = "ethernet-phy-ieee802.3-c22"; 5688f7f6bcSTeresa Remmet reg = <0>; 5788f7f6bcSTeresa Remmet interrupt-parent = <&gpio1>; 5888f7f6bcSTeresa Remmet interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 5988f7f6bcSTeresa Remmet ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 6088f7f6bcSTeresa Remmet ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 6188f7f6bcSTeresa Remmet ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 6288f7f6bcSTeresa Remmet ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 6388f7f6bcSTeresa Remmet enet-phy-lane-no-swap; 6488f7f6bcSTeresa Remmet }; 6588f7f6bcSTeresa Remmet }; 6688f7f6bcSTeresa Remmet}; 6788f7f6bcSTeresa Remmet 68a4f27c75SHeiko Schocher&flexspi { 69a4f27c75SHeiko Schocher pinctrl-names = "default"; 70a4f27c75SHeiko Schocher pinctrl-0 = <&pinctrl_flexspi0>; 71a4f27c75SHeiko Schocher status = "okay"; 72a4f27c75SHeiko Schocher 73a4f27c75SHeiko Schocher som_flash: flash@0 { 74a4f27c75SHeiko Schocher compatible = "jedec,spi-nor"; 75a4f27c75SHeiko Schocher reg = <0>; 76a4f27c75SHeiko Schocher spi-max-frequency = <80000000>; 77*04aa946dSHaibo Chen spi-tx-bus-width = <1>; 78a4f27c75SHeiko Schocher spi-rx-bus-width = <4>; 79a4f27c75SHeiko Schocher }; 80a4f27c75SHeiko Schocher}; 81a4f27c75SHeiko Schocher 8288f7f6bcSTeresa Remmet&i2c1 { 8388f7f6bcSTeresa Remmet clock-frequency = <400000>; 84412627f6STeresa Remmet pinctrl-names = "default", "gpio"; 8588f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_i2c1>; 8688f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_i2c1_gpio>; 8788f7f6bcSTeresa Remmet sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 8888f7f6bcSTeresa Remmet scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 8988f7f6bcSTeresa Remmet status = "okay"; 9088f7f6bcSTeresa Remmet 9188f7f6bcSTeresa Remmet pmic: pmic@25 { 9288f7f6bcSTeresa Remmet reg = <0x25>; 9388f7f6bcSTeresa Remmet compatible = "nxp,pca9450c"; 9488f7f6bcSTeresa Remmet pinctrl-names = "default"; 9588f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_pmic>; 9688f7f6bcSTeresa Remmet interrupt-parent = <&gpio4>; 9788f7f6bcSTeresa Remmet interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 9888f7f6bcSTeresa Remmet 9988f7f6bcSTeresa Remmet regulators { 10088f7f6bcSTeresa Remmet buck1: BUCK1 { 10188f7f6bcSTeresa Remmet regulator-compatible = "BUCK1"; 10288f7f6bcSTeresa Remmet regulator-min-microvolt = <600000>; 10388f7f6bcSTeresa Remmet regulator-max-microvolt = <2187500>; 10488f7f6bcSTeresa Remmet regulator-boot-on; 10588f7f6bcSTeresa Remmet regulator-always-on; 10688f7f6bcSTeresa Remmet regulator-ramp-delay = <3125>; 10788f7f6bcSTeresa Remmet }; 10888f7f6bcSTeresa Remmet 10988f7f6bcSTeresa Remmet buck2: BUCK2 { 11088f7f6bcSTeresa Remmet regulator-compatible = "BUCK2"; 11188f7f6bcSTeresa Remmet regulator-min-microvolt = <600000>; 11288f7f6bcSTeresa Remmet regulator-max-microvolt = <2187500>; 11388f7f6bcSTeresa Remmet regulator-boot-on; 11488f7f6bcSTeresa Remmet regulator-always-on; 11588f7f6bcSTeresa Remmet regulator-ramp-delay = <3125>; 11688f7f6bcSTeresa Remmet }; 11788f7f6bcSTeresa Remmet 11888f7f6bcSTeresa Remmet buck4: BUCK4 { 11988f7f6bcSTeresa Remmet regulator-compatible = "BUCK4"; 12088f7f6bcSTeresa Remmet regulator-min-microvolt = <600000>; 12188f7f6bcSTeresa Remmet regulator-max-microvolt = <3400000>; 12288f7f6bcSTeresa Remmet regulator-boot-on; 12388f7f6bcSTeresa Remmet regulator-always-on; 12488f7f6bcSTeresa Remmet }; 12588f7f6bcSTeresa Remmet 12688f7f6bcSTeresa Remmet buck5: BUCK5 { 12788f7f6bcSTeresa Remmet regulator-compatible = "BUCK5"; 12888f7f6bcSTeresa Remmet regulator-min-microvolt = <600000>; 12988f7f6bcSTeresa Remmet regulator-max-microvolt = <3400000>; 13088f7f6bcSTeresa Remmet regulator-boot-on; 13188f7f6bcSTeresa Remmet regulator-always-on; 13288f7f6bcSTeresa Remmet }; 13388f7f6bcSTeresa Remmet 13488f7f6bcSTeresa Remmet buck6: BUCK6 { 13588f7f6bcSTeresa Remmet regulator-compatible = "BUCK6"; 13688f7f6bcSTeresa Remmet regulator-min-microvolt = <600000>; 13788f7f6bcSTeresa Remmet regulator-max-microvolt = <3400000>; 13888f7f6bcSTeresa Remmet regulator-boot-on; 13988f7f6bcSTeresa Remmet regulator-always-on; 14088f7f6bcSTeresa Remmet }; 14188f7f6bcSTeresa Remmet 14288f7f6bcSTeresa Remmet ldo1: LDO1 { 14388f7f6bcSTeresa Remmet regulator-compatible = "LDO1"; 14488f7f6bcSTeresa Remmet regulator-min-microvolt = <1600000>; 14588f7f6bcSTeresa Remmet regulator-max-microvolt = <3300000>; 14688f7f6bcSTeresa Remmet regulator-boot-on; 14788f7f6bcSTeresa Remmet regulator-always-on; 14888f7f6bcSTeresa Remmet }; 14988f7f6bcSTeresa Remmet 15088f7f6bcSTeresa Remmet ldo2: LDO2 { 15188f7f6bcSTeresa Remmet regulator-compatible = "LDO2"; 15288f7f6bcSTeresa Remmet regulator-min-microvolt = <800000>; 15388f7f6bcSTeresa Remmet regulator-max-microvolt = <1150000>; 15488f7f6bcSTeresa Remmet regulator-boot-on; 15588f7f6bcSTeresa Remmet regulator-always-on; 15688f7f6bcSTeresa Remmet }; 15788f7f6bcSTeresa Remmet 15888f7f6bcSTeresa Remmet ldo3: LDO3 { 15988f7f6bcSTeresa Remmet regulator-compatible = "LDO3"; 16088f7f6bcSTeresa Remmet regulator-min-microvolt = <800000>; 16188f7f6bcSTeresa Remmet regulator-max-microvolt = <3300000>; 16288f7f6bcSTeresa Remmet regulator-boot-on; 16388f7f6bcSTeresa Remmet regulator-always-on; 16488f7f6bcSTeresa Remmet }; 16588f7f6bcSTeresa Remmet 16688f7f6bcSTeresa Remmet ldo4: LDO4 { 16788f7f6bcSTeresa Remmet regulator-compatible = "LDO4"; 16888f7f6bcSTeresa Remmet regulator-min-microvolt = <800000>; 16988f7f6bcSTeresa Remmet regulator-max-microvolt = <3300000>; 17088f7f6bcSTeresa Remmet regulator-boot-on; 17188f7f6bcSTeresa Remmet regulator-always-on; 17288f7f6bcSTeresa Remmet }; 17388f7f6bcSTeresa Remmet 17488f7f6bcSTeresa Remmet ldo5: LDO5 { 17588f7f6bcSTeresa Remmet regulator-compatible = "LDO5"; 17688f7f6bcSTeresa Remmet regulator-min-microvolt = <1800000>; 17788f7f6bcSTeresa Remmet regulator-max-microvolt = <3300000>; 17888f7f6bcSTeresa Remmet }; 17988f7f6bcSTeresa Remmet }; 18088f7f6bcSTeresa Remmet }; 18188f7f6bcSTeresa Remmet 18288f7f6bcSTeresa Remmet eeprom@51 { 18388f7f6bcSTeresa Remmet compatible = "atmel,24c32"; 18488f7f6bcSTeresa Remmet reg = <0x51>; 18588f7f6bcSTeresa Remmet pagesize = <32>; 18688f7f6bcSTeresa Remmet }; 18788f7f6bcSTeresa Remmet 18888f7f6bcSTeresa Remmet rv3028: rtc@52 { 18988f7f6bcSTeresa Remmet compatible = "microcrystal,rv3028"; 19088f7f6bcSTeresa Remmet reg = <0x52>; 19188f7f6bcSTeresa Remmet trickle-resistor-ohms = <3000>; 19288f7f6bcSTeresa Remmet }; 19388f7f6bcSTeresa Remmet}; 19488f7f6bcSTeresa Remmet 19588f7f6bcSTeresa Remmet/* eMMC */ 19688f7f6bcSTeresa Remmet&usdhc3 { 19788f7f6bcSTeresa Remmet pinctrl-names = "default", "state_100mhz", "state_200mhz"; 19888f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_usdhc3>; 19988f7f6bcSTeresa Remmet pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 20088f7f6bcSTeresa Remmet pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 20188f7f6bcSTeresa Remmet bus-width = <8>; 20288f7f6bcSTeresa Remmet non-removable; 20388f7f6bcSTeresa Remmet status = "okay"; 20488f7f6bcSTeresa Remmet}; 20588f7f6bcSTeresa Remmet 20688f7f6bcSTeresa Remmet&wdog1 { 20788f7f6bcSTeresa Remmet pinctrl-names = "default"; 20888f7f6bcSTeresa Remmet pinctrl-0 = <&pinctrl_wdog>; 20988f7f6bcSTeresa Remmet fsl,ext-reset-output; 21088f7f6bcSTeresa Remmet status = "okay"; 21188f7f6bcSTeresa Remmet}; 21288f7f6bcSTeresa Remmet 21388f7f6bcSTeresa Remmet&iomuxc { 21488f7f6bcSTeresa Remmet pinctrl_fec: fecgrp { 21588f7f6bcSTeresa Remmet fsl,pins = < 21688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 21788f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 21888f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 21988f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 22088f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 22188f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 22288f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 22388f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 22488f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 22588f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 22688f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 22788f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 22888f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 22988f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 23088f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 23188f7f6bcSTeresa Remmet >; 23288f7f6bcSTeresa Remmet }; 23388f7f6bcSTeresa Remmet 234a4f27c75SHeiko Schocher pinctrl_flexspi0: flexspi0grp { 235a4f27c75SHeiko Schocher fsl,pins = < 236a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 237a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 238a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 239a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 240a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 241a4f27c75SHeiko Schocher MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 242a4f27c75SHeiko Schocher >; 243a4f27c75SHeiko Schocher }; 244a4f27c75SHeiko Schocher 24588f7f6bcSTeresa Remmet pinctrl_i2c1: i2c1grp { 24688f7f6bcSTeresa Remmet fsl,pins = < 24788f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 24888f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 24988f7f6bcSTeresa Remmet >; 25088f7f6bcSTeresa Remmet }; 25188f7f6bcSTeresa Remmet 25288f7f6bcSTeresa Remmet pinctrl_i2c1_gpio: i2c1gpiogrp { 25388f7f6bcSTeresa Remmet fsl,pins = < 25488f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 25588f7f6bcSTeresa Remmet MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 25688f7f6bcSTeresa Remmet >; 25788f7f6bcSTeresa Remmet }; 25888f7f6bcSTeresa Remmet 25988f7f6bcSTeresa Remmet pinctrl_pmic: pmicirqgrp { 26088f7f6bcSTeresa Remmet fsl,pins = < 26188f7f6bcSTeresa Remmet MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 26288f7f6bcSTeresa Remmet >; 26388f7f6bcSTeresa Remmet }; 26488f7f6bcSTeresa Remmet 26588f7f6bcSTeresa Remmet pinctrl_usdhc3: usdhc3grp { 26688f7f6bcSTeresa Remmet fsl,pins = < 26788f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 26888f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 26988f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 27088f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 27188f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 27288f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 27388f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 27488f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 27588f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 27688f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 27788f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 27888f7f6bcSTeresa Remmet >; 27988f7f6bcSTeresa Remmet }; 28088f7f6bcSTeresa Remmet 28188f7f6bcSTeresa Remmet pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 28288f7f6bcSTeresa Remmet fsl,pins = < 28388f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 28488f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 28588f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 28688f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 28788f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 28888f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 28988f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 29088f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 29188f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 29288f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 29388f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 29488f7f6bcSTeresa Remmet >; 29588f7f6bcSTeresa Remmet }; 29688f7f6bcSTeresa Remmet 29788f7f6bcSTeresa Remmet pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 29888f7f6bcSTeresa Remmet fsl,pins = < 29988f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 30088f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 30188f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 30288f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 30388f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 30488f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 30588f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 30688f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 30788f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 30888f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 30988f7f6bcSTeresa Remmet MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 31088f7f6bcSTeresa Remmet >; 31188f7f6bcSTeresa Remmet }; 31288f7f6bcSTeresa Remmet 31388f7f6bcSTeresa Remmet pinctrl_wdog: wdoggrp { 31488f7f6bcSTeresa Remmet fsl,pins = < 31588f7f6bcSTeresa Remmet MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 31688f7f6bcSTeresa Remmet >; 31788f7f6bcSTeresa Remmet }; 31888f7f6bcSTeresa Remmet}; 319