1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 Avnet Embedded GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9#include <dt-bindings/net/ti-dp83867.h>
10
11/ {
12	aliases {
13		rtc0 = &sys_rtc;
14		rtc1 = &snvs_rtc;
15	};
16
17	chosen {
18		stdout-path = &uart2;
19	};
20
21	reg_usb0_host_vbus: regulator-usb0-vbus {
22		compatible = "regulator-fixed";
23		regulator-name = "usb0_host_vbus";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_usb0_vbus>;
26		regulator-min-microvolt = <5000000>;
27		regulator-max-microvolt = <5000000>;
28		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
29		enable-active-high;
30	};
31
32	reg_usb1_host_vbus: regulator-usb1-vbus {
33		compatible = "regulator-fixed";
34		regulator-name = "usb1_host_vbus";
35		pinctrl-names = "default";
36		pinctrl-0 = <&pinctrl_usb1_vbus>;
37		regulator-min-microvolt = <5000000>;
38		regulator-max-microvolt = <5000000>;
39		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41	};
42
43	reg_usdhc2_vmmc: regulator-usdhc2 {
44		compatible = "regulator-fixed";
45		pinctrl-names = "default";
46		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
47		regulator-name = "VSD_3V3";
48		regulator-min-microvolt = <3300000>;
49		regulator-max-microvolt = <3300000>;
50		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51		enable-active-high;
52		startup-delay-us = <100>;
53		off-on-delay-us = <12000>;
54	};
55
56	reg_flexcan1_xceiver: regulator-flexcan1 {
57		compatible = "regulator-fixed";
58		regulator-name = "flexcan1-xceiver";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61	};
62
63	reg_flexcan2_xceiver: regulator-flexcan2 {
64		compatible = "regulator-fixed";
65		regulator-name = "flexcan2-xceiver";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68	};
69
70	lcd0_backlight: backlight-0 {
71		compatible = "pwm-backlight";
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_lcd0_backlight>;
74		pwms = <&pwm1 0 100000 0>;
75		brightness-levels = <0 255>;
76		num-interpolated-steps = <255>;
77		default-brightness-level = <255>;
78		enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
79		status = "disabled";
80	};
81
82	lcd1_backlight: backlight-1 {
83		compatible = "pwm-backlight";
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_lcd1_backlight>;
86		pwms = <&pwm2 0 100000 0>;
87		brightness-levels = <0 255>;
88		num-interpolated-steps = <255>;
89		default-brightness-level = <255>;
90		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
91		status = "disabled";
92	};
93
94	leds {
95		compatible = "gpio-leds";
96		pinctrl-names = "default";
97		pinctrl-0 = <&pinctrl_leds>;
98		status = "okay";
99
100		led-sw {
101			label = "sw-led";
102			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
103			default-state = "off";
104			linux,default-trigger = "heartbeat";
105		};
106	};
107
108	extcon_usb0: extcon-usb0 {
109		compatible = "linux,extcon-usb-gpio";
110		pinctrl-names = "default";
111		pinctrl-0 = <&pinctrl_usb0_extcon>;
112		id-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
113	};
114};
115
116&A53_0 {
117	cpu-supply = <&vcc_arm>;
118};
119
120&A53_1 {
121	cpu-supply = <&vcc_arm>;
122};
123
124&A53_2 {
125	cpu-supply = <&vcc_arm>;
126};
127
128&A53_3 {
129	cpu-supply = <&vcc_arm>;
130};
131
132&ecspi1 {
133	#address-cells = <1>;
134	#size-cells = <0>;
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_ecspi1>;
137	cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>;
138};
139
140&ecspi2 {
141	#address-cells = <1>;
142	#size-cells = <0>;
143	pinctrl-names = "default";
144	pinctrl-0 = <&pinctrl_ecspi2>;
145	cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>;
146};
147
148&eqos {
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_eqos>;
151	phy-mode = "rgmii-id";
152	phy-handle = <&ethphy0>;
153	status = "okay";
154
155	mdio {
156		compatible = "snps,dwmac-mdio";
157		#address-cells = <1>;
158		#size-cells = <0>;
159
160		ethphy0: ethernet-phy@1 {
161			compatible = "ethernet-phy-ieee802.3-c22";
162			reg = <1>;
163			eee-broken-1000t;
164			reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>;
165			reset-assert-us = <1000>;
166			reset-deassert-us = <1000>;
167			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
168			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
169			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
170			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
171		};
172	};
173};
174
175&fec {
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_fec>;
178	phy-mode = "rgmii-id";
179	phy-handle = <&ethphy1>;
180	fsl,magic-packet;
181	status = "okay";
182
183	mdio {
184		#address-cells = <1>;
185		#size-cells = <0>;
186
187		ethphy1: ethernet-phy@1 {
188			compatible = "ethernet-phy-ieee802.3-c22";
189			reg = <1>;
190			eee-broken-1000t;
191			reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>;
192			reset-assert-us = <1000>;
193			reset-deassert-us = <1000>;
194			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
195			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
196			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
197			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
198		};
199	};
200};
201
202&i2c1 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_i2c1>;
205	clock-frequency = <400000>;
206	status = "okay";
207
208	id_eeprom: eeprom@50 {
209		compatible = "atmel,24c64";
210		reg = <0x50>;
211		pagesize = <32>;
212	};
213};
214
215&i2c2 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_i2c2>;
218	clock-frequency = <400000>;
219	status = "disabled";
220};
221
222&i2c3 {
223	pinctrl-names = "default";
224	pinctrl-0 = <&pinctrl_i2c3>;
225	clock-frequency = <400000>;
226	status = "disabled";
227};
228
229&i2c4 {
230	pinctrl-names = "default";
231	pinctrl-0 = <&pinctrl_i2c4>;
232	clock-frequency = <400000>;
233	status = "disabled";
234};
235
236&i2c5 {
237	pinctrl-names = "default";
238	pinctrl-0 = <&pinctrl_i2c5>;
239	clock-frequency = <400000>;
240	status = "disabled";
241};
242
243&i2c6 {
244	pinctrl-names = "default";
245	pinctrl-0 = <&pinctrl_i2c6>;
246	clock-frequency = <400000>;
247	status = "okay";
248
249	tca6424: gpio@22 {
250		compatible = "ti,tca6424";
251		reg = <0x22>;
252		pinctrl-names = "default";
253		pinctrl-0 = <&pinctrl_tca6424>;
254		gpio-controller;
255		#gpio-cells = <2>;
256		gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",
257			"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",
258			"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",
259			"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",
260			"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",
261			"CHARGER_PRSNT#";
262		interrupt-parent = <&gpio1>;
263		interrupts = <9 IRQ_TYPE_EDGE_RISING>;
264		interrupt-controller;
265		#interrupt-cells = <2>;
266	};
267
268	dsi_lvds_bridge: bridge@2d {
269		compatible = "ti,sn65dsi83";
270		reg = <0x2d>;
271		pinctrl-names = "default";
272		pinctrl-0 = <&pinctrl_lvds_bridge>;
273		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
274		status = "disabled";
275	};
276
277	pmic: pmic@30 {
278		compatible = "ricoh,rn5t567";
279		reg = <0x30>;
280		interrupt-parent = <&tca6424>;
281		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
282
283		regulators {
284			DCDC1 {
285				regulator-name = "VCC_SOC";
286				regulator-always-on;
287				regulator-min-microvolt = <950000>;
288				regulator-max-microvolt = <950000>;
289			};
290
291			DCDC2 {
292				regulator-name = "VCC_DRAM";
293				regulator-always-on;
294				regulator-min-microvolt = <1100000>;
295				regulator-max-microvolt = <1100000>;
296			};
297
298			vcc_arm: DCDC3 {
299				regulator-name = "VCC_ARM";
300				regulator-always-on;
301				regulator-min-microvolt = <950000>;
302				regulator-max-microvolt = <950000>;
303			};
304
305			DCDC4 {
306				regulator-name = "VCC_1V8";
307				regulator-always-on;
308				regulator-min-microvolt = <1800000>;
309				regulator-max-microvolt = <1800000>;
310			};
311
312			LDO1 {
313				regulator-name = "VCC_LDO1_2V5";
314				regulator-always-on;
315				regulator-min-microvolt = <2500000>;
316				regulator-max-microvolt = <2500000>;
317			};
318
319			LDO2 {
320				regulator-name = "VCC_LDO2_1V8";
321				regulator-always-on;
322				regulator-min-microvolt = <1800000>;
323				regulator-max-microvolt = <1800000>;
324			};
325
326			LDO3 {
327				regulator-name = "VCC_ETH_2V5";
328				regulator-always-on;
329				regulator-min-microvolt = <2500000>;
330				regulator-max-microvolt = <2500000>;
331			};
332
333			LDO4 {
334				regulator-name = "VCC_DDR4_2V5";
335				regulator-always-on;
336				regulator-min-microvolt = <2500000>;
337				regulator-max-microvolt = <2500000>;
338			};
339
340			LDO5 {
341				regulator-name = "VCC_LDO5_1V8";
342				regulator-always-on;
343				regulator-min-microvolt = <1800000>;
344				regulator-max-microvolt = <1800000>;
345			};
346
347			LDORTC1 {
348				regulator-name = "VCC_SNVS_1V8";
349				regulator-always-on;
350				regulator-min-microvolt = <1800000>;
351				regulator-max-microvolt = <1800000>;
352			};
353
354			LDORTC2 {
355				regulator-name = "VCC_SNVS_3V3";
356				regulator-always-on;
357				regulator-min-microvolt = <3300000>;
358				regulator-max-microvolt = <3300000>;
359			};
360		};
361	};
362
363	sys_rtc: rtc@32 {
364		compatible = "ricoh,r2221tl";
365		reg = <0x32>;
366		interrupt-parent = <&tca6424>;
367		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
368	};
369
370	tmp_sensor: temperature-sensor@71 {
371		compatible = "ti,tmp103";
372		reg = <0x71>;
373	};
374};
375
376&flexcan1 {
377	pinctrl-names = "default";
378	pinctrl-0 = <&pinctrl_flexcan1>;
379	xceiver-supply = <&reg_flexcan1_xceiver>;
380	status = "disabled";
381};
382
383&flexcan2 {
384	pinctrl-names = "default";
385	pinctrl-0 = <&pinctrl_flexcan2>;
386	xceiver-supply = <&reg_flexcan2_xceiver>;
387	status = "disabled";
388};
389
390&flexspi {
391	pinctrl-names = "default";
392	pinctrl-0 = <&pinctrl_flexspi0>;
393	status = "okay";
394
395	qspi_flash: flash@0 {
396		compatible = "jedec,spi-nor";
397		reg = <0>;
398		#address-cells = <1>;
399		#size-cells = <1>;
400		spi-max-frequency = <80000000>;
401		spi-tx-bus-width = <4>;
402		spi-rx-bus-width = <4>;
403	};
404};
405
406&pwm1 {
407	pinctrl-names = "default";
408	pinctrl-0 = <&pinctrl_pwm1>;
409	status = "disabled";
410};
411
412&pwm2 {
413	pinctrl-names = "default";
414	pinctrl-0 = <&pinctrl_pwm2>;
415	status = "disabled";
416};
417
418&pwm3 {
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_pwm3>;
421	status = "disabled";
422};
423
424&pwm4 {
425	pinctrl-names = "default";
426	pinctrl-0 = <&pinctrl_pwm4>;
427	status = "disabled";
428};
429
430&snvs_pwrkey {
431	status = "okay";
432};
433
434&uart1 {
435	pinctrl-names = "default";
436	pinctrl-0 = <&pinctrl_uart1>;
437	status = "okay";
438};
439
440&uart2 {
441	pinctrl-names = "default";
442	pinctrl-0 = <&pinctrl_uart2>;
443	uart-has-rtscts;
444	status = "okay";
445};
446
447&uart3 {
448	pinctrl-names = "default";
449	pinctrl-0 = <&pinctrl_uart3>;
450	uart-has-rtscts;
451	status = "okay";
452};
453
454&uart4 {
455	pinctrl-names = "default";
456	pinctrl-0 = <&pinctrl_uart4>;
457	status = "disabled";
458};
459
460&usb3_phy0 {
461	vbus-supply = <&reg_usb0_host_vbus>;
462	status = "okay";
463};
464
465&usb3_phy1 {
466	vbus-supply = <&reg_usb1_host_vbus>;
467	status = "okay";
468};
469
470&usb3_0 {
471	status = "okay";
472};
473
474&usb3_1 {
475	status = "okay";
476};
477
478&usb_dwc3_0 {
479	dr_mode = "otg";
480	hnp-disable;
481	srp-disable;
482	adp-disable;
483	extcon = <&extcon_usb0>;
484	status = "okay";
485};
486
487&usb_dwc3_1 {
488	dr_mode = "host";
489	status = "okay";
490};
491
492&usdhc2 {
493	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
494	assigned-clock-rates = <400000000>;
495	pinctrl-names = "default", "state_100mhz", "state_200mhz";
496	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
497	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
498	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
499	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
500	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
501	bus-width = <4>;
502	vmmc-supply = <&reg_usdhc2_vmmc>;
503	status = "okay";
504};
505
506&usdhc3 {
507	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
508	assigned-clock-rates = <400000000>;
509	pinctrl-names = "default", "state_100mhz", "state_200mhz";
510	pinctrl-0 = <&pinctrl_usdhc3>;
511	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
512	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
513	bus-width = <8>;
514	non-removable;
515	status = "okay";
516};
517
518&wdog1 {
519	pinctrl-names = "default";
520	pinctrl-0 = <&pinctrl_wdog>;
521	fsl,ext-reset-output;
522	status = "okay";
523};
524
525&iomuxc {
526	pinctrl_ecspi1: ecspi1grp {
527		fsl,pins =
528			<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82>,
529			<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82>,
530			<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82>,
531			<MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0		0x40000>,
532			<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x40000>;
533	};
534
535	pinctrl_ecspi2: ecspi2grp {
536		fsl,pins =
537			<MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82>,
538			<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82>,
539			<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82>,
540			<MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000>,
541			<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x40000>;
542	};
543
544	pinctrl_eqos: eqosgrp {
545		fsl,pins =
546			<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3>,
547			<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3>,
548			<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91>,
549			<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91>,
550			<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91>,
551			<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91>,
552			<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91>,
553			<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91>,
554			<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f>,
555			<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f>,
556			<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f>,
557			<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f>,
558			<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f>,
559			<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f>;
560	};
561
562	pinctrl_fec: fecgrp {
563		fsl,pins =
564			<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3>,
565			<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3>,
566			<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91>,
567			<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91>,
568			<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91>,
569			<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91>,
570			<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91>,
571			<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91>,
572			<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x1f>,
573			<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x1f>,
574			<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x1f>,
575			<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x1f>,
576			<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f>,
577			<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x1f>;
578	};
579
580	pinctrl_flexcan1: flexcan1grp {
581		fsl,pins =
582			<MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154>,
583			<MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154>;
584	};
585
586	pinctrl_flexcan2: flexcan2grp {
587		fsl,pins =
588			<MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154>,
589			<MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154>;
590	};
591
592	pinctrl_flexspi0: flexspi0grp {
593		fsl,pins =
594			<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2>,
595			<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
596			<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
597			<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
598			<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
599			<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>,
600			<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x19>;
601	};
602
603	pinctrl_i2c1: i2c1grp {
604		fsl,pins =
605			<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3>,
606			<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3>;
607	};
608
609	pinctrl_i2c2: i2c2grp {
610		fsl,pins =
611			<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3>,
612			<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3>;
613	};
614
615	pinctrl_i2c3: i2c3grp {
616		fsl,pins =
617			<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3>,
618			<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3>;
619	};
620
621	pinctrl_i2c4: i2c4grp {
622		fsl,pins =
623			<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c3>,
624			<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c3>;
625	};
626
627	pinctrl_i2c5: i2c5grp {
628		fsl,pins =
629			<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL		0x400001c3>,
630			<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001c3>;
631	};
632
633	pinctrl_i2c6: i2c6grp {
634		fsl,pins =
635			<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001c3>,
636			<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c3>;
637	};
638
639	pinctrl_lcd0_backlight: lcd0-backlightgrp {
640		fsl,pins =
641			<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x41>;
642	};
643
644	pinctrl_lcd1_backlight: lcd1-backlightgrp {
645		fsl,pins =
646			<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x41>;
647	};
648
649	pinctrl_leds: ledsgrp {
650		fsl,pins =
651			<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x19>;
652	};
653
654	pinctrl_lvds_bridge: lvds-bridgegrp {
655		fsl,pins =
656			<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x41>;
657	};
658
659	pinctrl_pwm1: pwm1grp {
660		fsl,pins =
661			<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116>;
662	};
663
664	pinctrl_pwm2: pwm2grp {
665		fsl,pins =
666			<MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116>;
667	};
668
669	pinctrl_pwm3: pwm3grp {
670		fsl,pins =
671			<MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT		0x116>;
672	};
673
674	pinctrl_pwm4: pwm4grp {
675		fsl,pins =
676			<MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0x116>;
677	};
678
679	pinctrl_tca6424: tca6424grp {
680		fsl,pins =
681			<MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x41>;
682	};
683
684	pinctrl_uart1: uart1grp {
685		fsl,pins =
686			<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x49>,
687			<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x49>;
688	};
689
690	pinctrl_uart2: uart2grp {
691		fsl,pins =
692			<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x1c4>,
693			<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x1c4>,
694			<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49>,
695			<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49>;
696	};
697
698	pinctrl_uart3: uart3grp {
699		fsl,pins =
700			<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4>,
701			<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x1c4>,
702			<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49>,
703			<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49>;
704	};
705
706	pinctrl_uart4: uart4grp {
707		fsl,pins =
708			<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49>,
709			<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49>;
710	};
711
712	pinctrl_usb0_extcon: usb0-extcongrp {
713		fsl,pins =
714			<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x19>;
715	};
716
717	pinctrl_usb0_vbus: usb0-vbusgrp {
718		fsl,pins =
719			<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x19>;
720	};
721
722	pinctrl_usb1_vbus: usb1-vbusgrp {
723		fsl,pins =
724			<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x19>;
725	};
726
727	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
728		fsl,pins =
729			<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4>,
730			<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x1c4>;
731	};
732
733	pinctrl_usdhc2: usdhc2grp {
734		fsl,pins =
735			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190>,
736			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0>,
737			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0>,
738			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0>,
739			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0>,
740			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0>,
741			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
742	};
743
744	pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {
745		fsl,pins =
746			<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41>;
747	};
748
749	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
750		fsl,pins =
751			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194>,
752			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4>,
753			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4>,
754			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4>,
755			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4>,
756			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4>,
757			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
758	};
759
760	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
761		fsl,pins =
762			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196>,
763			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6>,
764			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6>,
765			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6>,
766			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6>,
767			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6>,
768			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
769	};
770
771	pinctrl_usdhc3: usdhc3grp {
772		fsl,pins =
773			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190>,
774			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0>,
775			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0>,
776			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0>,
777			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0>,
778			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0>,
779			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0>,
780			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0>,
781			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0>,
782			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0>,
783			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190>;
784	};
785
786	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
787		fsl,pins =
788			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
789			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
790			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4>,
791			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4>,
792			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4>,
793			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4>,
794			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4>,
795			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4>,
796			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4>,
797			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
798			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194>;
799	};
800
801	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
802		fsl,pins =
803			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196>,
804			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6>,
805			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6>,
806			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6>,
807			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6>,
808			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6>,
809			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6>,
810			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6>,
811			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6>,
812			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6>,
813			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196>;
814	};
815
816	pinctrl_wdog: wdoggrp {
817		fsl,pins =
818			<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6>;
819	};
820};
821