1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp.dtsi"
7
8/ {
9	model = "DH electronics i.MX8M Plus DHCOM SoM";
10	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
11
12	aliases {
13		ethernet0 = &eqos;
14		ethernet1 = &fec;
15		rtc0 = &rv3032;
16		rtc1 = &snvs_rtc;
17		spi0 = &flexspi;
18	};
19
20	memory@40000000 {
21		device_type = "memory";
22		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
23		reg = <0x0 0x40000000 0 0x08000000>;
24	};
25
26	reg_eth_vio: regulator-eth-vio {
27		compatible = "regulator-fixed";
28		gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
29		pinctrl-0 = <&pinctrl_enet_vio>;
30		pinctrl-names = "default";
31		regulator-always-on;
32		regulator-boot-on;
33		regulator-min-microvolt = <3300000>;
34		regulator-max-microvolt = <3300000>;
35		regulator-name = "eth_vio";
36		vin-supply = <&buck4>;
37	};
38
39	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40		compatible = "regulator-fixed";
41		enable-active-high;
42		gpio = <&gpio2 19 0>; /* SD2_RESET */
43		off-on-delay-us = <12000>;
44		pinctrl-names = "default";
45		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46		regulator-max-microvolt = <3300000>;
47		regulator-min-microvolt = <3300000>;
48		regulator-name = "VDD_3V3_SD";
49		startup-delay-us = <100>;
50		vin-supply = <&buck4>;
51	};
52};
53
54&A53_0 {
55	cpu-supply = <&buck2>;
56};
57
58&A53_1 {
59	cpu-supply = <&buck2>;
60};
61
62&A53_2 {
63	cpu-supply = <&buck2>;
64};
65
66&A53_3 {
67	cpu-supply = <&buck2>;
68};
69
70&ecspi1 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_ecspi1>;
73	cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
74	status = "disabled";
75};
76
77&ecspi2 {
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_ecspi2>;
80	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
81	status = "disabled";
82};
83
84&eqos {	/* First ethernet */
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_eqos>;
87	phy-handle = <&ethphy0g>;
88	phy-mode = "rgmii-id";
89	status = "okay";
90
91	mdio {
92		compatible = "snps,dwmac-mdio";
93		#address-cells = <1>;
94		#size-cells = <0>;
95
96		/* Up to one of these two PHYs may be populated. */
97		ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
98			compatible = "ethernet-phy-id0007.c110",
99				     "ethernet-phy-ieee802.3-c22";
100			interrupt-parent = <&gpio3>;
101			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
102			pinctrl-0 = <&pinctrl_ethphy0>;
103			pinctrl-names = "default";
104			reg = <1>;
105			reset-assert-us = <1000>;
106			reset-deassert-us = <1000>;
107			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
108			/* Non-default PHY population option. */
109			status = "disabled";
110		};
111
112		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
113			compatible = "ethernet-phy-id0022.1642",
114				     "ethernet-phy-ieee802.3-c22";
115			interrupt-parent = <&gpio3>;
116			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
117			micrel,led-mode = <0>;
118			pinctrl-0 = <&pinctrl_ethphy0>;
119			pinctrl-names = "default";
120			reg = <5>;
121			reset-assert-us = <1000>;
122			reset-deassert-us = <1000>;
123			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
124			/* Default PHY population option. */
125			status = "okay";
126		};
127	};
128};
129
130&fec {	/* Second ethernet */
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_fec>;
133	phy-handle = <&ethphy1f>;
134	phy-mode = "rgmii";
135	fsl,magic-packet;
136	status = "okay";
137
138	mdio {
139		#address-cells = <1>;
140		#size-cells = <0>;
141
142		/* Up to one PHY may be populated. */
143		ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
144			compatible = "ethernet-phy-id0007.c110",
145				     "ethernet-phy-ieee802.3-c22";
146			interrupt-parent = <&gpio4>;
147			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
148			pinctrl-0 = <&pinctrl_ethphy1>;
149			pinctrl-names = "default";
150			reg = <1>;
151			reset-assert-us = <1000>;
152			reset-deassert-us = <1000>;
153			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
154			/* Non-default PHY population option. */
155			status = "disabled";
156		};
157	};
158};
159
160&flexcan1 {
161	pinctrl-names = "default";
162	pinctrl-0 = <&pinctrl_flexcan1>;
163	status = "disabled";
164};
165
166&flexcan2 {
167	pinctrl-names = "default";
168	pinctrl-0 = <&pinctrl_flexcan2>;
169	status = "disabled";
170};
171
172&flexspi {
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_flexspi>;
175	status = "okay";
176
177	flash@0 {	/* W25Q128JWPIM */
178		compatible = "jedec,spi-nor";
179		reg = <0>;
180		spi-max-frequency = <80000000>;
181		spi-tx-bus-width = <4>;
182		spi-rx-bus-width = <4>;
183	};
184};
185
186&gpio1 {
187	gpio-line-names =
188		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
189		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
190		"", "", "", "", "", "", "", "",
191		"", "", "", "", "", "", "", "";
192};
193
194&gpio2 {
195	gpio-line-names =
196		"", "", "", "", "", "", "", "",
197		"", "", "", "DHCOM-K", "", "", "", "",
198		"", "", "", "", "DHCOM-INT", "", "", "",
199		"", "", "", "", "", "", "", "";
200};
201
202&gpio3 {
203	gpio-line-names =
204		"", "", "", "", "", "", "", "",
205		"", "", "", "", "", "", "SOM-HW0", "",
206		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
207		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
208};
209
210&gpio4 {
211	gpio-line-names =
212		"", "", "", "", "", "", "", "",
213		"", "", "", "", "", "", "", "",
214		"", "", "", "SOM-HW1", "", "", "", "",
215		"", "", "", "DHCOM-D", "", "", "", "";
216};
217
218&gpio5 {
219	gpio-line-names =
220		"", "", "DHCOM-C", "", "", "", "", "",
221		"", "", "", "", "", "", "", "",
222		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
223		"", "", "", "", "", "", "", "";
224};
225
226&i2c3 {
227	clock-frequency = <100000>;
228	pinctrl-names = "default", "gpio";
229	pinctrl-0 = <&pinctrl_i2c3>;
230	pinctrl-1 = <&pinctrl_i2c3_gpio>;
231	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
232	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
233	status = "okay";
234
235	pmic: pmic@25 {
236		compatible = "nxp,pca9450c";
237		reg = <0x25>;
238		pinctrl-names = "default";
239		pinctrl-0 = <&pinctrl_pmic>;
240		interrupt-parent = <&gpio1>;
241		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
242		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
243
244		/*
245		 * i.MX 8M Plus Data Sheet for Consumer Products
246		 * 3.1.4 Operating ranges
247		 * MIMX8ML8CVNKZAB
248		 */
249		regulators {
250			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
251				regulator-compatible = "BUCK1";
252				regulator-min-microvolt = <850000>;
253				regulator-max-microvolt = <1000000>;
254				regulator-ramp-delay = <3125>;
255				regulator-always-on;
256				regulator-boot-on;
257			};
258
259			buck2: BUCK2 {	/* VDD_ARM */
260				regulator-compatible = "BUCK2";
261				regulator-min-microvolt = <850000>;
262				regulator-max-microvolt = <1000000>;
263				regulator-ramp-delay = <3125>;
264				regulator-always-on;
265				regulator-boot-on;
266			};
267
268			buck4: BUCK4 {	/* VDD_3V3 */
269				regulator-compatible = "BUCK4";
270				regulator-min-microvolt = <3300000>;
271				regulator-max-microvolt = <3300000>;
272				regulator-always-on;
273				regulator-boot-on;
274			};
275
276			buck5: BUCK5 {	/* VDD_1V8 */
277				regulator-compatible = "BUCK5";
278				regulator-min-microvolt = <1800000>;
279				regulator-max-microvolt = <1800000>;
280				regulator-always-on;
281				regulator-boot-on;
282			};
283
284			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
285				regulator-compatible = "BUCK6";
286				regulator-min-microvolt = <1100000>;
287				regulator-max-microvolt = <1100000>;
288				regulator-always-on;
289				regulator-boot-on;
290			};
291
292			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
293				regulator-compatible = "LDO1";
294				regulator-min-microvolt = <1800000>;
295				regulator-max-microvolt = <1800000>;
296				regulator-always-on;
297				regulator-boot-on;
298			};
299
300			ldo3: LDO3 {	/* VDDA_1V8 */
301				regulator-compatible = "LDO3";
302				regulator-min-microvolt = <1800000>;
303				regulator-max-microvolt = <1800000>;
304				regulator-always-on;
305				regulator-boot-on;
306			};
307
308			ldo4: LDO4 {	/* PMIC_LDO4 */
309				regulator-compatible = "LDO4";
310				regulator-min-microvolt = <3300000>;
311				regulator-max-microvolt = <3300000>;
312			};
313
314			ldo5: LDO5 {	/* NVCC_SD2 */
315				regulator-compatible = "LDO5";
316				regulator-min-microvolt = <1800000>;
317				regulator-max-microvolt = <3300000>;
318			};
319		};
320	};
321
322	adc@48 {
323		compatible = "ti,tla2024";
324		reg = <0x48>;
325		#address-cells = <1>;
326		#size-cells = <0>;
327
328		channel@0 {	/* Voltage over AIN0 and AIN1. */
329			reg = <0>;
330		};
331
332		channel@1 {	/* Voltage over AIN0 and AIN3. */
333			reg = <1>;
334		};
335
336		channel@2 {	/* Voltage over AIN1 and AIN3. */
337			reg = <2>;
338		};
339
340		channel@3 {	/* Voltage over AIN2 and AIN3. */
341			reg = <3>;
342		};
343
344		channel@4 {	/* Voltage over AIN0 and GND. */
345			reg = <4>;
346		};
347
348		channel@5 {	/* Voltage over AIN1 and GND. */
349			reg = <5>;
350		};
351
352		channel@6 {	/* Voltage over AIN2 and GND. */
353			reg = <6>;
354		};
355
356		channel@7 {	/* Voltage over AIN3 and GND. */
357			reg = <7>;
358		};
359	};
360
361	touchscreen@49 {
362		compatible = "ti,tsc2004";
363		reg = <0x49>;
364		interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
365		pinctrl-names = "default";
366		pinctrl-0 = <&pinctrl_touch>;
367		vio-supply = <&buck4>;
368	};
369
370	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */
371		compatible = "atmel,24c02";
372		pagesize = <16>;
373		reg = <0x50>;
374	};
375
376	rv3032: rtc@51 {
377		compatible = "microcrystal,rv3032";
378		reg = <0x51>;
379		interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
380		pinctrl-names = "default";
381		pinctrl-0 = <&pinctrl_rtc>;
382	};
383
384	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */
385		compatible = "atmel,24c02";
386		pagesize = <16>;
387		reg = <0x53>;
388	};
389};
390
391&i2c4 {
392	clock-frequency = <100000>;
393	pinctrl-names = "default", "gpio";
394	pinctrl-0 = <&pinctrl_i2c4>;
395	pinctrl-1 = <&pinctrl_i2c4_gpio>;
396	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
397	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
398	status = "okay";
399};
400
401&i2c5 {	/* HDMI EDID bus */
402	clock-frequency = <100000>;
403	pinctrl-names = "default", "gpio";
404	pinctrl-0 = <&pinctrl_i2c5>;
405	pinctrl-1 = <&pinctrl_i2c5_gpio>;
406	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
407	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
408	status = "okay";
409};
410
411&pwm1 {
412	pinctrl-0 = <&pinctrl_pwm1>;
413	pinctrl-names = "default";
414	status = "disabled";
415};
416
417&uart1 {
418	/* CA53 console */
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_uart1>;
421	status = "okay";
422};
423
424&uart2 {
425	/* Bluetooth */
426	pinctrl-names = "default";
427	pinctrl-0 = <&pinctrl_uart2>;
428	uart-has-rtscts;
429	status = "okay";
430
431	/*
432	 * PLL3 at 320 MHz supplies UART2 root with 64 MHz clock,
433	 * which with 16x oversampling yields 4 Mbdps baud base,
434	 * which is exactly the maximum rate supported by muRata
435	 * 2AE bluetooth UART.
436	 */
437	assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>;
438	assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>;
439	assigned-clock-rates = <320000000>, <64000000>;
440
441	bluetooth {
442		pinctrl-names = "default";
443		pinctrl-0 = <&pinctrl_uart2_bt>;
444		compatible = "cypress,cyw4373a0-bt";
445		shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
446		max-speed = <4000000>;
447	};
448};
449
450&uart3 {
451	pinctrl-names = "default";
452	pinctrl-0 = <&pinctrl_uart3>;
453	uart-has-rtscts;
454	status = "okay";
455};
456
457&uart4 {
458	pinctrl-names = "default";
459	pinctrl-0 = <&pinctrl_uart4>;
460	status = "okay";
461};
462
463&usb3_phy0 {
464	status = "okay";
465};
466
467&usb3_0 {
468	status = "okay";
469};
470
471&usb_dwc3_0 {
472	pinctrl-names = "default";
473	pinctrl-0 = <&pinctrl_usb0_vbus>;
474	dr_mode = "otg";
475	status = "okay";
476};
477
478&usb3_phy1 {
479	status = "okay";
480};
481
482&usb3_1 {
483	status = "okay";
484};
485
486&usb_dwc3_1 {
487	pinctrl-names = "default";
488	pinctrl-0 = <&pinctrl_usb1_vbus>;
489	dr_mode = "host";
490	status = "okay";
491};
492
493/* SDIO WiFi */
494&usdhc1 {
495	pinctrl-names = "default", "state_100mhz", "state_200mhz";
496	pinctrl-0 = <&pinctrl_usdhc1>;
497	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
498	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
499	vmmc-supply = <&buck4>;
500	bus-width = <4>;
501	non-removable;
502	cap-power-off-card;
503	keep-power-in-suspend;
504	status = "okay";
505
506	#address-cells = <1>;
507	#size-cells = <0>;
508
509	brcmf: bcrmf@1 {	/* muRata 2AE */
510		reg = <1>;
511		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
512		/*
513		 * The "host-wake" interrupt output is by default not
514		 * connected to the SoC, but can be connected on to
515		 * SoC pin on the carrier board.
516		 */
517		reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
518	};
519};
520
521/* SD slot */
522&usdhc2 {
523	pinctrl-names = "default", "state_100mhz", "state_200mhz";
524	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
525	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
526	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
527	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
528	vmmc-supply = <&reg_usdhc2_vmmc>;
529	bus-width = <4>;
530	status = "okay";
531};
532
533/* eMMC */
534&usdhc3 {
535	pinctrl-names = "default", "state_100mhz", "state_200mhz";
536	pinctrl-0 = <&pinctrl_usdhc3>;
537	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
538	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
539	vmmc-supply = <&buck4>;
540	vqmmc-supply = <&buck5>;
541	bus-width = <8>;
542	non-removable;
543	status = "okay";
544};
545
546&wdog1 {
547	pinctrl-names = "default";
548	pinctrl-0 = <&pinctrl_wdog>;
549	fsl,ext-reset-output;
550	status = "okay";
551};
552
553&iomuxc {
554	pinctrl-0 = <&pinctrl_hog_base
555		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
556		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
557		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
558		     &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
559		     /* GPIO_M is connected to CLKOUT2 */
560		     &pinctrl_dhcom_int>;
561	pinctrl-names = "default";
562
563	pinctrl_dhcom_a: dhcom-a-grp {
564		fsl,pins = <
565			/* ENET_QOS_EVENT0-OUT */
566			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2
567		>;
568	};
569
570	pinctrl_dhcom_b: dhcom-b-grp {
571		fsl,pins = <
572			/* ENET_QOS_EVENT0-IN */
573			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2
574		>;
575	};
576
577	pinctrl_dhcom_c: dhcom-c-grp {
578		fsl,pins = <
579			/* GPIO_C */
580			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2
581		>;
582	};
583
584	pinctrl_dhcom_d: dhcom-d-grp {
585		fsl,pins = <
586			/* GPIO_D */
587			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2
588		>;
589	};
590
591	pinctrl_dhcom_e: dhcom-e-grp {
592		fsl,pins = <
593			/* GPIO_E */
594			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2
595		>;
596	};
597
598	pinctrl_dhcom_f: dhcom-f-grp {
599		fsl,pins = <
600			/* GPIO_F */
601			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2
602		>;
603	};
604
605	pinctrl_dhcom_g: dhcom-g-grp {
606		fsl,pins = <
607			/* GPIO_G */
608			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2
609		>;
610	};
611
612	pinctrl_dhcom_h: dhcom-h-grp {
613		fsl,pins = <
614			/* GPIO_H */
615			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2
616		>;
617	};
618
619	pinctrl_dhcom_i: dhcom-i-grp {
620		fsl,pins = <
621			/* CSI1_SYNC */
622			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
623		>;
624	};
625
626	pinctrl_dhcom_j: dhcom-j-grp {
627		fsl,pins = <
628			/* CSIx_#RST */
629			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2
630		>;
631	};
632
633	pinctrl_dhcom_k: dhcom-k-grp {
634		fsl,pins = <
635			/* CSIx_PWDN */
636			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2
637		>;
638	};
639
640	pinctrl_dhcom_l: dhcom-l-grp {
641		fsl,pins = <
642			/* CSI2_SYNC */
643			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2
644		>;
645	};
646
647	pinctrl_dhcom_int: dhcom-int-grp {
648		fsl,pins = <
649			/* INT_HIGHEST_PRIO */
650			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2
651		>;
652	};
653
654	pinctrl_hog_base: dhcom-hog-base-grp {
655		fsl,pins = <
656			/* GPIOs for memory coding */
657			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080
658			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080
659			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080
660			/* GPIOs for hardware coding */
661			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080
662			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080
663			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080
664		>;
665	};
666
667	pinctrl_ecspi1: dhcom-ecspi1-grp {
668		fsl,pins = <
669			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
670			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
671			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
672			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
673		>;
674	};
675
676	pinctrl_ecspi2: dhcom-ecspi2-grp {
677		fsl,pins = <
678			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
679			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
680			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
681			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
682		>;
683	};
684
685	pinctrl_eqos: dhcom-eqos-grp {	/* RGMII */
686		fsl,pins = <
687			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
688			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
689			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
690			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
691			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
692			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
693			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
694			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
695			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
696			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
697			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
698			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
699			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
700			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
701		>;
702	};
703
704	pinctrl_enet_vio: dhcom-enet-vio-grp {
705		fsl,pins = <
706			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x22
707		>;
708	};
709
710	pinctrl_ethphy0: dhcom-ethphy0-grp {
711		fsl,pins = <
712			/* ENET1_#RST Reset */
713			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22
714			/* ENET1_#INT Interrupt */
715			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22
716		>;
717	};
718
719	pinctrl_ethphy1: dhcom-ethphy1-grp {
720		fsl,pins = <
721			/* ENET1_#RST Reset */
722			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11
723			/* ENET1_#INT Interrupt */
724			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11
725		>;
726	};
727
728	pinctrl_fec: dhcom-fec-grp {
729		fsl,pins = <
730			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f
731			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
732			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
733			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
734			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
735			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
736			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
737			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
738			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
739			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
740			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
741			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
742			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
743			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
744			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
745			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f
746		>;
747	};
748
749	pinctrl_flexcan1: dhcom-flexcan1-grp {
750		fsl,pins = <
751			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
752			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
753		>;
754	};
755
756	pinctrl_flexcan2: dhcom-flexcan2-grp {
757		fsl,pins = <
758			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154
759			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154
760		>;
761	};
762
763	pinctrl_flexspi: dhcom-flexspi-grp {
764		fsl,pins = <
765			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
766			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
767			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
768			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
769			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
770			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
771		>;
772	};
773
774	pinctrl_hdmi: dhcom-hdmi-grp {
775		fsl,pins = <
776			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
777			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
778		>;
779	};
780
781	pinctrl_i2c3: dhcom-i2c3-grp {
782		fsl,pins = <
783			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
784			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
785		>;
786	};
787
788	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
789		fsl,pins = <
790			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
791			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
792		>;
793	};
794
795	pinctrl_i2c4: dhcom-i2c4-grp {
796		fsl,pins = <
797			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084
798			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084
799		>;
800	};
801
802	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
803		fsl,pins = <
804			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84
805			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84
806		>;
807	};
808
809	pinctrl_i2c5: dhcom-i2c5-grp {
810		fsl,pins = <
811			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
812			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
813		>;
814	};
815
816	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
817		fsl,pins = <
818			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
819			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
820		>;
821	};
822
823	pinctrl_pmic: dhcom-pmic-grp {
824		fsl,pins = <
825			/* PMIC_nINT */
826			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
827		>;
828	};
829
830	pinctrl_pwm1: dhcom-pwm1-grp {
831		fsl,pins = <
832			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6
833		>;
834	};
835
836	pinctrl_rtc: dhcom-rtc-grp {
837		fsl,pins = <
838			/* RTC_#INT Interrupt */
839			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x40000080
840		>;
841	};
842
843	pinctrl_touch: dhcom-touch-grp {
844		fsl,pins = <
845			/* #TOUCH_INT */
846			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080
847		>;
848	};
849
850	pinctrl_uart1: dhcom-uart1-grp {
851		fsl,pins = <
852			/* Console UART */
853			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49
854			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49
855			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
856			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
857		>;
858	};
859
860	pinctrl_uart2: dhcom-uart2-grp {
861		fsl,pins = <
862			/* Bluetooth UART */
863			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
864			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
865			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
866			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
867		>;
868	};
869
870	pinctrl_uart2_bt: dhcom-uart2-bt-grp {
871		fsl,pins = <
872			/* BT_REG_EN */
873			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
874		>;
875	};
876
877	pinctrl_uart3: dhcom-uart3-grp {
878		fsl,pins = <
879			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49
880			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49
881			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49
882			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49
883		>;
884	};
885
886	pinctrl_uart4: dhcom-uart4-grp {
887		fsl,pins = <
888			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
889			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
890		>;
891	};
892
893	pinctrl_usb0_vbus: dhcom-usb0-grp {
894		fsl,pins = <
895			MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID		0x0
896		>;
897	};
898
899	pinctrl_usb1_vbus: dhcom-usb1-grp {
900		fsl,pins = <
901			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6
902			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80
903		>;
904	};
905
906	pinctrl_usdhc1: dhcom-usdhc1-grp {
907		fsl,pins = <
908			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
909			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
910			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
911			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
912			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
913			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
914			/* WL_REG_EN */
915			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
916		>;
917	};
918
919	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
920		fsl,pins = <
921			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
922			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
923			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
924			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
925			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
926			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
927			/* WL_REG_EN */
928			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
929		>;
930	};
931
932	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
933		fsl,pins = <
934			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
935			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
936			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
937			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
938			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
939			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
940			/* WL_REG_EN */
941			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
942		>;
943	};
944
945	pinctrl_usdhc2: dhcom-usdhc2-grp {
946		fsl,pins = <
947			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
948			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
949			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
950			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
951			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
952			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
953			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
954		>;
955	};
956
957	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
958		fsl,pins = <
959			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
960			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
961			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
962			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
963			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
964			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
965			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
966		>;
967	};
968
969	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
970		fsl,pins = <
971			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
972			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
973			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
974			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
975			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
976			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
977			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
978		>;
979	};
980
981	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
982		fsl,pins = <
983			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
984		>;
985	};
986
987	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
988		fsl,pins = <
989			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
990		>;
991	};
992
993	pinctrl_usdhc3: dhcom-usdhc3-grp {
994		fsl,pins = <
995			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
996			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
997			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
998			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
999			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
1000			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
1001			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
1002			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
1003			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
1004			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
1005			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
1006			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1007		>;
1008	};
1009
1010	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1011		fsl,pins = <
1012			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
1013			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
1014			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
1015			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
1016			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
1017			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
1018			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
1019			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
1020			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
1021			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
1022			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
1023			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1024		>;
1025	};
1026
1027	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1028		fsl,pins = <
1029			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
1030			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
1031			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
1032			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
1033			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
1034			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
1035			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
1036			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
1037			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
1038			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
1039			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
1040			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1041		>;
1042	};
1043
1044	pinctrl_wdog: dhcom-wdog-grp {
1045		fsl,pins = <
1046			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
1047		>;
1048	};
1049};
1050