|
Revision tags: v6.6.36, v6.6.35, v6.6.34 |
|
| #
625c4fda |
| 15-Jun-2024 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Fix TC9595 input clock on DH i.MX8M Plus DHCOM SoM
[ Upstream commit c03984d43a9dd9282da54ccf275419f666029452 ]
The IMX8MP_CLK_CLKOUT2 supplies the TC9595 bridge with 13 MHz ref
arm64: dts: imx8mp: Fix TC9595 input clock on DH i.MX8M Plus DHCOM SoM
[ Upstream commit c03984d43a9dd9282da54ccf275419f666029452 ]
The IMX8MP_CLK_CLKOUT2 supplies the TC9595 bridge with 13 MHz reference
clock. The IMX8MP_CLK_CLKOUT2 is supplied from IMX8MP_AUDIO_PLL2_OUT.
The IMX8MP_CLK_CLKOUT2 operates only as a power-of-two divider, and the
current 156 MHz is not power-of-two divisible to achieve 13 MHz.
To achieve 13 MHz output from IMX8MP_CLK_CLKOUT2, set IMX8MP_AUDIO_PLL2_OUT
to 208 MHz, because 208 MHz / 16 = 13 MHz.
Fixes: 20d0b83e712b ("arm64: dts: imx8mp: Add TC9595 bridge on DH electronics i.MX8M Plus DHCOM")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24, v6.6.23 |
|
| #
332af18d |
| 24-Feb-2024 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Fix TC9595 reset GPIO on DH i.MX8M Plus DHCOM SoM
[ Upstream commit 418a7fc5397719c4b8f50eaeca6694879f89a6ec ]
The TC9595 reset GPIO is SAI1_RXC / GPIO4_IO01, fix the DT accordi
arm64: dts: imx8mp: Fix TC9595 reset GPIO on DH i.MX8M Plus DHCOM SoM
[ Upstream commit 418a7fc5397719c4b8f50eaeca6694879f89a6ec ]
The TC9595 reset GPIO is SAI1_RXC / GPIO4_IO01, fix the DT accordingly.
The SAI5_RXD0 / GPIO3_IO21 is thus far unused TC9595 interrupt line.
Fixes: 20d0b83e712b ("arm64: dts: imx8mp: Add TC9595 bridge on DH electronics i.MX8M Plus DHCOM")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stable-dep-of: c03984d43a9d ("arm64: dts: imx8mp: Fix TC9595 input clock on DH i.MX8M Plus DHCOM SoM")
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31 |
|
| #
04a0b7b8 |
| 27-May-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Enable SAI audio on MX8MP DHCOM PDK2 and PDK3
Add SAI I2S and audio bindings on MX8MP DHCOM PDK2 and PDK3.
The VDDA is supplied from on-carrier-board regulator, the VDDIO
is sup
arm64: dts: imx8mp: Enable SAI audio on MX8MP DHCOM PDK2 and PDK3
Add SAI I2S and audio bindings on MX8MP DHCOM PDK2 and PDK3.
The VDDA is supplied from on-carrier-board regulator, the VDDIO
is supplied from always-on on-SoM regulator. Except for different
I2C bus used to connect the codec, the implementation is virtually
identical on both carrier boards.
Align regulator-avdd name to regulator-3p3vdd on PDK3, since this
is the VDDA supply and it is the same on both carrier boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.1.30, v6.1.29 |
|
| #
20d0b83e |
| 15-May-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Add TC9595 bridge on DH electronics i.MX8M Plus DHCOM
Add TC9595 DSI-to-DPI and DSI-to-(e)DP bridge to
DH electronics i.MX8M Plus DHCOM SoM . The bridge
is populated on the SoM,
arm64: dts: imx8mp: Add TC9595 bridge on DH electronics i.MX8M Plus DHCOM
Add TC9595 DSI-to-DPI and DSI-to-(e)DP bridge to
DH electronics i.MX8M Plus DHCOM SoM . The bridge
is populated on the SoM, but disabled by default
unless used for display output.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2 |
|
| #
3d274f8b |
| 17-Feb-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for
arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
f4662e0c |
| 17-Feb-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Add EQoS RMII pin mux on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux setting
arm64: dts: imx8mp: Add EQoS RMII pin mux on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
15a03a22 |
| 17-Feb-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Adjust EQoS PHY address on i.MX8MP DHCOM
The current variant of the SoM has LAN8740Ai PHY connected to EQoS
strapped to MDIO address 0 , adjust the MDIO address to match the
hard
arm64: dts: imx8mp: Adjust EQoS PHY address on i.MX8MP DHCOM
The current variant of the SoM has LAN8740Ai PHY connected to EQoS
strapped to MDIO address 0 , adjust the MDIO address to match the
hardware.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
6ef01842 |
| 17-Feb-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Adjust EQoS reset comment on i.MX8MP DHCOM
Fix copy-paste error in the EQoS reset comment, align with SoM schematic.
No functional change.
Signed-off-by: Marek Vasut <marex@denx
arm64: dts: imx8mp: Adjust EQoS reset comment on i.MX8MP DHCOM
Fix copy-paste error in the EQoS reset comment, align with SoM schematic.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
3e431f25 |
| 17-Feb-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Update GPIO M to CLKOUT1 on DH electronics i.MX8M Plus DHCOM and PDK2
The GPIO M SoM pin is connected to CLKOUT1, while CLKOUT2 is used as a supply
for TC9595 bridge chip clock.
arm64: dts: imx8mp: Update GPIO M to CLKOUT1 on DH electronics i.MX8M Plus DHCOM and PDK2
The GPIO M SoM pin is connected to CLKOUT1, while CLKOUT2 is used as a supply
for TC9595 bridge chip clock. Update the comment. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7 |
|
| #
a51e4fac |
| 17-Jan-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Drop sd-vsel-gpios from i.MX8M Plus DHCOM SoM
The VSELECT pin is configured as MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT
and not as a GPIO, drop the bogus sd-vsel-gpios property as
arm64: dts: imx8mp: Drop sd-vsel-gpios from i.MX8M Plus DHCOM SoM
The VSELECT pin is configured as MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT
and not as a GPIO, drop the bogus sd-vsel-gpios property as the eSDHC
block handles the VSELECT pin on its own.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
| #
ab156707 |
| 17-Jan-2023 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM
Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz
instead of 64 MHz to obtain suitable block clo
arm64: dts: imx8mp: Improve bluetooth UART on DH electronics i.MX8M Plus DHCOM
Use PLL1_80M instead of PLL3 to drive UART2 clock divided down to 80 MHz
instead of 64 MHz to obtain suitable block clock for exact 4 Mbdps, which
is the maximum supported baud rate by the muRata 2AE BT UART.
The difference here is that at 64 MHz UART block clock, the clock with are
divided by 16 (due to oversampling) to 4 MHz and the baud rate generator
then needs to be set to UBIR+1/UBMR+1 = 1/1 to yield 4 Mbdps . In case of
80 MHz UART block clock divided by 16 to 5 MHz, the baud rate generator
needs to be set to UBIR+1/UBMR+1 = 4/5 to yield 4 Mbdps .
Both options are valid and yield the same result, except using the PLL1_80M
output requires fewer clock tree changes, since the PLL1 already generates
the 80 MHz usable for UART, which frees the PLL3 for other uses.
Suggested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14 |
|
| #
db9dd598 |
| 15-Dec-2022 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Drop deprecated regulator-compatible from i.MX8M Plus DHCOM
The "regulator-compatible" property is deprecated and unused, as the
match happens on the node name in Linux of_regula
arm64: dts: imx8mp: Drop deprecated regulator-compatible from i.MX8M Plus DHCOM
The "regulator-compatible" property is deprecated and unused, as the
match happens on the node name in Linux of_regulator_match() in case
the property is not present. Drop the deprecated property from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77 |
|
| #
a9404a89 |
| 31-Oct-2022 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Bind bluetooth UART on DH electronics i.MX8M Plus DHCOM
The i.MX8MP DHCOM SoM does contain muRata 2AE WiFi+BT chip, bind the
bluetooth to UART2 using btbcm and hci_bcm drivers. U
arm64: dts: imx8mp: Bind bluetooth UART on DH electronics i.MX8M Plus DHCOM
The i.MX8MP DHCOM SoM does contain muRata 2AE WiFi+BT chip, bind the
bluetooth to UART2 using btbcm and hci_bcm drivers. Use PLL3 to drive
UART2 clock divided down to 64 MHz to obtain suitable block clock for
exact 4 Mbdps, which is the maximum supported baud rate by the muRata
2AE BT UART.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61 |
|
| #
17fe7251 |
| 12-Aug-2022 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Fix I2C5 GPIO assignment on i.MX8M Plus DHCOM
Fix copy-paste error of the I2C5 bus recovery GPIO assignment,
the I2C5 GPIOs are on gpio3 instead of gpio5.
Fixes: 8d6712695bc8e (
arm64: dts: imx8mp: Fix I2C5 GPIO assignment on i.MX8M Plus DHCOM
Fix copy-paste error of the I2C5 bus recovery GPIO assignment,
the I2C5 GPIOs are on gpio3 instead of gpio5.
Fixes: 8d6712695bc8e ("arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.60, v5.15.59, v5.19, v5.15.58 |
|
| #
c7afab4a |
| 23-Jul-2022 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Adjust ECSPI1 pinmux on i.MX8M Plus DHCOM
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly.
Fixes: 8d6712695bc8e ("arm64: dts: imx8mp: Add support for D
arm64: dts: imx8mp: Adjust ECSPI1 pinmux on i.MX8M Plus DHCOM
The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly.
Fixes: 8d6712695bc8e ("arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
|
Revision tags: v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47 |
|
| #
8d671269 |
| 13-Jun-2022 |
Marek Vasut <marex@denx.de> |
arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board.
Currently supported are serial console, EQoS
arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR, CAN.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|