1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp.dtsi"
7
8/ {
9	model = "DH electronics i.MX8M Plus DHCOM SoM";
10	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
11
12	aliases {
13		ethernet0 = &eqos;
14		ethernet1 = &fec;
15		rtc0 = &rv3032;
16		rtc1 = &snvs_rtc;
17		spi0 = &flexspi;
18	};
19
20	memory@40000000 {
21		device_type = "memory";
22		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
23		reg = <0x0 0x40000000 0 0x08000000>;
24	};
25
26	reg_eth_vio: regulator-eth-vio {
27		compatible = "regulator-fixed";
28		gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
29		pinctrl-0 = <&pinctrl_enet_vio>;
30		pinctrl-names = "default";
31		regulator-always-on;
32		regulator-boot-on;
33		regulator-min-microvolt = <3300000>;
34		regulator-max-microvolt = <3300000>;
35		regulator-name = "eth_vio";
36		vin-supply = <&buck4>;
37	};
38
39	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40		compatible = "regulator-fixed";
41		enable-active-high;
42		gpio = <&gpio2 19 0>; /* SD2_RESET */
43		off-on-delay-us = <12000>;
44		pinctrl-names = "default";
45		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46		regulator-max-microvolt = <3300000>;
47		regulator-min-microvolt = <3300000>;
48		regulator-name = "VDD_3V3_SD";
49		startup-delay-us = <100>;
50		vin-supply = <&buck4>;
51	};
52
53	reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo {	/* VDD_3V3_AWO */
54		compatible = "regulator-fixed";
55		regulator-always-on;
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "VDD_3P3V_AWO";
59	};
60};
61
62&A53_0 {
63	cpu-supply = <&buck2>;
64};
65
66&A53_1 {
67	cpu-supply = <&buck2>;
68};
69
70&A53_2 {
71	cpu-supply = <&buck2>;
72};
73
74&A53_3 {
75	cpu-supply = <&buck2>;
76};
77
78&ecspi1 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_ecspi1>;
81	cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
82	status = "disabled";
83};
84
85&ecspi2 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_ecspi2>;
88	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
89	status = "disabled";
90};
91
92&eqos {	/* First ethernet */
93	pinctrl-names = "default";
94	pinctrl-0 = <&pinctrl_eqos_rgmii>;
95	phy-handle = <&ethphy0g>;
96	phy-mode = "rgmii-id";
97	status = "okay";
98
99	mdio {
100		compatible = "snps,dwmac-mdio";
101		#address-cells = <1>;
102		#size-cells = <0>;
103
104		/* Up to one of these two PHYs may be populated. */
105		ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
106			compatible = "ethernet-phy-id0007.c110",
107				     "ethernet-phy-ieee802.3-c22";
108			interrupt-parent = <&gpio3>;
109			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
110			pinctrl-0 = <&pinctrl_ethphy0>;
111			pinctrl-names = "default";
112			reg = <0>;
113			reset-assert-us = <1000>;
114			reset-deassert-us = <1000>;
115			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
116			/* Non-default PHY population option. */
117			status = "disabled";
118		};
119
120		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
121			compatible = "ethernet-phy-id0022.1642",
122				     "ethernet-phy-ieee802.3-c22";
123			interrupt-parent = <&gpio3>;
124			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
125			micrel,led-mode = <0>;
126			pinctrl-0 = <&pinctrl_ethphy0>;
127			pinctrl-names = "default";
128			reg = <5>;
129			reset-assert-us = <1000>;
130			reset-deassert-us = <1000>;
131			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
132			/* Default PHY population option. */
133			status = "okay";
134		};
135	};
136};
137
138&fec {	/* Second ethernet */
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_fec_rmii>;
141	phy-handle = <&ethphy1f>;
142	phy-mode = "rmii";
143	fsl,magic-packet;
144	status = "okay";
145
146	mdio {
147		#address-cells = <1>;
148		#size-cells = <0>;
149
150		/* Up to one PHY may be populated. */
151		ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
152			compatible = "ethernet-phy-id0007.c110",
153				     "ethernet-phy-ieee802.3-c22";
154			interrupt-parent = <&gpio4>;
155			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
156			pinctrl-0 = <&pinctrl_ethphy1>;
157			pinctrl-names = "default";
158			reg = <1>;
159			reset-assert-us = <1000>;
160			reset-deassert-us = <1000>;
161			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
162			/* Non-default PHY population option. */
163			status = "disabled";
164		};
165	};
166};
167
168&flexcan1 {
169	pinctrl-names = "default";
170	pinctrl-0 = <&pinctrl_flexcan1>;
171	status = "disabled";
172};
173
174&flexcan2 {
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_flexcan2>;
177	status = "disabled";
178};
179
180&flexspi {
181	pinctrl-names = "default";
182	pinctrl-0 = <&pinctrl_flexspi>;
183	status = "okay";
184
185	flash@0 {	/* W25Q128JWPIM */
186		compatible = "jedec,spi-nor";
187		reg = <0>;
188		spi-max-frequency = <80000000>;
189		spi-tx-bus-width = <4>;
190		spi-rx-bus-width = <4>;
191	};
192};
193
194&gpio1 {
195	gpio-line-names =
196		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
197		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
198		"", "", "", "", "", "", "", "",
199		"", "", "", "", "", "", "", "";
200};
201
202&gpio2 {
203	gpio-line-names =
204		"", "", "", "", "", "", "", "",
205		"", "", "", "DHCOM-K", "", "", "", "",
206		"", "", "", "", "DHCOM-INT", "", "", "",
207		"", "", "", "", "", "", "", "";
208};
209
210&gpio3 {
211	gpio-line-names =
212		"", "", "", "", "", "", "", "",
213		"", "", "", "", "", "", "SOM-HW0", "",
214		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
215		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
216};
217
218&gpio4 {
219	gpio-line-names =
220		"", "", "", "", "", "", "", "",
221		"", "", "", "", "", "", "", "",
222		"", "", "", "SOM-HW1", "", "", "", "",
223		"", "", "", "DHCOM-D", "", "", "", "";
224};
225
226&gpio5 {
227	gpio-line-names =
228		"", "", "DHCOM-C", "", "", "", "", "",
229		"", "", "", "", "", "", "", "",
230		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
231		"", "", "", "", "", "", "", "";
232};
233
234&i2c3 {
235	clock-frequency = <100000>;
236	pinctrl-names = "default", "gpio";
237	pinctrl-0 = <&pinctrl_i2c3>;
238	pinctrl-1 = <&pinctrl_i2c3_gpio>;
239	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
240	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
241	status = "okay";
242
243	tc_bridge: bridge@f {
244		compatible = "toshiba,tc9595", "toshiba,tc358767";
245		pinctrl-names = "default";
246		pinctrl-0 = <&pinctrl_tc9595>;
247		reg = <0xf>;
248		clock-names = "ref";
249		clocks = <&clk IMX8MP_CLK_CLKOUT2>;
250		assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
251				  <&clk IMX8MP_CLK_CLKOUT2>,
252				  <&clk IMX8MP_AUDIO_PLL2_OUT>;
253		assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
254		assigned-clock-rates = <13000000>, <13000000>, <208000000>;
255		reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
256		status = "disabled";
257
258		ports {
259			#address-cells = <1>;
260			#size-cells = <0>;
261
262			port@0 {
263				reg = <0>;
264
265				tc_bridge_in: endpoint {
266					data-lanes = <1 2 3 4>;
267					remote-endpoint = <&dsi_out>;
268				};
269			};
270		};
271	};
272
273	pmic: pmic@25 {
274		compatible = "nxp,pca9450c";
275		reg = <0x25>;
276		pinctrl-names = "default";
277		pinctrl-0 = <&pinctrl_pmic>;
278		interrupt-parent = <&gpio1>;
279		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
280
281		/*
282		 * i.MX 8M Plus Data Sheet for Consumer Products
283		 * 3.1.4 Operating ranges
284		 * MIMX8ML8CVNKZAB
285		 */
286		regulators {
287			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
288				regulator-min-microvolt = <850000>;
289				regulator-max-microvolt = <1000000>;
290				regulator-ramp-delay = <3125>;
291				regulator-always-on;
292				regulator-boot-on;
293			};
294
295			buck2: BUCK2 {	/* VDD_ARM */
296				regulator-min-microvolt = <850000>;
297				regulator-max-microvolt = <1000000>;
298				regulator-ramp-delay = <3125>;
299				regulator-always-on;
300				regulator-boot-on;
301			};
302
303			buck4: BUCK4 {	/* VDD_3V3 */
304				regulator-min-microvolt = <3300000>;
305				regulator-max-microvolt = <3300000>;
306				regulator-always-on;
307				regulator-boot-on;
308			};
309
310			buck5: BUCK5 {	/* VDD_1V8 */
311				regulator-min-microvolt = <1800000>;
312				regulator-max-microvolt = <1800000>;
313				regulator-always-on;
314				regulator-boot-on;
315			};
316
317			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
318				regulator-min-microvolt = <1100000>;
319				regulator-max-microvolt = <1100000>;
320				regulator-always-on;
321				regulator-boot-on;
322			};
323
324			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
325				regulator-min-microvolt = <1800000>;
326				regulator-max-microvolt = <1800000>;
327				regulator-always-on;
328				regulator-boot-on;
329			};
330
331			ldo3: LDO3 {	/* VDDA_1V8 */
332				regulator-min-microvolt = <1800000>;
333				regulator-max-microvolt = <1800000>;
334				regulator-always-on;
335				regulator-boot-on;
336			};
337
338			ldo4: LDO4 {	/* PMIC_LDO4 */
339				regulator-min-microvolt = <3300000>;
340				regulator-max-microvolt = <3300000>;
341			};
342
343			ldo5: LDO5 {	/* NVCC_SD2 */
344				regulator-min-microvolt = <1800000>;
345				regulator-max-microvolt = <3300000>;
346			};
347		};
348	};
349
350	adc@48 {
351		compatible = "ti,tla2024";
352		reg = <0x48>;
353		#address-cells = <1>;
354		#size-cells = <0>;
355
356		channel@0 {	/* Voltage over AIN0 and AIN1. */
357			reg = <0>;
358		};
359
360		channel@1 {	/* Voltage over AIN0 and AIN3. */
361			reg = <1>;
362		};
363
364		channel@2 {	/* Voltage over AIN1 and AIN3. */
365			reg = <2>;
366		};
367
368		channel@3 {	/* Voltage over AIN2 and AIN3. */
369			reg = <3>;
370		};
371
372		channel@4 {	/* Voltage over AIN0 and GND. */
373			reg = <4>;
374		};
375
376		channel@5 {	/* Voltage over AIN1 and GND. */
377			reg = <5>;
378		};
379
380		channel@6 {	/* Voltage over AIN2 and GND. */
381			reg = <6>;
382		};
383
384		channel@7 {	/* Voltage over AIN3 and GND. */
385			reg = <7>;
386		};
387	};
388
389	touchscreen@49 {
390		compatible = "ti,tsc2004";
391		reg = <0x49>;
392		interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
393		pinctrl-names = "default";
394		pinctrl-0 = <&pinctrl_touch>;
395		vio-supply = <&buck4>;
396	};
397
398	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */
399		compatible = "atmel,24c02";
400		pagesize = <16>;
401		reg = <0x50>;
402	};
403
404	rv3032: rtc@51 {
405		compatible = "microcrystal,rv3032";
406		reg = <0x51>;
407		interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
408		pinctrl-names = "default";
409		pinctrl-0 = <&pinctrl_rtc>;
410	};
411
412	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */
413		compatible = "atmel,24c02";
414		pagesize = <16>;
415		reg = <0x53>;
416	};
417};
418
419&i2c4 {
420	clock-frequency = <100000>;
421	pinctrl-names = "default", "gpio";
422	pinctrl-0 = <&pinctrl_i2c4>;
423	pinctrl-1 = <&pinctrl_i2c4_gpio>;
424	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
425	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
426	status = "okay";
427};
428
429&i2c5 {	/* HDMI EDID bus */
430	clock-frequency = <100000>;
431	pinctrl-names = "default", "gpio";
432	pinctrl-0 = <&pinctrl_i2c5>;
433	pinctrl-1 = <&pinctrl_i2c5_gpio>;
434	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
435	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
436	status = "okay";
437};
438
439&mipi_dsi {
440	samsung,burst-clock-frequency = <160000000>;
441	samsung,esc-clock-frequency = <10000000>;
442
443	ports {
444		port@1 {
445			reg = <1>;
446
447			dsi_out: endpoint {
448				data-lanes = <1 2 3 4>;
449				remote-endpoint = <&tc_bridge_in>;
450			};
451		};
452	};
453};
454
455&pwm1 {
456	pinctrl-0 = <&pinctrl_pwm1>;
457	pinctrl-names = "default";
458	status = "disabled";
459};
460
461&uart1 {
462	/* CA53 console */
463	pinctrl-names = "default";
464	pinctrl-0 = <&pinctrl_uart1>;
465	status = "okay";
466};
467
468&uart2 {
469	/* Bluetooth */
470	pinctrl-names = "default";
471	pinctrl-0 = <&pinctrl_uart2>;
472	uart-has-rtscts;
473	status = "okay";
474
475	/*
476	 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
477	 * which with 16x oversampling yields 5 Mbdps baud base,
478	 * which can be well divided by 5/4 to achieve 4 Mbdps,
479	 * which is exactly the maximum rate supported by muRata
480	 * 2AE bluetooth UART.
481	 */
482	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
483	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
484	assigned-clock-rates = <80000000>;
485
486	bluetooth {
487		pinctrl-names = "default";
488		pinctrl-0 = <&pinctrl_uart2_bt>;
489		compatible = "cypress,cyw4373a0-bt";
490		shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
491		max-speed = <4000000>;
492	};
493};
494
495&uart3 {
496	pinctrl-names = "default";
497	pinctrl-0 = <&pinctrl_uart3>;
498	uart-has-rtscts;
499	status = "okay";
500};
501
502&uart4 {
503	pinctrl-names = "default";
504	pinctrl-0 = <&pinctrl_uart4>;
505	status = "okay";
506};
507
508&usb3_phy0 {
509	status = "okay";
510};
511
512&usb3_0 {
513	status = "okay";
514};
515
516&usb_dwc3_0 {
517	pinctrl-names = "default";
518	pinctrl-0 = <&pinctrl_usb0_vbus>;
519	dr_mode = "otg";
520	status = "okay";
521};
522
523&usb3_phy1 {
524	status = "okay";
525};
526
527&usb3_1 {
528	status = "okay";
529};
530
531&usb_dwc3_1 {
532	pinctrl-names = "default";
533	pinctrl-0 = <&pinctrl_usb1_vbus>;
534	dr_mode = "host";
535	status = "okay";
536};
537
538/* SDIO WiFi */
539&usdhc1 {
540	pinctrl-names = "default", "state_100mhz", "state_200mhz";
541	pinctrl-0 = <&pinctrl_usdhc1>;
542	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
543	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
544	vmmc-supply = <&buck4>;
545	bus-width = <4>;
546	non-removable;
547	cap-power-off-card;
548	keep-power-in-suspend;
549	status = "okay";
550
551	#address-cells = <1>;
552	#size-cells = <0>;
553
554	brcmf: bcrmf@1 {	/* muRata 2AE */
555		reg = <1>;
556		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
557		/*
558		 * The "host-wake" interrupt output is by default not
559		 * connected to the SoC, but can be connected on to
560		 * SoC pin on the carrier board.
561		 */
562		reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
563	};
564};
565
566/* SD slot */
567&usdhc2 {
568	pinctrl-names = "default", "state_100mhz", "state_200mhz";
569	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
570	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
571	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
572	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
573	vmmc-supply = <&reg_usdhc2_vmmc>;
574	bus-width = <4>;
575	status = "okay";
576};
577
578/* eMMC */
579&usdhc3 {
580	pinctrl-names = "default", "state_100mhz", "state_200mhz";
581	pinctrl-0 = <&pinctrl_usdhc3>;
582	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
583	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
584	vmmc-supply = <&buck4>;
585	vqmmc-supply = <&buck5>;
586	bus-width = <8>;
587	non-removable;
588	status = "okay";
589};
590
591&wdog1 {
592	pinctrl-names = "default";
593	pinctrl-0 = <&pinctrl_wdog>;
594	fsl,ext-reset-output;
595	status = "okay";
596};
597
598&iomuxc {
599	pinctrl-0 = <&pinctrl_hog_base
600		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
601		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
602		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
603		     &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
604		     /* GPIO_M is connected to CLKOUT1 */
605		     &pinctrl_dhcom_int>;
606	pinctrl-names = "default";
607
608	pinctrl_dhcom_a: dhcom-a-grp {
609		fsl,pins = <
610			/* ENET_QOS_EVENT0-OUT */
611			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2
612		>;
613	};
614
615	pinctrl_dhcom_b: dhcom-b-grp {
616		fsl,pins = <
617			/* ENET_QOS_EVENT0-IN */
618			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2
619		>;
620	};
621
622	pinctrl_dhcom_c: dhcom-c-grp {
623		fsl,pins = <
624			/* GPIO_C */
625			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2
626		>;
627	};
628
629	pinctrl_dhcom_d: dhcom-d-grp {
630		fsl,pins = <
631			/* GPIO_D */
632			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2
633		>;
634	};
635
636	pinctrl_dhcom_e: dhcom-e-grp {
637		fsl,pins = <
638			/* GPIO_E */
639			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2
640		>;
641	};
642
643	pinctrl_dhcom_f: dhcom-f-grp {
644		fsl,pins = <
645			/* GPIO_F */
646			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2
647		>;
648	};
649
650	pinctrl_dhcom_g: dhcom-g-grp {
651		fsl,pins = <
652			/* GPIO_G */
653			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2
654		>;
655	};
656
657	pinctrl_dhcom_h: dhcom-h-grp {
658		fsl,pins = <
659			/* GPIO_H */
660			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2
661		>;
662	};
663
664	pinctrl_dhcom_i: dhcom-i-grp {
665		fsl,pins = <
666			/* CSI1_SYNC */
667			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
668		>;
669	};
670
671	pinctrl_dhcom_j: dhcom-j-grp {
672		fsl,pins = <
673			/* CSIx_#RST */
674			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2
675		>;
676	};
677
678	pinctrl_dhcom_k: dhcom-k-grp {
679		fsl,pins = <
680			/* CSIx_PWDN */
681			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2
682		>;
683	};
684
685	pinctrl_dhcom_l: dhcom-l-grp {
686		fsl,pins = <
687			/* CSI2_SYNC */
688			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2
689		>;
690	};
691
692	pinctrl_dhcom_int: dhcom-int-grp {
693		fsl,pins = <
694			/* INT_HIGHEST_PRIO */
695			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2
696		>;
697	};
698
699	pinctrl_hog_base: dhcom-hog-base-grp {
700		fsl,pins = <
701			/* GPIOs for memory coding */
702			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080
703			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080
704			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080
705			/* GPIOs for hardware coding */
706			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080
707			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080
708			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080
709		>;
710	};
711
712	pinctrl_ecspi1: dhcom-ecspi1-grp {
713		fsl,pins = <
714			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
715			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
716			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
717			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
718		>;
719	};
720
721	pinctrl_ecspi2: dhcom-ecspi2-grp {
722		fsl,pins = <
723			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
724			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
725			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
726			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
727		>;
728	};
729
730	pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp {	/* RGMII */
731		fsl,pins = <
732			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
733			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
734			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
735			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
736			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
737			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
738			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
739			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
740			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
741			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
742			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
743			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
744			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
745			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
746		>;
747	};
748
749	pinctrl_eqos_rmii: dhcom-eqos-rmii-grp {	/* RMII */
750		fsl,pins = <
751			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
752			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
753			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
754			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
755			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
756			MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER		0x1f
757			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
758			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
759			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
760			/* Clock */
761			MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK	0x4000001f
762		>;
763	};
764
765	pinctrl_enet_vio: dhcom-enet-vio-grp {
766		fsl,pins = <
767			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x22
768		>;
769	};
770
771	pinctrl_ethphy0: dhcom-ethphy0-grp {
772		fsl,pins = <
773			/* ENET_QOS_#RST Reset */
774			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22
775			/* ENET_QOS_#INT Interrupt */
776			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22
777		>;
778	};
779
780	pinctrl_ethphy1: dhcom-ethphy1-grp {
781		fsl,pins = <
782			/* ENET1_#RST Reset */
783			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11
784			/* ENET1_#INT Interrupt */
785			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11
786		>;
787	};
788
789	pinctrl_fec_rgmii: dhcom-fec-rgmii-grp {	/* RGMII */
790		fsl,pins = <
791			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f
792			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
793			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
794			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
795			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
796			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
797			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
798			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
799			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
800			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
801			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
802			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
803			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
804			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
805			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
806			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f
807		>;
808	};
809
810	pinctrl_fec_rmii: dhcom-fec-rmii-grp {	/* RMII */
811		fsl,pins = <
812			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
813			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
814			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
815			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
816			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
817			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x91
818			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
819			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
820			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
821			/* Clock */
822			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x4000001f
823		>;
824	};
825
826	pinctrl_flexcan1: dhcom-flexcan1-grp {
827		fsl,pins = <
828			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
829			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
830		>;
831	};
832
833	pinctrl_flexcan2: dhcom-flexcan2-grp {
834		fsl,pins = <
835			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154
836			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154
837		>;
838	};
839
840	pinctrl_flexspi: dhcom-flexspi-grp {
841		fsl,pins = <
842			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
843			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
844			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
845			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
846			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
847			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
848		>;
849	};
850
851	pinctrl_hdmi: dhcom-hdmi-grp {
852		fsl,pins = <
853			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
854			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
855		>;
856	};
857
858	pinctrl_i2c3: dhcom-i2c3-grp {
859		fsl,pins = <
860			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
861			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
862		>;
863	};
864
865	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
866		fsl,pins = <
867			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
868			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
869		>;
870	};
871
872	pinctrl_i2c4: dhcom-i2c4-grp {
873		fsl,pins = <
874			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084
875			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084
876		>;
877	};
878
879	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
880		fsl,pins = <
881			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84
882			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84
883		>;
884	};
885
886	pinctrl_i2c5: dhcom-i2c5-grp {
887		fsl,pins = <
888			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
889			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
890		>;
891	};
892
893	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
894		fsl,pins = <
895			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
896			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
897		>;
898	};
899
900	pinctrl_pmic: dhcom-pmic-grp {
901		fsl,pins = <
902			/* PMIC_nINT */
903			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
904		>;
905	};
906
907	pinctrl_pwm1: dhcom-pwm1-grp {
908		fsl,pins = <
909			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6
910		>;
911	};
912
913	pinctrl_rtc: dhcom-rtc-grp {
914		fsl,pins = <
915			/* RTC_#INT Interrupt */
916			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x40000080
917		>;
918	};
919
920	pinctrl_tc9595: dhcom-tc9595-grp {
921		fsl,pins = <
922			/* RESET_DSIBRIDGE */
923			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x40000146
924			/* DSI-CONV_INT Interrupt */
925			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x141
926		>;
927	};
928
929	pinctrl_sai3: dhcom-sai3-grp {
930		fsl,pins = <
931			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
932			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
933			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
934			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
935		>;
936	};
937
938	pinctrl_touch: dhcom-touch-grp {
939		fsl,pins = <
940			/* #TOUCH_INT */
941			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080
942		>;
943	};
944
945	pinctrl_uart1: dhcom-uart1-grp {
946		fsl,pins = <
947			/* Console UART */
948			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49
949			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49
950			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
951			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
952		>;
953	};
954
955	pinctrl_uart2: dhcom-uart2-grp {
956		fsl,pins = <
957			/* Bluetooth UART */
958			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
959			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
960			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
961			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
962		>;
963	};
964
965	pinctrl_uart2_bt: dhcom-uart2-bt-grp {
966		fsl,pins = <
967			/* BT_REG_EN */
968			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
969		>;
970	};
971
972	pinctrl_uart3: dhcom-uart3-grp {
973		fsl,pins = <
974			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49
975			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49
976			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49
977			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49
978		>;
979	};
980
981	pinctrl_uart4: dhcom-uart4-grp {
982		fsl,pins = <
983			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
984			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
985		>;
986	};
987
988	pinctrl_usb0_vbus: dhcom-usb0-grp {
989		fsl,pins = <
990			MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID		0x0
991		>;
992	};
993
994	pinctrl_usb1_vbus: dhcom-usb1-grp {
995		fsl,pins = <
996			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6
997			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80
998		>;
999	};
1000
1001	pinctrl_usdhc1: dhcom-usdhc1-grp {
1002		fsl,pins = <
1003			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
1004			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
1005			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
1006			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
1007			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
1008			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
1009			/* WL_REG_EN */
1010			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
1011		>;
1012	};
1013
1014	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1015		fsl,pins = <
1016			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
1017			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
1018			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
1019			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
1020			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
1021			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
1022			/* WL_REG_EN */
1023			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
1024		>;
1025	};
1026
1027	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1028		fsl,pins = <
1029			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
1030			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
1031			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
1032			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
1033			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
1034			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
1035			/* WL_REG_EN */
1036			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
1037		>;
1038	};
1039
1040	pinctrl_usdhc2: dhcom-usdhc2-grp {
1041		fsl,pins = <
1042			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
1043			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
1044			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
1045			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
1046			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
1047			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
1048			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1049		>;
1050	};
1051
1052	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
1053		fsl,pins = <
1054			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
1055			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
1056			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
1057			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
1058			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
1059			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
1060			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1061		>;
1062	};
1063
1064	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
1065		fsl,pins = <
1066			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
1067			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
1068			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
1069			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
1070			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
1071			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
1072			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1073		>;
1074	};
1075
1076	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
1077		fsl,pins = <
1078			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
1079		>;
1080	};
1081
1082	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
1083		fsl,pins = <
1084			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
1085		>;
1086	};
1087
1088	pinctrl_usdhc3: dhcom-usdhc3-grp {
1089		fsl,pins = <
1090			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
1091			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
1092			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
1093			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
1094			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
1095			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
1096			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
1097			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
1098			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
1099			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
1100			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
1101			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1102		>;
1103	};
1104
1105	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1106		fsl,pins = <
1107			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
1108			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
1109			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
1110			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
1111			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
1112			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
1113			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
1114			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
1115			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
1116			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
1117			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
1118			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1119		>;
1120	};
1121
1122	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1123		fsl,pins = <
1124			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
1125			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
1126			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
1127			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
1128			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
1129			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
1130			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
1131			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
1132			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
1133			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
1134			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
1135			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1136		>;
1137	};
1138
1139	pinctrl_wdog: dhcom-wdog-grp {
1140		fsl,pins = <
1141			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
1142		>;
1143	};
1144};
1145