1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx8mn-pinfunc.h" 12 13/ { 14 compatible = "fsl,imx8mn"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 A53_0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0>; 50 clock-latency = <61036>; 51 clocks = <&clk IMX8MN_CLK_ARM>; 52 enable-method = "psci"; 53 next-level-cache = <&A53_L2>; 54 operating-points-v2 = <&a53_opp_table>; 55 nvmem-cells = <&cpu_speed_grade>; 56 nvmem-cell-names = "speed_grade"; 57 }; 58 59 A53_1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x1>; 63 clock-latency = <61036>; 64 clocks = <&clk IMX8MN_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 }; 69 70 A53_2: cpu@2 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x2>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MN_CLK_ARM>; 76 enable-method = "psci"; 77 next-level-cache = <&A53_L2>; 78 operating-points-v2 = <&a53_opp_table>; 79 }; 80 81 A53_3: cpu@3 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x3>; 85 clock-latency = <61036>; 86 clocks = <&clk IMX8MN_CLK_ARM>; 87 enable-method = "psci"; 88 next-level-cache = <&A53_L2>; 89 operating-points-v2 = <&a53_opp_table>; 90 }; 91 92 A53_L2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 a53_opp_table: opp-table { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 101 opp-1200000000 { 102 opp-hz = /bits/ 64 <1200000000>; 103 opp-microvolt = <850000>; 104 opp-supported-hw = <0xb00>, <0x7>; 105 clock-latency-ns = <150000>; 106 opp-suspend; 107 }; 108 109 opp-1400000000 { 110 opp-hz = /bits/ 64 <1400000000>; 111 opp-microvolt = <950000>; 112 opp-supported-hw = <0x300>, <0x7>; 113 clock-latency-ns = <150000>; 114 opp-suspend; 115 }; 116 117 opp-1500000000 { 118 opp-hz = /bits/ 64 <1500000000>; 119 opp-microvolt = <1000000>; 120 opp-supported-hw = <0x100>, <0x3>; 121 clock-latency-ns = <150000>; 122 opp-suspend; 123 }; 124 }; 125 126 memory@40000000 { 127 device_type = "memory"; 128 reg = <0x0 0x40000000 0 0x80000000>; 129 }; 130 131 osc_32k: clock-osc-32k { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <32768>; 135 clock-output-names = "osc_32k"; 136 }; 137 138 osc_24m: clock-osc-24m { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <24000000>; 142 clock-output-names = "osc_24m"; 143 }; 144 145 clk_ext1: clock-ext1 { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 clock-frequency = <133000000>; 149 clock-output-names = "clk_ext1"; 150 }; 151 152 clk_ext2: clock-ext2 { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <133000000>; 156 clock-output-names = "clk_ext2"; 157 }; 158 159 clk_ext3: clock-ext3 { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 clock-frequency = <133000000>; 163 clock-output-names = "clk_ext3"; 164 }; 165 166 clk_ext4: clock-ext4 { 167 compatible = "fixed-clock"; 168 #clock-cells = <0>; 169 clock-frequency= <133000000>; 170 clock-output-names = "clk_ext4"; 171 }; 172 173 psci { 174 compatible = "arm,psci-1.0"; 175 method = "smc"; 176 }; 177 178 timer { 179 compatible = "arm,armv8-timer"; 180 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 181 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 182 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 183 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 184 clock-frequency = <8000000>; 185 arm,no-tick-in-suspend; 186 }; 187 188 soc@0 { 189 compatible = "simple-bus"; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 ranges = <0x0 0x0 0x0 0x3e000000>; 193 194 aips1: bus@30000000 { 195 compatible = "fsl,aips-bus", "simple-bus"; 196 reg = <0x30000000 0x400000>; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges; 200 201 gpio1: gpio@30200000 { 202 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 203 reg = <0x30200000 0x10000>; 204 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 207 gpio-controller; 208 #gpio-cells = <2>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 gpio-ranges = <&iomuxc 0 10 30>; 212 }; 213 214 gpio2: gpio@30210000 { 215 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 216 reg = <0x30210000 0x10000>; 217 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 gpio-ranges = <&iomuxc 0 40 21>; 225 }; 226 227 gpio3: gpio@30220000 { 228 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 229 reg = <0x30220000 0x10000>; 230 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 233 gpio-controller; 234 #gpio-cells = <2>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 gpio-ranges = <&iomuxc 0 61 26>; 238 }; 239 240 gpio4: gpio@30230000 { 241 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 242 reg = <0x30230000 0x10000>; 243 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 gpio-ranges = <&iomuxc 21 108 11>; 251 }; 252 253 gpio5: gpio@30240000 { 254 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 255 reg = <0x30240000 0x10000>; 256 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 gpio-ranges = <&iomuxc 0 119 30>; 264 }; 265 266 wdog1: watchdog@30280000 { 267 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 268 reg = <0x30280000 0x10000>; 269 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 271 status = "disabled"; 272 }; 273 274 wdog2: watchdog@30290000 { 275 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 276 reg = <0x30290000 0x10000>; 277 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 279 status = "disabled"; 280 }; 281 282 wdog3: watchdog@302a0000 { 283 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 284 reg = <0x302a0000 0x10000>; 285 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 287 status = "disabled"; 288 }; 289 290 sdma3: dma-controller@302b0000 { 291 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 292 reg = <0x302b0000 0x10000>; 293 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 295 <&clk IMX8MN_CLK_SDMA3_ROOT>; 296 clock-names = "ipg", "ahb"; 297 #dma-cells = <3>; 298 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 299 }; 300 301 sdma2: dma-controller@302c0000 { 302 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 303 reg = <0x302c0000 0x10000>; 304 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 306 <&clk IMX8MN_CLK_SDMA2_ROOT>; 307 clock-names = "ipg", "ahb"; 308 #dma-cells = <3>; 309 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 310 }; 311 312 iomuxc: pinctrl@30330000 { 313 compatible = "fsl,imx8mn-iomuxc"; 314 reg = <0x30330000 0x10000>; 315 }; 316 317 gpr: iomuxc-gpr@30340000 { 318 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 319 reg = <0x30340000 0x10000>; 320 }; 321 322 ocotp: ocotp-ctrl@30350000 { 323 compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon"; 324 reg = <0x30350000 0x10000>; 325 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 cpu_speed_grade: speed-grade@10 { 330 reg = <0x10 4>; 331 }; 332 }; 333 334 anatop: anatop@30360000 { 335 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 336 "syscon", "simple-bus"; 337 reg = <0x30360000 0x10000>; 338 }; 339 340 snvs: snvs@30370000 { 341 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 342 reg = <0x30370000 0x10000>; 343 344 snvs_rtc: snvs-rtc-lp { 345 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 346 regmap = <&snvs>; 347 offset = <0x34>; 348 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 350 clock-names = "snvs-rtc"; 351 }; 352 353 snvs_pwrkey: snvs-powerkey { 354 compatible = "fsl,sec-v4.0-pwrkey"; 355 regmap = <&snvs>; 356 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 357 linux,keycode = <KEY_POWER>; 358 wakeup-source; 359 status = "disabled"; 360 }; 361 }; 362 363 clk: clock-controller@30380000 { 364 compatible = "fsl,imx8mn-ccm"; 365 reg = <0x30380000 0x10000>; 366 #clock-cells = <1>; 367 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 368 <&clk_ext3>, <&clk_ext4>; 369 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 370 "clk_ext3", "clk_ext4"; 371 }; 372 373 src: reset-controller@30390000 { 374 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 375 reg = <0x30390000 0x10000>; 376 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 377 #reset-cells = <1>; 378 }; 379 }; 380 381 aips2: bus@30400000 { 382 compatible = "fsl,aips-bus", "simple-bus"; 383 reg = <0x30400000 0x400000>; 384 #address-cells = <1>; 385 #size-cells = <1>; 386 ranges; 387 388 pwm1: pwm@30660000 { 389 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 390 reg = <0x30660000 0x10000>; 391 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 393 <&clk IMX8MN_CLK_PWM1_ROOT>; 394 clock-names = "ipg", "per"; 395 #pwm-cells = <2>; 396 status = "disabled"; 397 }; 398 399 pwm2: pwm@30670000 { 400 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 401 reg = <0x30670000 0x10000>; 402 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 404 <&clk IMX8MN_CLK_PWM2_ROOT>; 405 clock-names = "ipg", "per"; 406 #pwm-cells = <2>; 407 status = "disabled"; 408 }; 409 410 pwm3: pwm@30680000 { 411 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 412 reg = <0x30680000 0x10000>; 413 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 415 <&clk IMX8MN_CLK_PWM3_ROOT>; 416 clock-names = "ipg", "per"; 417 #pwm-cells = <2>; 418 status = "disabled"; 419 }; 420 421 pwm4: pwm@30690000 { 422 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 423 reg = <0x30690000 0x10000>; 424 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 426 <&clk IMX8MN_CLK_PWM4_ROOT>; 427 clock-names = "ipg", "per"; 428 #pwm-cells = <2>; 429 status = "disabled"; 430 }; 431 432 system_counter: timer@306a0000 { 433 compatible = "nxp,sysctr-timer"; 434 reg = <0x306a0000 0x20000>; 435 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&osc_24m>; 437 clock-names = "per"; 438 }; 439 }; 440 441 aips3: bus@30800000 { 442 compatible = "fsl,aips-bus", "simple-bus"; 443 reg = <0x30800000 0x400000>; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 ranges; 447 448 ecspi1: spi@30820000 { 449 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 reg = <0x30820000 0x10000>; 453 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 455 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 456 clock-names = "ipg", "per"; 457 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 ecspi2: spi@30830000 { 463 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 reg = <0x30830000 0x10000>; 467 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 469 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 470 clock-names = "ipg", "per"; 471 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 472 dma-names = "rx", "tx"; 473 status = "disabled"; 474 }; 475 476 ecspi3: spi@30840000 { 477 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 reg = <0x30840000 0x10000>; 481 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 483 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 484 clock-names = "ipg", "per"; 485 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 486 dma-names = "rx", "tx"; 487 status = "disabled"; 488 }; 489 490 uart1: serial@30860000 { 491 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 492 reg = <0x30860000 0x10000>; 493 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 495 <&clk IMX8MN_CLK_UART1_ROOT>; 496 clock-names = "ipg", "per"; 497 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 498 dma-names = "rx", "tx"; 499 status = "disabled"; 500 }; 501 502 uart3: serial@30880000 { 503 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 504 reg = <0x30880000 0x10000>; 505 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 507 <&clk IMX8MN_CLK_UART3_ROOT>; 508 clock-names = "ipg", "per"; 509 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 }; 513 514 uart2: serial@30890000 { 515 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 516 reg = <0x30890000 0x10000>; 517 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 519 <&clk IMX8MN_CLK_UART2_ROOT>; 520 clock-names = "ipg", "per"; 521 status = "disabled"; 522 }; 523 524 i2c1: i2c@30a20000 { 525 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 reg = <0x30a20000 0x10000>; 529 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 531 status = "disabled"; 532 }; 533 534 i2c2: i2c@30a30000 { 535 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 reg = <0x30a30000 0x10000>; 539 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 541 status = "disabled"; 542 }; 543 544 i2c3: i2c@30a40000 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 548 reg = <0x30a40000 0x10000>; 549 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 551 status = "disabled"; 552 }; 553 554 i2c4: i2c@30a50000 { 555 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 reg = <0x30a50000 0x10000>; 559 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 561 status = "disabled"; 562 }; 563 564 uart4: serial@30a60000 { 565 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 566 reg = <0x30a60000 0x10000>; 567 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 569 <&clk IMX8MN_CLK_UART4_ROOT>; 570 clock-names = "ipg", "per"; 571 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 572 dma-names = "rx", "tx"; 573 status = "disabled"; 574 }; 575 576 usdhc1: mmc@30b40000 { 577 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 578 reg = <0x30b40000 0x10000>; 579 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&clk IMX8MN_CLK_DUMMY>, 581 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 582 <&clk IMX8MN_CLK_USDHC1_ROOT>; 583 clock-names = "ipg", "ahb", "per"; 584 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; 585 assigned-clock-rates = <400000000>; 586 fsl,tuning-start-tap = <20>; 587 fsl,tuning-step= <2>; 588 bus-width = <4>; 589 status = "disabled"; 590 }; 591 592 usdhc2: mmc@30b50000 { 593 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 594 reg = <0x30b50000 0x10000>; 595 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clk IMX8MN_CLK_DUMMY>, 597 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 598 <&clk IMX8MN_CLK_USDHC2_ROOT>; 599 clock-names = "ipg", "ahb", "per"; 600 fsl,tuning-start-tap = <20>; 601 fsl,tuning-step= <2>; 602 bus-width = <4>; 603 status = "disabled"; 604 }; 605 606 usdhc3: mmc@30b60000 { 607 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 608 reg = <0x30b60000 0x10000>; 609 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MN_CLK_DUMMY>, 611 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 612 <&clk IMX8MN_CLK_USDHC3_ROOT>; 613 clock-names = "ipg", "ahb", "per"; 614 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 615 assigned-clock-rates = <400000000>; 616 fsl,tuning-start-tap = <20>; 617 fsl,tuning-step= <2>; 618 bus-width = <4>; 619 status = "disabled"; 620 }; 621 622 sdma1: dma-controller@30bd0000 { 623 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 624 reg = <0x30bd0000 0x10000>; 625 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 627 <&clk IMX8MN_CLK_SDMA1_ROOT>; 628 clock-names = "ipg", "ahb"; 629 #dma-cells = <3>; 630 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 631 }; 632 633 fec1: ethernet@30be0000 { 634 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; 635 reg = <0x30be0000 0x10000>; 636 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 640 <&clk IMX8MN_CLK_ENET1_ROOT>, 641 <&clk IMX8MN_CLK_ENET_TIMER>, 642 <&clk IMX8MN_CLK_ENET_REF>, 643 <&clk IMX8MN_CLK_ENET_PHY_REF>; 644 clock-names = "ipg", "ahb", "ptp", 645 "enet_clk_ref", "enet_out"; 646 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 647 <&clk IMX8MN_CLK_ENET_TIMER>, 648 <&clk IMX8MN_CLK_ENET_REF>, 649 <&clk IMX8MN_CLK_ENET_TIMER>; 650 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 651 <&clk IMX8MN_SYS_PLL2_100M>, 652 <&clk IMX8MN_SYS_PLL2_125M>; 653 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 654 fsl,num-tx-queues = <3>; 655 fsl,num-rx-queues = <3>; 656 status = "disabled"; 657 }; 658 659 }; 660 661 aips4: bus@32c00000 { 662 compatible = "fsl,aips-bus", "simple-bus"; 663 reg = <0x32c00000 0x400000>; 664 #address-cells = <1>; 665 #size-cells = <1>; 666 ranges; 667 668 usbotg1: usb@32e40000 { 669 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 670 reg = <0x32e40000 0x200>; 671 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 673 clock-names = "usb1_ctrl_root_clk"; 674 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 675 <&clk IMX8MN_CLK_USB_CORE_REF>; 676 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 677 <&clk IMX8MN_SYS_PLL1_100M>; 678 fsl,usbphy = <&usbphynop1>; 679 fsl,usbmisc = <&usbmisc1 0>; 680 status = "disabled"; 681 }; 682 683 usbmisc1: usbmisc@32e40200 { 684 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 685 #index-cells = <1>; 686 reg = <0x32e40200 0x200>; 687 }; 688 689 usbotg2: usb@32e50000 { 690 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 691 reg = <0x32e50000 0x200>; 692 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 694 clock-names = "usb1_ctrl_root_clk"; 695 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 696 <&clk IMX8MN_CLK_USB_CORE_REF>; 697 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 698 <&clk IMX8MN_SYS_PLL1_100M>; 699 fsl,usbphy = <&usbphynop2>; 700 fsl,usbmisc = <&usbmisc2 0>; 701 status = "disabled"; 702 }; 703 704 usbmisc2: usbmisc@32e50200 { 705 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 706 #index-cells = <1>; 707 reg = <0x32e50200 0x200>; 708 }; 709 710 }; 711 712 dma_apbh: dma-controller@33000000 { 713 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 714 reg = <0x33000000 0x2000>; 715 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 720 #dma-cells = <1>; 721 dma-channels = <4>; 722 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 723 }; 724 725 gpmi: nand-controller@33002000 { 726 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 727 #address-cells = <1>; 728 #size-cells = <1>; 729 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 730 reg-names = "gpmi-nand", "bch"; 731 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "bch"; 733 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 734 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 735 clock-names = "gpmi_io", "gpmi_bch_apb"; 736 dmas = <&dma_apbh 0>; 737 dma-names = "rx-tx"; 738 status = "disabled"; 739 }; 740 741 gic: interrupt-controller@38800000 { 742 compatible = "arm,gic-v3"; 743 reg = <0x38800000 0x10000>, 744 <0x38880000 0xc0000>; 745 #interrupt-cells = <3>; 746 interrupt-controller; 747 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 }; 750 751 usbphynop1: usbphynop1 { 752 compatible = "usb-nop-xceiv"; 753 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 754 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 755 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 756 clock-names = "main_clk"; 757 }; 758 759 usbphynop2: usbphynop2 { 760 compatible = "usb-nop-xceiv"; 761 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 762 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 763 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 764 clock-names = "main_clk"; 765 }; 766}; 767