1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mn-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; 64 clocks = <&clk IMX8MN_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; 79 clocks = <&clk IMX8MN_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; 92 clocks = <&clk IMX8MN_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; 105 clocks = <&clk IMX8MN_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xb00>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1400000000 { 131 opp-hz = /bits/ 64 <1400000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0x300>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1500000000 { 139 opp-hz = /bits/ 64 <1500000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x100>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 pmu { 190 compatible = "arm,cortex-a53-pmu"; 191 interrupts = <GIC_PPI 7 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 194 }; 195 196 psci { 197 compatible = "arm,psci-1.0"; 198 method = "smc"; 199 }; 200 201 thermal-zones { 202 cpu-thermal { 203 polling-delay-passive = <250>; 204 polling-delay = <2000>; 205 thermal-sensors = <&tmu>; 206 trips { 207 cpu_alert0: trip0 { 208 temperature = <85000>; 209 hysteresis = <2000>; 210 type = "passive"; 211 }; 212 213 cpu_crit0: trip1 { 214 temperature = <95000>; 215 hysteresis = <2000>; 216 type = "critical"; 217 }; 218 }; 219 220 cooling-maps { 221 map0 { 222 trip = <&cpu_alert0>; 223 cooling-device = 224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 228 }; 229 }; 230 }; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 239 clock-frequency = <8000000>; 240 arm,no-tick-in-suspend; 241 }; 242 243 soc@0 { 244 compatible = "simple-bus"; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 ranges = <0x0 0x0 0x0 0x3e000000>; 248 249 aips1: bus@30000000 { 250 compatible = "fsl,aips-bus", "simple-bus"; 251 reg = <0x30000000 0x400000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges; 255 256 spba: bus@30000000 { 257 compatible = "fsl,spba-bus", "simple-bus"; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 reg = <0x30000000 0x100000>; 261 ranges; 262 263 easrc: easrc@300c0000 { 264 compatible = "fsl,imx8mn-easrc"; 265 reg = <0x300c0000 0x10000>; 266 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 268 clock-names = "mem"; 269 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 270 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 271 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 272 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 273 dma-names = "ctx0_rx", "ctx0_tx", 274 "ctx1_rx", "ctx1_tx", 275 "ctx2_rx", "ctx2_tx", 276 "ctx3_rx", "ctx3_tx"; 277 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 278 fsl,asrc-rate = <8000>; 279 fsl,asrc-format = <2>; 280 status = "disabled"; 281 }; 282 }; 283 284 gpio1: gpio@30200000 { 285 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 286 reg = <0x30200000 0x10000>; 287 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 gpio-ranges = <&iomuxc 0 10 30>; 295 }; 296 297 gpio2: gpio@30210000 { 298 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 299 reg = <0x30210000 0x10000>; 300 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 gpio-ranges = <&iomuxc 0 40 21>; 308 }; 309 310 gpio3: gpio@30220000 { 311 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 312 reg = <0x30220000 0x10000>; 313 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 316 gpio-controller; 317 #gpio-cells = <2>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 gpio-ranges = <&iomuxc 0 61 26>; 321 }; 322 323 gpio4: gpio@30230000 { 324 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 325 reg = <0x30230000 0x10000>; 326 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 gpio-ranges = <&iomuxc 21 108 11>; 334 }; 335 336 gpio5: gpio@30240000 { 337 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 338 reg = <0x30240000 0x10000>; 339 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 342 gpio-controller; 343 #gpio-cells = <2>; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 gpio-ranges = <&iomuxc 0 119 30>; 347 }; 348 349 tmu: tmu@30260000 { 350 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 351 reg = <0x30260000 0x10000>; 352 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 353 #thermal-sensor-cells = <0>; 354 }; 355 356 wdog1: watchdog@30280000 { 357 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 358 reg = <0x30280000 0x10000>; 359 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 361 status = "disabled"; 362 }; 363 364 wdog2: watchdog@30290000 { 365 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 366 reg = <0x30290000 0x10000>; 367 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 369 status = "disabled"; 370 }; 371 372 wdog3: watchdog@302a0000 { 373 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 374 reg = <0x302a0000 0x10000>; 375 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 377 status = "disabled"; 378 }; 379 380 sdma3: dma-controller@302b0000 { 381 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 382 reg = <0x302b0000 0x10000>; 383 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 385 <&clk IMX8MN_CLK_SDMA3_ROOT>; 386 clock-names = "ipg", "ahb"; 387 #dma-cells = <3>; 388 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 389 }; 390 391 sdma2: dma-controller@302c0000 { 392 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 393 reg = <0x302c0000 0x10000>; 394 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 396 <&clk IMX8MN_CLK_SDMA2_ROOT>; 397 clock-names = "ipg", "ahb"; 398 #dma-cells = <3>; 399 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 400 }; 401 402 iomuxc: pinctrl@30330000 { 403 compatible = "fsl,imx8mn-iomuxc"; 404 reg = <0x30330000 0x10000>; 405 }; 406 407 gpr: iomuxc-gpr@30340000 { 408 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 409 reg = <0x30340000 0x10000>; 410 }; 411 412 ocotp: efuse@30350000 { 413 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 414 reg = <0x30350000 0x10000>; 415 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 416 #address-cells = <1>; 417 #size-cells = <1>; 418 419 cpu_speed_grade: speed-grade@10 { 420 reg = <0x10 4>; 421 }; 422 }; 423 424 anatop: anatop@30360000 { 425 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 426 "syscon"; 427 reg = <0x30360000 0x10000>; 428 }; 429 430 snvs: snvs@30370000 { 431 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 432 reg = <0x30370000 0x10000>; 433 434 snvs_rtc: snvs-rtc-lp { 435 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 436 regmap = <&snvs>; 437 offset = <0x34>; 438 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 441 clock-names = "snvs-rtc"; 442 }; 443 444 snvs_pwrkey: snvs-powerkey { 445 compatible = "fsl,sec-v4.0-pwrkey"; 446 regmap = <&snvs>; 447 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 449 clock-names = "snvs-pwrkey"; 450 linux,keycode = <KEY_POWER>; 451 wakeup-source; 452 status = "disabled"; 453 }; 454 }; 455 456 clk: clock-controller@30380000 { 457 compatible = "fsl,imx8mn-ccm"; 458 reg = <0x30380000 0x10000>; 459 #clock-cells = <1>; 460 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 461 <&clk_ext3>, <&clk_ext4>; 462 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 463 "clk_ext3", "clk_ext4"; 464 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 465 <&clk IMX8MN_CLK_A53_CORE>, 466 <&clk IMX8MN_CLK_NOC>, 467 <&clk IMX8MN_CLK_AUDIO_AHB>, 468 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 469 <&clk IMX8MN_SYS_PLL3>; 470 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 471 <&clk IMX8MN_ARM_PLL_OUT>, 472 <&clk IMX8MN_SYS_PLL3_OUT>, 473 <&clk IMX8MN_SYS_PLL1_800M>; 474 assigned-clock-rates = <0>, <0>, <0>, 475 <400000000>, 476 <400000000>, 477 <600000000>; 478 }; 479 480 src: reset-controller@30390000 { 481 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 482 reg = <0x30390000 0x10000>; 483 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 484 #reset-cells = <1>; 485 }; 486 }; 487 488 aips2: bus@30400000 { 489 compatible = "fsl,aips-bus", "simple-bus"; 490 reg = <0x30400000 0x400000>; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 ranges; 494 495 pwm1: pwm@30660000 { 496 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 497 reg = <0x30660000 0x10000>; 498 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 500 <&clk IMX8MN_CLK_PWM1_ROOT>; 501 clock-names = "ipg", "per"; 502 #pwm-cells = <2>; 503 status = "disabled"; 504 }; 505 506 pwm2: pwm@30670000 { 507 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 508 reg = <0x30670000 0x10000>; 509 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 511 <&clk IMX8MN_CLK_PWM2_ROOT>; 512 clock-names = "ipg", "per"; 513 #pwm-cells = <2>; 514 status = "disabled"; 515 }; 516 517 pwm3: pwm@30680000 { 518 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 519 reg = <0x30680000 0x10000>; 520 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 522 <&clk IMX8MN_CLK_PWM3_ROOT>; 523 clock-names = "ipg", "per"; 524 #pwm-cells = <2>; 525 status = "disabled"; 526 }; 527 528 pwm4: pwm@30690000 { 529 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 530 reg = <0x30690000 0x10000>; 531 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 533 <&clk IMX8MN_CLK_PWM4_ROOT>; 534 clock-names = "ipg", "per"; 535 #pwm-cells = <2>; 536 status = "disabled"; 537 }; 538 539 system_counter: timer@306a0000 { 540 compatible = "nxp,sysctr-timer"; 541 reg = <0x306a0000 0x20000>; 542 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&osc_24m>; 544 clock-names = "per"; 545 }; 546 }; 547 548 aips3: bus@30800000 { 549 compatible = "fsl,aips-bus", "simple-bus"; 550 reg = <0x30800000 0x400000>; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 ranges; 554 555 ecspi1: spi@30820000 { 556 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 reg = <0x30820000 0x10000>; 560 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 562 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 563 clock-names = "ipg", "per"; 564 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 565 dma-names = "rx", "tx"; 566 status = "disabled"; 567 }; 568 569 ecspi2: spi@30830000 { 570 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <0x30830000 0x10000>; 574 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 576 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 577 clock-names = "ipg", "per"; 578 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 579 dma-names = "rx", "tx"; 580 status = "disabled"; 581 }; 582 583 ecspi3: spi@30840000 { 584 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 reg = <0x30840000 0x10000>; 588 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 590 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 591 clock-names = "ipg", "per"; 592 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 593 dma-names = "rx", "tx"; 594 status = "disabled"; 595 }; 596 597 uart1: serial@30860000 { 598 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 599 reg = <0x30860000 0x10000>; 600 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 602 <&clk IMX8MN_CLK_UART1_ROOT>; 603 clock-names = "ipg", "per"; 604 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 605 dma-names = "rx", "tx"; 606 status = "disabled"; 607 }; 608 609 uart3: serial@30880000 { 610 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 611 reg = <0x30880000 0x10000>; 612 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 614 <&clk IMX8MN_CLK_UART3_ROOT>; 615 clock-names = "ipg", "per"; 616 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 617 dma-names = "rx", "tx"; 618 status = "disabled"; 619 }; 620 621 uart2: serial@30890000 { 622 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 623 reg = <0x30890000 0x10000>; 624 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 626 <&clk IMX8MN_CLK_UART2_ROOT>; 627 clock-names = "ipg", "per"; 628 status = "disabled"; 629 }; 630 631 crypto: crypto@30900000 { 632 compatible = "fsl,sec-v4.0"; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 reg = <0x30900000 0x40000>; 636 ranges = <0 0x30900000 0x40000>; 637 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&clk IMX8MN_CLK_AHB>, 639 <&clk IMX8MN_CLK_IPG_ROOT>; 640 clock-names = "aclk", "ipg"; 641 642 sec_jr0: jr@1000 { 643 compatible = "fsl,sec-v4.0-job-ring"; 644 reg = <0x1000 0x1000>; 645 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 646 }; 647 648 sec_jr1: jr@2000 { 649 compatible = "fsl,sec-v4.0-job-ring"; 650 reg = <0x2000 0x1000>; 651 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 652 }; 653 654 sec_jr2: jr@3000 { 655 compatible = "fsl,sec-v4.0-job-ring"; 656 reg = <0x3000 0x1000>; 657 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 658 }; 659 }; 660 661 i2c1: i2c@30a20000 { 662 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 reg = <0x30a20000 0x10000>; 666 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 668 status = "disabled"; 669 }; 670 671 i2c2: i2c@30a30000 { 672 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 reg = <0x30a30000 0x10000>; 676 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 678 status = "disabled"; 679 }; 680 681 i2c3: i2c@30a40000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 685 reg = <0x30a40000 0x10000>; 686 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 688 status = "disabled"; 689 }; 690 691 i2c4: i2c@30a50000 { 692 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0x30a50000 0x10000>; 696 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 698 status = "disabled"; 699 }; 700 701 uart4: serial@30a60000 { 702 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 703 reg = <0x30a60000 0x10000>; 704 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 706 <&clk IMX8MN_CLK_UART4_ROOT>; 707 clock-names = "ipg", "per"; 708 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 709 dma-names = "rx", "tx"; 710 status = "disabled"; 711 }; 712 713 mu: mailbox@30aa0000 { 714 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 715 reg = <0x30aa0000 0x10000>; 716 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 718 #mbox-cells = <2>; 719 }; 720 721 usdhc1: mmc@30b40000 { 722 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 723 reg = <0x30b40000 0x10000>; 724 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 726 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 727 <&clk IMX8MN_CLK_USDHC1_ROOT>; 728 clock-names = "ipg", "ahb", "per"; 729 fsl,tuning-start-tap = <20>; 730 fsl,tuning-step= <2>; 731 bus-width = <4>; 732 status = "disabled"; 733 }; 734 735 usdhc2: mmc@30b50000 { 736 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 737 reg = <0x30b50000 0x10000>; 738 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 740 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 741 <&clk IMX8MN_CLK_USDHC2_ROOT>; 742 clock-names = "ipg", "ahb", "per"; 743 fsl,tuning-start-tap = <20>; 744 fsl,tuning-step= <2>; 745 bus-width = <4>; 746 status = "disabled"; 747 }; 748 749 usdhc3: mmc@30b60000 { 750 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 751 reg = <0x30b60000 0x10000>; 752 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 754 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 755 <&clk IMX8MN_CLK_USDHC3_ROOT>; 756 clock-names = "ipg", "ahb", "per"; 757 fsl,tuning-start-tap = <20>; 758 fsl,tuning-step= <2>; 759 bus-width = <4>; 760 status = "disabled"; 761 }; 762 763 sdma1: dma-controller@30bd0000 { 764 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 765 reg = <0x30bd0000 0x10000>; 766 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 768 <&clk IMX8MN_CLK_AHB>; 769 clock-names = "ipg", "ahb"; 770 #dma-cells = <3>; 771 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 772 }; 773 774 fec1: ethernet@30be0000 { 775 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; 776 reg = <0x30be0000 0x10000>; 777 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 782 <&clk IMX8MN_CLK_ENET1_ROOT>, 783 <&clk IMX8MN_CLK_ENET_TIMER>, 784 <&clk IMX8MN_CLK_ENET_REF>, 785 <&clk IMX8MN_CLK_ENET_PHY_REF>; 786 clock-names = "ipg", "ahb", "ptp", 787 "enet_clk_ref", "enet_out"; 788 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 789 <&clk IMX8MN_CLK_ENET_TIMER>, 790 <&clk IMX8MN_CLK_ENET_REF>, 791 <&clk IMX8MN_CLK_ENET_TIMER>; 792 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 793 <&clk IMX8MN_SYS_PLL2_100M>, 794 <&clk IMX8MN_SYS_PLL2_125M>; 795 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 796 fsl,num-tx-queues = <3>; 797 fsl,num-rx-queues = <3>; 798 status = "disabled"; 799 }; 800 801 }; 802 803 aips4: bus@32c00000 { 804 compatible = "fsl,aips-bus", "simple-bus"; 805 reg = <0x32c00000 0x400000>; 806 #address-cells = <1>; 807 #size-cells = <1>; 808 ranges; 809 810 usbotg1: usb@32e40000 { 811 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 812 reg = <0x32e40000 0x200>; 813 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 815 clock-names = "usb1_ctrl_root_clk"; 816 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 817 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 818 fsl,usbphy = <&usbphynop1>; 819 fsl,usbmisc = <&usbmisc1 0>; 820 status = "disabled"; 821 }; 822 823 usbmisc1: usbmisc@32e40200 { 824 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 825 #index-cells = <1>; 826 reg = <0x32e40200 0x200>; 827 }; 828 829 usbotg2: usb@32e50000 { 830 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 831 reg = <0x32e50000 0x200>; 832 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 834 clock-names = "usb1_ctrl_root_clk"; 835 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 836 <&clk IMX8MN_CLK_USB_CORE_REF>; 837 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 838 <&clk IMX8MN_SYS_PLL1_100M>; 839 fsl,usbphy = <&usbphynop2>; 840 fsl,usbmisc = <&usbmisc2 0>; 841 status = "disabled"; 842 }; 843 844 usbmisc2: usbmisc@32e50200 { 845 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 846 #index-cells = <1>; 847 reg = <0x32e50200 0x200>; 848 }; 849 850 }; 851 852 dma_apbh: dma-controller@33000000 { 853 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 854 reg = <0x33000000 0x2000>; 855 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 860 #dma-cells = <1>; 861 dma-channels = <4>; 862 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 863 }; 864 865 gpmi: nand-controller@33002000 { 866 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 870 reg-names = "gpmi-nand", "bch"; 871 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 872 interrupt-names = "bch"; 873 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 874 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 875 clock-names = "gpmi_io", "gpmi_bch_apb"; 876 dmas = <&dma_apbh 0>; 877 dma-names = "rx-tx"; 878 status = "disabled"; 879 }; 880 881 gic: interrupt-controller@38800000 { 882 compatible = "arm,gic-v3"; 883 reg = <0x38800000 0x10000>, 884 <0x38880000 0xc0000>; 885 #interrupt-cells = <3>; 886 interrupt-controller; 887 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 888 }; 889 890 ddrc: memory-controller@3d400000 { 891 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 892 reg = <0x3d400000 0x400000>; 893 clock-names = "core", "pll", "alt", "apb"; 894 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 895 <&clk IMX8MN_DRAM_PLL>, 896 <&clk IMX8MN_CLK_DRAM_ALT>, 897 <&clk IMX8MN_CLK_DRAM_APB>; 898 }; 899 900 ddr-pmu@3d800000 { 901 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 902 reg = <0x3d800000 0x400000>; 903 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 904 }; 905 }; 906 907 usbphynop1: usbphynop1 { 908 compatible = "usb-nop-xceiv"; 909 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 910 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 911 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 912 clock-names = "main_clk"; 913 }; 914 915 usbphynop2: usbphynop2 { 916 compatible = "usb-nop-xceiv"; 917 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 918 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 919 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 920 clock-names = "main_clk"; 921 }; 922}; 923