1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mn-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; 64 clocks = <&clk IMX8MN_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; 79 clocks = <&clk IMX8MN_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; 92 clocks = <&clk IMX8MN_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; 105 clocks = <&clk IMX8MN_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xb00>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1400000000 { 131 opp-hz = /bits/ 64 <1400000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0x300>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1500000000 { 139 opp-hz = /bits/ 64 <1500000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x100>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 pmu { 190 compatible = "arm,cortex-a53-pmu"; 191 interrupts = <GIC_PPI 7 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 194 }; 195 196 psci { 197 compatible = "arm,psci-1.0"; 198 method = "smc"; 199 }; 200 201 thermal-zones { 202 cpu-thermal { 203 polling-delay-passive = <250>; 204 polling-delay = <2000>; 205 thermal-sensors = <&tmu>; 206 trips { 207 cpu_alert0: trip0 { 208 temperature = <85000>; 209 hysteresis = <2000>; 210 type = "passive"; 211 }; 212 213 cpu_crit0: trip1 { 214 temperature = <95000>; 215 hysteresis = <2000>; 216 type = "critical"; 217 }; 218 }; 219 220 cooling-maps { 221 map0 { 222 trip = <&cpu_alert0>; 223 cooling-device = 224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 228 }; 229 }; 230 }; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 239 clock-frequency = <8000000>; 240 arm,no-tick-in-suspend; 241 }; 242 243 soc@0 { 244 compatible = "fsl,imx8mn-soc", "simple-bus"; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 ranges = <0x0 0x0 0x0 0x3e000000>; 248 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 249 nvmem-cells = <&imx8mn_uid>; 250 nvmem-cell-names = "soc_unique_id"; 251 252 aips1: bus@30000000 { 253 compatible = "fsl,aips-bus", "simple-bus"; 254 reg = <0x30000000 0x400000>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges; 258 259 spba2: spba-bus@30000000 { 260 compatible = "fsl,spba-bus", "simple-bus"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 reg = <0x30000000 0x100000>; 264 ranges; 265 266 sai2: sai@30020000 { 267 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 268 reg = <0x30020000 0x10000>; 269 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 271 <&clk IMX8MN_CLK_DUMMY>, 272 <&clk IMX8MN_CLK_SAI2_ROOT>, 273 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 274 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 275 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 276 dma-names = "rx", "tx"; 277 status = "disabled"; 278 }; 279 280 sai3: sai@30030000 { 281 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 282 reg = <0x30030000 0x10000>; 283 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 285 <&clk IMX8MN_CLK_DUMMY>, 286 <&clk IMX8MN_CLK_SAI3_ROOT>, 287 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 288 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 289 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 290 dma-names = "rx", "tx"; 291 status = "disabled"; 292 }; 293 294 sai5: sai@30050000 { 295 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 296 reg = <0x30050000 0x10000>; 297 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 299 <&clk IMX8MN_CLK_DUMMY>, 300 <&clk IMX8MN_CLK_SAI5_ROOT>, 301 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 302 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 303 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 304 dma-names = "rx", "tx"; 305 fsl,shared-interrupt; 306 fsl,dataline = <0 0xf 0xf>; 307 status = "disabled"; 308 }; 309 310 sai6: sai@30060000 { 311 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 312 reg = <0x30060000 0x10000>; 313 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 315 <&clk IMX8MN_CLK_DUMMY>, 316 <&clk IMX8MN_CLK_SAI6_ROOT>, 317 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 318 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 319 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 }; 323 324 micfil: audio-controller@30080000 { 325 compatible = "fsl,imx8mm-micfil"; 326 reg = <0x30080000 0x10000>; 327 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 332 <&clk IMX8MN_CLK_PDM_ROOT>, 333 <&clk IMX8MN_AUDIO_PLL1_OUT>, 334 <&clk IMX8MN_AUDIO_PLL2_OUT>, 335 <&clk IMX8MN_CLK_EXT3>; 336 clock-names = "ipg_clk", "ipg_clk_app", 337 "pll8k", "pll11k", "clkext3"; 338 dmas = <&sdma2 24 25 0x80000000>; 339 dma-names = "rx"; 340 status = "disabled"; 341 }; 342 343 spdif1: spdif@30090000 { 344 compatible = "fsl,imx35-spdif"; 345 reg = <0x30090000 0x10000>; 346 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 348 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 349 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 350 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 351 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 352 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 353 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 354 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 355 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 356 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 357 clock-names = "core", "rxtx0", 358 "rxtx1", "rxtx2", 359 "rxtx3", "rxtx4", 360 "rxtx5", "rxtx6", 361 "rxtx7", "spba"; 362 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 363 dma-names = "rx", "tx"; 364 status = "disabled"; 365 }; 366 367 sai7: sai@300b0000 { 368 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 369 reg = <0x300b0000 0x10000>; 370 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 372 <&clk IMX8MN_CLK_DUMMY>, 373 <&clk IMX8MN_CLK_SAI7_ROOT>, 374 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 375 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 376 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 easrc: easrc@300c0000 { 382 compatible = "fsl,imx8mn-easrc"; 383 reg = <0x300c0000 0x10000>; 384 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 386 clock-names = "mem"; 387 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 388 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 389 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 390 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 391 dma-names = "ctx0_rx", "ctx0_tx", 392 "ctx1_rx", "ctx1_tx", 393 "ctx2_rx", "ctx2_tx", 394 "ctx3_rx", "ctx3_tx"; 395 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 396 fsl,asrc-rate = <8000>; 397 fsl,asrc-format = <2>; 398 status = "disabled"; 399 }; 400 }; 401 402 gpio1: gpio@30200000 { 403 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 404 reg = <0x30200000 0x10000>; 405 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 gpio-ranges = <&iomuxc 0 10 30>; 413 }; 414 415 gpio2: gpio@30210000 { 416 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 417 reg = <0x30210000 0x10000>; 418 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 gpio-ranges = <&iomuxc 0 40 21>; 426 }; 427 428 gpio3: gpio@30220000 { 429 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 430 reg = <0x30220000 0x10000>; 431 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 434 gpio-controller; 435 #gpio-cells = <2>; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 gpio-ranges = <&iomuxc 0 61 26>; 439 }; 440 441 gpio4: gpio@30230000 { 442 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 443 reg = <0x30230000 0x10000>; 444 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 gpio-ranges = <&iomuxc 21 108 11>; 452 }; 453 454 gpio5: gpio@30240000 { 455 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 456 reg = <0x30240000 0x10000>; 457 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 gpio-ranges = <&iomuxc 0 119 30>; 465 }; 466 467 tmu: tmu@30260000 { 468 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 469 reg = <0x30260000 0x10000>; 470 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 471 #thermal-sensor-cells = <0>; 472 }; 473 474 wdog1: watchdog@30280000 { 475 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 476 reg = <0x30280000 0x10000>; 477 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 479 status = "disabled"; 480 }; 481 482 wdog2: watchdog@30290000 { 483 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 484 reg = <0x30290000 0x10000>; 485 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 487 status = "disabled"; 488 }; 489 490 wdog3: watchdog@302a0000 { 491 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 492 reg = <0x302a0000 0x10000>; 493 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 495 status = "disabled"; 496 }; 497 498 sdma3: dma-controller@302b0000 { 499 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 500 reg = <0x302b0000 0x10000>; 501 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 503 <&clk IMX8MN_CLK_SDMA3_ROOT>; 504 clock-names = "ipg", "ahb"; 505 #dma-cells = <3>; 506 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 507 }; 508 509 sdma2: dma-controller@302c0000 { 510 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 511 reg = <0x302c0000 0x10000>; 512 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 514 <&clk IMX8MN_CLK_SDMA2_ROOT>; 515 clock-names = "ipg", "ahb"; 516 #dma-cells = <3>; 517 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 518 }; 519 520 iomuxc: pinctrl@30330000 { 521 compatible = "fsl,imx8mn-iomuxc"; 522 reg = <0x30330000 0x10000>; 523 }; 524 525 gpr: iomuxc-gpr@30340000 { 526 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 527 reg = <0x30340000 0x10000>; 528 }; 529 530 ocotp: efuse@30350000 { 531 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 532 reg = <0x30350000 0x10000>; 533 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 534 #address-cells = <1>; 535 #size-cells = <1>; 536 537 imx8mn_uid: unique-id@410 { 538 reg = <0x4 0x8>; 539 }; 540 541 cpu_speed_grade: speed-grade@10 { 542 reg = <0x10 4>; 543 }; 544 545 fec_mac_address: mac-address@90 { 546 reg = <0x90 6>; 547 }; 548 }; 549 550 anatop: anatop@30360000 { 551 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 552 "syscon"; 553 reg = <0x30360000 0x10000>; 554 }; 555 556 snvs: snvs@30370000 { 557 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 558 reg = <0x30370000 0x10000>; 559 560 snvs_rtc: snvs-rtc-lp { 561 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 562 regmap = <&snvs>; 563 offset = <0x34>; 564 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 567 clock-names = "snvs-rtc"; 568 }; 569 570 snvs_pwrkey: snvs-powerkey { 571 compatible = "fsl,sec-v4.0-pwrkey"; 572 regmap = <&snvs>; 573 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 575 clock-names = "snvs-pwrkey"; 576 linux,keycode = <KEY_POWER>; 577 wakeup-source; 578 status = "disabled"; 579 }; 580 }; 581 582 clk: clock-controller@30380000 { 583 compatible = "fsl,imx8mn-ccm"; 584 reg = <0x30380000 0x10000>; 585 #clock-cells = <1>; 586 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 587 <&clk_ext3>, <&clk_ext4>; 588 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 589 "clk_ext3", "clk_ext4"; 590 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 591 <&clk IMX8MN_CLK_A53_CORE>, 592 <&clk IMX8MN_CLK_NOC>, 593 <&clk IMX8MN_CLK_AUDIO_AHB>, 594 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 595 <&clk IMX8MN_SYS_PLL3>, 596 <&clk IMX8MN_AUDIO_PLL1>, 597 <&clk IMX8MN_AUDIO_PLL2>; 598 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 599 <&clk IMX8MN_ARM_PLL_OUT>, 600 <&clk IMX8MN_SYS_PLL3_OUT>, 601 <&clk IMX8MN_SYS_PLL1_800M>; 602 assigned-clock-rates = <0>, <0>, <0>, 603 <400000000>, 604 <400000000>, 605 <600000000>, 606 <393216000>, 607 <361267200>; 608 }; 609 610 src: reset-controller@30390000 { 611 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 612 reg = <0x30390000 0x10000>; 613 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 614 #reset-cells = <1>; 615 }; 616 }; 617 618 aips2: bus@30400000 { 619 compatible = "fsl,aips-bus", "simple-bus"; 620 reg = <0x30400000 0x400000>; 621 #address-cells = <1>; 622 #size-cells = <1>; 623 ranges; 624 625 pwm1: pwm@30660000 { 626 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 627 reg = <0x30660000 0x10000>; 628 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 630 <&clk IMX8MN_CLK_PWM1_ROOT>; 631 clock-names = "ipg", "per"; 632 #pwm-cells = <2>; 633 status = "disabled"; 634 }; 635 636 pwm2: pwm@30670000 { 637 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 638 reg = <0x30670000 0x10000>; 639 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 641 <&clk IMX8MN_CLK_PWM2_ROOT>; 642 clock-names = "ipg", "per"; 643 #pwm-cells = <2>; 644 status = "disabled"; 645 }; 646 647 pwm3: pwm@30680000 { 648 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 649 reg = <0x30680000 0x10000>; 650 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 652 <&clk IMX8MN_CLK_PWM3_ROOT>; 653 clock-names = "ipg", "per"; 654 #pwm-cells = <2>; 655 status = "disabled"; 656 }; 657 658 pwm4: pwm@30690000 { 659 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 660 reg = <0x30690000 0x10000>; 661 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 663 <&clk IMX8MN_CLK_PWM4_ROOT>; 664 clock-names = "ipg", "per"; 665 #pwm-cells = <2>; 666 status = "disabled"; 667 }; 668 669 system_counter: timer@306a0000 { 670 compatible = "nxp,sysctr-timer"; 671 reg = <0x306a0000 0x20000>; 672 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&osc_24m>; 674 clock-names = "per"; 675 }; 676 }; 677 678 aips3: bus@30800000 { 679 compatible = "fsl,aips-bus", "simple-bus"; 680 reg = <0x30800000 0x400000>; 681 #address-cells = <1>; 682 #size-cells = <1>; 683 ranges; 684 685 spba1: spba-bus@30800000 { 686 compatible = "fsl,spba-bus", "simple-bus"; 687 #address-cells = <1>; 688 #size-cells = <1>; 689 reg = <0x30800000 0x100000>; 690 ranges; 691 692 ecspi1: spi@30820000 { 693 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 reg = <0x30820000 0x10000>; 697 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 699 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 700 clock-names = "ipg", "per"; 701 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 702 dma-names = "rx", "tx"; 703 status = "disabled"; 704 }; 705 706 ecspi2: spi@30830000 { 707 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 reg = <0x30830000 0x10000>; 711 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 713 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 714 clock-names = "ipg", "per"; 715 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 716 dma-names = "rx", "tx"; 717 status = "disabled"; 718 }; 719 720 ecspi3: spi@30840000 { 721 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 reg = <0x30840000 0x10000>; 725 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 727 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 728 clock-names = "ipg", "per"; 729 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 730 dma-names = "rx", "tx"; 731 status = "disabled"; 732 }; 733 734 uart1: serial@30860000 { 735 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 736 reg = <0x30860000 0x10000>; 737 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 739 <&clk IMX8MN_CLK_UART1_ROOT>; 740 clock-names = "ipg", "per"; 741 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 742 dma-names = "rx", "tx"; 743 status = "disabled"; 744 }; 745 746 uart3: serial@30880000 { 747 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 748 reg = <0x30880000 0x10000>; 749 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 751 <&clk IMX8MN_CLK_UART3_ROOT>; 752 clock-names = "ipg", "per"; 753 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 754 dma-names = "rx", "tx"; 755 status = "disabled"; 756 }; 757 758 uart2: serial@30890000 { 759 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 760 reg = <0x30890000 0x10000>; 761 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 763 <&clk IMX8MN_CLK_UART2_ROOT>; 764 clock-names = "ipg", "per"; 765 status = "disabled"; 766 }; 767 }; 768 769 crypto: crypto@30900000 { 770 compatible = "fsl,sec-v4.0"; 771 #address-cells = <1>; 772 #size-cells = <1>; 773 reg = <0x30900000 0x40000>; 774 ranges = <0 0x30900000 0x40000>; 775 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&clk IMX8MN_CLK_AHB>, 777 <&clk IMX8MN_CLK_IPG_ROOT>; 778 clock-names = "aclk", "ipg"; 779 780 sec_jr0: jr@1000 { 781 compatible = "fsl,sec-v4.0-job-ring"; 782 reg = <0x1000 0x1000>; 783 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 784 }; 785 786 sec_jr1: jr@2000 { 787 compatible = "fsl,sec-v4.0-job-ring"; 788 reg = <0x2000 0x1000>; 789 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 790 }; 791 792 sec_jr2: jr@3000 { 793 compatible = "fsl,sec-v4.0-job-ring"; 794 reg = <0x3000 0x1000>; 795 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 796 }; 797 }; 798 799 i2c1: i2c@30a20000 { 800 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 reg = <0x30a20000 0x10000>; 804 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 806 status = "disabled"; 807 }; 808 809 i2c2: i2c@30a30000 { 810 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 reg = <0x30a30000 0x10000>; 814 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 816 status = "disabled"; 817 }; 818 819 i2c3: i2c@30a40000 { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 823 reg = <0x30a40000 0x10000>; 824 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 826 status = "disabled"; 827 }; 828 829 i2c4: i2c@30a50000 { 830 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 reg = <0x30a50000 0x10000>; 834 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 836 status = "disabled"; 837 }; 838 839 uart4: serial@30a60000 { 840 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 841 reg = <0x30a60000 0x10000>; 842 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 844 <&clk IMX8MN_CLK_UART4_ROOT>; 845 clock-names = "ipg", "per"; 846 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 847 dma-names = "rx", "tx"; 848 status = "disabled"; 849 }; 850 851 mu: mailbox@30aa0000 { 852 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 853 reg = <0x30aa0000 0x10000>; 854 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 856 #mbox-cells = <2>; 857 }; 858 859 usdhc1: mmc@30b40000 { 860 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 861 reg = <0x30b40000 0x10000>; 862 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 864 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 865 <&clk IMX8MN_CLK_USDHC1_ROOT>; 866 clock-names = "ipg", "ahb", "per"; 867 fsl,tuning-start-tap = <20>; 868 fsl,tuning-step= <2>; 869 bus-width = <4>; 870 status = "disabled"; 871 }; 872 873 usdhc2: mmc@30b50000 { 874 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 875 reg = <0x30b50000 0x10000>; 876 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 878 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 879 <&clk IMX8MN_CLK_USDHC2_ROOT>; 880 clock-names = "ipg", "ahb", "per"; 881 fsl,tuning-start-tap = <20>; 882 fsl,tuning-step= <2>; 883 bus-width = <4>; 884 status = "disabled"; 885 }; 886 887 usdhc3: mmc@30b60000 { 888 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 889 reg = <0x30b60000 0x10000>; 890 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 892 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 893 <&clk IMX8MN_CLK_USDHC3_ROOT>; 894 clock-names = "ipg", "ahb", "per"; 895 fsl,tuning-start-tap = <20>; 896 fsl,tuning-step= <2>; 897 bus-width = <4>; 898 status = "disabled"; 899 }; 900 901 flexspi: spi@30bb0000 { 902 #address-cells = <1>; 903 #size-cells = <0>; 904 compatible = "nxp,imx8mm-fspi"; 905 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 906 reg-names = "fspi_base", "fspi_mmap"; 907 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 909 <&clk IMX8MN_CLK_QSPI_ROOT>; 910 clock-names = "fspi_en", "fspi"; 911 status = "disabled"; 912 }; 913 914 sdma1: dma-controller@30bd0000 { 915 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 916 reg = <0x30bd0000 0x10000>; 917 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 919 <&clk IMX8MN_CLK_AHB>; 920 clock-names = "ipg", "ahb"; 921 #dma-cells = <3>; 922 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 923 }; 924 925 fec1: ethernet@30be0000 { 926 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; 927 reg = <0x30be0000 0x10000>; 928 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 933 <&clk IMX8MN_CLK_ENET1_ROOT>, 934 <&clk IMX8MN_CLK_ENET_TIMER>, 935 <&clk IMX8MN_CLK_ENET_REF>, 936 <&clk IMX8MN_CLK_ENET_PHY_REF>; 937 clock-names = "ipg", "ahb", "ptp", 938 "enet_clk_ref", "enet_out"; 939 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 940 <&clk IMX8MN_CLK_ENET_TIMER>, 941 <&clk IMX8MN_CLK_ENET_REF>, 942 <&clk IMX8MN_CLK_ENET_PHY_REF>; 943 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 944 <&clk IMX8MN_SYS_PLL2_100M>, 945 <&clk IMX8MN_SYS_PLL2_125M>, 946 <&clk IMX8MN_SYS_PLL2_50M>; 947 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 948 fsl,num-tx-queues = <3>; 949 fsl,num-rx-queues = <3>; 950 nvmem-cells = <&fec_mac_address>; 951 nvmem-cell-names = "mac-address"; 952 nvmem_macaddr_swap; 953 fsl,stop-mode = <&gpr 0x10 3>; 954 status = "disabled"; 955 }; 956 957 }; 958 959 aips4: bus@32c00000 { 960 compatible = "fsl,aips-bus", "simple-bus"; 961 reg = <0x32c00000 0x400000>; 962 #address-cells = <1>; 963 #size-cells = <1>; 964 ranges; 965 966 usbotg1: usb@32e40000 { 967 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 968 reg = <0x32e40000 0x200>; 969 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 971 clock-names = "usb1_ctrl_root_clk"; 972 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 973 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 974 fsl,usbphy = <&usbphynop1>; 975 fsl,usbmisc = <&usbmisc1 0>; 976 status = "disabled"; 977 }; 978 979 usbmisc1: usbmisc@32e40200 { 980 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 981 #index-cells = <1>; 982 reg = <0x32e40200 0x200>; 983 }; 984 }; 985 986 dma_apbh: dma-controller@33000000 { 987 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 988 reg = <0x33000000 0x2000>; 989 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 994 #dma-cells = <1>; 995 dma-channels = <4>; 996 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 997 }; 998 999 gpmi: nand-controller@33002000 { 1000 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1001 #address-cells = <1>; 1002 #size-cells = <1>; 1003 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1004 reg-names = "gpmi-nand", "bch"; 1005 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1006 interrupt-names = "bch"; 1007 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1008 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1009 clock-names = "gpmi_io", "gpmi_bch_apb"; 1010 dmas = <&dma_apbh 0>; 1011 dma-names = "rx-tx"; 1012 status = "disabled"; 1013 }; 1014 1015 gic: interrupt-controller@38800000 { 1016 compatible = "arm,gic-v3"; 1017 reg = <0x38800000 0x10000>, 1018 <0x38880000 0xc0000>; 1019 #interrupt-cells = <3>; 1020 interrupt-controller; 1021 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1022 }; 1023 1024 ddrc: memory-controller@3d400000 { 1025 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1026 reg = <0x3d400000 0x400000>; 1027 clock-names = "core", "pll", "alt", "apb"; 1028 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1029 <&clk IMX8MN_DRAM_PLL>, 1030 <&clk IMX8MN_CLK_DRAM_ALT>, 1031 <&clk IMX8MN_CLK_DRAM_APB>; 1032 }; 1033 1034 ddr-pmu@3d800000 { 1035 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1036 reg = <0x3d800000 0x400000>; 1037 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1038 }; 1039 }; 1040 1041 usbphynop1: usbphynop1 { 1042 compatible = "usb-nop-xceiv"; 1043 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1044 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1045 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1046 clock-names = "main_clk"; 1047 }; 1048}; 1049