1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mn-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; 64 clocks = <&clk IMX8MN_CLK_ARM>; 65 enable-method = "psci"; 66 i-cache-size = <0x8000>; 67 i-cache-line-size = <64>; 68 i-cache-sets = <256>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 next-level-cache = <&A53_L2>; 73 operating-points-v2 = <&a53_opp_table>; 74 nvmem-cells = <&cpu_speed_grade>; 75 nvmem-cell-names = "speed_grade"; 76 cpu-idle-states = <&cpu_pd_wait>; 77 #cooling-cells = <2>; 78 }; 79 80 A53_1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x1>; 84 clock-latency = <61036>; 85 clocks = <&clk IMX8MN_CLK_ARM>; 86 enable-method = "psci"; 87 i-cache-size = <0x8000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&A53_L2>; 94 operating-points-v2 = <&a53_opp_table>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 #cooling-cells = <2>; 97 }; 98 99 A53_2: cpu@2 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x2>; 103 clock-latency = <61036>; 104 clocks = <&clk IMX8MN_CLK_ARM>; 105 enable-method = "psci"; 106 i-cache-size = <0x8000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <256>; 109 d-cache-size = <0x8000>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&A53_L2>; 113 operating-points-v2 = <&a53_opp_table>; 114 cpu-idle-states = <&cpu_pd_wait>; 115 #cooling-cells = <2>; 116 }; 117 118 A53_3: cpu@3 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a53"; 121 reg = <0x3>; 122 clock-latency = <61036>; 123 clocks = <&clk IMX8MN_CLK_ARM>; 124 enable-method = "psci"; 125 i-cache-size = <0x8000>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <256>; 128 d-cache-size = <0x8000>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&A53_L2>; 132 operating-points-v2 = <&a53_opp_table>; 133 cpu-idle-states = <&cpu_pd_wait>; 134 #cooling-cells = <2>; 135 }; 136 137 A53_L2: l2-cache0 { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-size = <0x80000>; 141 cache-line-size = <64>; 142 cache-sets = <512>; 143 }; 144 }; 145 146 a53_opp_table: opp-table { 147 compatible = "operating-points-v2"; 148 opp-shared; 149 150 opp-1200000000 { 151 opp-hz = /bits/ 64 <1200000000>; 152 opp-microvolt = <850000>; 153 opp-supported-hw = <0xb00>, <0x7>; 154 clock-latency-ns = <150000>; 155 opp-suspend; 156 }; 157 158 opp-1400000000 { 159 opp-hz = /bits/ 64 <1400000000>; 160 opp-microvolt = <950000>; 161 opp-supported-hw = <0x300>, <0x7>; 162 clock-latency-ns = <150000>; 163 opp-suspend; 164 }; 165 166 opp-1500000000 { 167 opp-hz = /bits/ 64 <1500000000>; 168 opp-microvolt = <1000000>; 169 opp-supported-hw = <0x100>, <0x3>; 170 clock-latency-ns = <150000>; 171 opp-suspend; 172 }; 173 }; 174 175 osc_32k: clock-osc-32k { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <32768>; 179 clock-output-names = "osc_32k"; 180 }; 181 182 osc_24m: clock-osc-24m { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency = <24000000>; 186 clock-output-names = "osc_24m"; 187 }; 188 189 clk_ext1: clock-ext1 { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 clock-frequency = <133000000>; 193 clock-output-names = "clk_ext1"; 194 }; 195 196 clk_ext2: clock-ext2 { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-frequency = <133000000>; 200 clock-output-names = "clk_ext2"; 201 }; 202 203 clk_ext3: clock-ext3 { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <133000000>; 207 clock-output-names = "clk_ext3"; 208 }; 209 210 clk_ext4: clock-ext4 { 211 compatible = "fixed-clock"; 212 #clock-cells = <0>; 213 clock-frequency= <133000000>; 214 clock-output-names = "clk_ext4"; 215 }; 216 217 pmu { 218 compatible = "arm,cortex-a53-pmu"; 219 interrupts = <GIC_PPI 7 220 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 221 }; 222 223 psci { 224 compatible = "arm,psci-1.0"; 225 method = "smc"; 226 }; 227 228 thermal-zones { 229 cpu-thermal { 230 polling-delay-passive = <250>; 231 polling-delay = <2000>; 232 thermal-sensors = <&tmu>; 233 trips { 234 cpu_alert0: trip0 { 235 temperature = <85000>; 236 hysteresis = <2000>; 237 type = "passive"; 238 }; 239 240 cpu_crit0: trip1 { 241 temperature = <95000>; 242 hysteresis = <2000>; 243 type = "critical"; 244 }; 245 }; 246 247 cooling-maps { 248 map0 { 249 trip = <&cpu_alert0>; 250 cooling-device = 251 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 254 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 255 }; 256 }; 257 }; 258 }; 259 260 timer { 261 compatible = "arm,armv8-timer"; 262 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 263 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 264 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 265 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 266 clock-frequency = <8000000>; 267 arm,no-tick-in-suspend; 268 }; 269 270 soc@0 { 271 compatible = "fsl,imx8mn-soc", "simple-bus"; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0x0 0x0 0x0 0x3e000000>; 275 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 276 nvmem-cells = <&imx8mn_uid>; 277 nvmem-cell-names = "soc_unique_id"; 278 279 aips1: bus@30000000 { 280 compatible = "fsl,aips-bus", "simple-bus"; 281 reg = <0x30000000 0x400000>; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 ranges; 285 286 spba2: spba-bus@30000000 { 287 compatible = "fsl,spba-bus", "simple-bus"; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 reg = <0x30000000 0x100000>; 291 ranges; 292 293 sai2: sai@30020000 { 294 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 295 reg = <0x30020000 0x10000>; 296 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 298 <&clk IMX8MN_CLK_DUMMY>, 299 <&clk IMX8MN_CLK_SAI2_ROOT>, 300 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 302 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 303 dma-names = "rx", "tx"; 304 status = "disabled"; 305 }; 306 307 sai3: sai@30030000 { 308 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 309 reg = <0x30030000 0x10000>; 310 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 312 <&clk IMX8MN_CLK_DUMMY>, 313 <&clk IMX8MN_CLK_SAI3_ROOT>, 314 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 315 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 316 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 317 dma-names = "rx", "tx"; 318 status = "disabled"; 319 }; 320 321 sai5: sai@30050000 { 322 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 323 reg = <0x30050000 0x10000>; 324 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 326 <&clk IMX8MN_CLK_DUMMY>, 327 <&clk IMX8MN_CLK_SAI5_ROOT>, 328 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 329 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 330 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 331 dma-names = "rx", "tx"; 332 fsl,shared-interrupt; 333 fsl,dataline = <0 0xf 0xf>; 334 status = "disabled"; 335 }; 336 337 sai6: sai@30060000 { 338 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 339 reg = <0x30060000 0x10000>; 340 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 342 <&clk IMX8MN_CLK_DUMMY>, 343 <&clk IMX8MN_CLK_SAI6_ROOT>, 344 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 345 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 346 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 347 dma-names = "rx", "tx"; 348 status = "disabled"; 349 }; 350 351 micfil: audio-controller@30080000 { 352 compatible = "fsl,imx8mm-micfil"; 353 reg = <0x30080000 0x10000>; 354 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 359 <&clk IMX8MN_CLK_PDM_ROOT>, 360 <&clk IMX8MN_AUDIO_PLL1_OUT>, 361 <&clk IMX8MN_AUDIO_PLL2_OUT>, 362 <&clk IMX8MN_CLK_EXT3>; 363 clock-names = "ipg_clk", "ipg_clk_app", 364 "pll8k", "pll11k", "clkext3"; 365 dmas = <&sdma2 24 25 0x80000000>; 366 dma-names = "rx"; 367 status = "disabled"; 368 }; 369 370 spdif1: spdif@30090000 { 371 compatible = "fsl,imx35-spdif"; 372 reg = <0x30090000 0x10000>; 373 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 375 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 376 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 377 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 378 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 379 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 380 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 382 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 383 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 384 clock-names = "core", "rxtx0", 385 "rxtx1", "rxtx2", 386 "rxtx3", "rxtx4", 387 "rxtx5", "rxtx6", 388 "rxtx7", "spba"; 389 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 390 dma-names = "rx", "tx"; 391 status = "disabled"; 392 }; 393 394 sai7: sai@300b0000 { 395 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 396 reg = <0x300b0000 0x10000>; 397 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 399 <&clk IMX8MN_CLK_DUMMY>, 400 <&clk IMX8MN_CLK_SAI7_ROOT>, 401 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 402 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 403 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 404 dma-names = "rx", "tx"; 405 status = "disabled"; 406 }; 407 408 easrc: easrc@300c0000 { 409 compatible = "fsl,imx8mn-easrc"; 410 reg = <0x300c0000 0x10000>; 411 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 413 clock-names = "mem"; 414 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 415 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 416 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 417 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 418 dma-names = "ctx0_rx", "ctx0_tx", 419 "ctx1_rx", "ctx1_tx", 420 "ctx2_rx", "ctx2_tx", 421 "ctx3_rx", "ctx3_tx"; 422 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 423 fsl,asrc-rate = <8000>; 424 fsl,asrc-format = <2>; 425 status = "disabled"; 426 }; 427 }; 428 429 gpio1: gpio@30200000 { 430 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 431 reg = <0x30200000 0x10000>; 432 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 gpio-ranges = <&iomuxc 0 10 30>; 440 }; 441 442 gpio2: gpio@30210000 { 443 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 444 reg = <0x30210000 0x10000>; 445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 448 gpio-controller; 449 #gpio-cells = <2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 gpio-ranges = <&iomuxc 0 40 21>; 453 }; 454 455 gpio3: gpio@30220000 { 456 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 457 reg = <0x30220000 0x10000>; 458 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 gpio-ranges = <&iomuxc 0 61 26>; 466 }; 467 468 gpio4: gpio@30230000 { 469 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 470 reg = <0x30230000 0x10000>; 471 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 gpio-ranges = <&iomuxc 21 108 11>; 479 }; 480 481 gpio5: gpio@30240000 { 482 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 483 reg = <0x30240000 0x10000>; 484 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 487 gpio-controller; 488 #gpio-cells = <2>; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 gpio-ranges = <&iomuxc 0 119 30>; 492 }; 493 494 tmu: tmu@30260000 { 495 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 496 reg = <0x30260000 0x10000>; 497 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 498 #thermal-sensor-cells = <0>; 499 }; 500 501 wdog1: watchdog@30280000 { 502 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 503 reg = <0x30280000 0x10000>; 504 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 506 status = "disabled"; 507 }; 508 509 wdog2: watchdog@30290000 { 510 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 511 reg = <0x30290000 0x10000>; 512 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 514 status = "disabled"; 515 }; 516 517 wdog3: watchdog@302a0000 { 518 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 519 reg = <0x302a0000 0x10000>; 520 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 522 status = "disabled"; 523 }; 524 525 sdma3: dma-controller@302b0000 { 526 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 527 reg = <0x302b0000 0x10000>; 528 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 530 <&clk IMX8MN_CLK_SDMA3_ROOT>; 531 clock-names = "ipg", "ahb"; 532 #dma-cells = <3>; 533 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 534 }; 535 536 sdma2: dma-controller@302c0000 { 537 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 538 reg = <0x302c0000 0x10000>; 539 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 541 <&clk IMX8MN_CLK_SDMA2_ROOT>; 542 clock-names = "ipg", "ahb"; 543 #dma-cells = <3>; 544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 545 }; 546 547 iomuxc: pinctrl@30330000 { 548 compatible = "fsl,imx8mn-iomuxc"; 549 reg = <0x30330000 0x10000>; 550 }; 551 552 gpr: iomuxc-gpr@30340000 { 553 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 554 reg = <0x30340000 0x10000>; 555 }; 556 557 ocotp: efuse@30350000 { 558 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 559 reg = <0x30350000 0x10000>; 560 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 564 imx8mn_uid: unique-id@410 { 565 reg = <0x4 0x8>; 566 }; 567 568 cpu_speed_grade: speed-grade@10 { 569 reg = <0x10 4>; 570 }; 571 572 fec_mac_address: mac-address@90 { 573 reg = <0x90 6>; 574 }; 575 }; 576 577 anatop: anatop@30360000 { 578 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 579 "syscon"; 580 reg = <0x30360000 0x10000>; 581 }; 582 583 snvs: snvs@30370000 { 584 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 585 reg = <0x30370000 0x10000>; 586 587 snvs_rtc: snvs-rtc-lp { 588 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 589 regmap = <&snvs>; 590 offset = <0x34>; 591 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 594 clock-names = "snvs-rtc"; 595 }; 596 597 snvs_pwrkey: snvs-powerkey { 598 compatible = "fsl,sec-v4.0-pwrkey"; 599 regmap = <&snvs>; 600 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 602 clock-names = "snvs-pwrkey"; 603 linux,keycode = <KEY_POWER>; 604 wakeup-source; 605 status = "disabled"; 606 }; 607 }; 608 609 clk: clock-controller@30380000 { 610 compatible = "fsl,imx8mn-ccm"; 611 reg = <0x30380000 0x10000>; 612 #clock-cells = <1>; 613 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 614 <&clk_ext3>, <&clk_ext4>; 615 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 616 "clk_ext3", "clk_ext4"; 617 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 618 <&clk IMX8MN_CLK_A53_CORE>, 619 <&clk IMX8MN_CLK_NOC>, 620 <&clk IMX8MN_CLK_AUDIO_AHB>, 621 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 622 <&clk IMX8MN_SYS_PLL3>, 623 <&clk IMX8MN_AUDIO_PLL1>, 624 <&clk IMX8MN_AUDIO_PLL2>; 625 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 626 <&clk IMX8MN_ARM_PLL_OUT>, 627 <&clk IMX8MN_SYS_PLL3_OUT>, 628 <&clk IMX8MN_SYS_PLL1_800M>; 629 assigned-clock-rates = <0>, <0>, <0>, 630 <400000000>, 631 <400000000>, 632 <600000000>, 633 <393216000>, 634 <361267200>; 635 }; 636 637 src: reset-controller@30390000 { 638 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 639 reg = <0x30390000 0x10000>; 640 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 641 #reset-cells = <1>; 642 }; 643 }; 644 645 aips2: bus@30400000 { 646 compatible = "fsl,aips-bus", "simple-bus"; 647 reg = <0x30400000 0x400000>; 648 #address-cells = <1>; 649 #size-cells = <1>; 650 ranges; 651 652 pwm1: pwm@30660000 { 653 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 654 reg = <0x30660000 0x10000>; 655 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 657 <&clk IMX8MN_CLK_PWM1_ROOT>; 658 clock-names = "ipg", "per"; 659 #pwm-cells = <2>; 660 status = "disabled"; 661 }; 662 663 pwm2: pwm@30670000 { 664 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 665 reg = <0x30670000 0x10000>; 666 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 668 <&clk IMX8MN_CLK_PWM2_ROOT>; 669 clock-names = "ipg", "per"; 670 #pwm-cells = <2>; 671 status = "disabled"; 672 }; 673 674 pwm3: pwm@30680000 { 675 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 676 reg = <0x30680000 0x10000>; 677 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 679 <&clk IMX8MN_CLK_PWM3_ROOT>; 680 clock-names = "ipg", "per"; 681 #pwm-cells = <2>; 682 status = "disabled"; 683 }; 684 685 pwm4: pwm@30690000 { 686 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 687 reg = <0x30690000 0x10000>; 688 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 690 <&clk IMX8MN_CLK_PWM4_ROOT>; 691 clock-names = "ipg", "per"; 692 #pwm-cells = <2>; 693 status = "disabled"; 694 }; 695 696 system_counter: timer@306a0000 { 697 compatible = "nxp,sysctr-timer"; 698 reg = <0x306a0000 0x20000>; 699 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&osc_24m>; 701 clock-names = "per"; 702 }; 703 }; 704 705 aips3: bus@30800000 { 706 compatible = "fsl,aips-bus", "simple-bus"; 707 reg = <0x30800000 0x400000>; 708 #address-cells = <1>; 709 #size-cells = <1>; 710 ranges; 711 712 spba1: spba-bus@30800000 { 713 compatible = "fsl,spba-bus", "simple-bus"; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 reg = <0x30800000 0x100000>; 717 ranges; 718 719 ecspi1: spi@30820000 { 720 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 reg = <0x30820000 0x10000>; 724 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 726 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 727 clock-names = "ipg", "per"; 728 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 729 dma-names = "rx", "tx"; 730 status = "disabled"; 731 }; 732 733 ecspi2: spi@30830000 { 734 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 reg = <0x30830000 0x10000>; 738 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 740 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 741 clock-names = "ipg", "per"; 742 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 743 dma-names = "rx", "tx"; 744 status = "disabled"; 745 }; 746 747 ecspi3: spi@30840000 { 748 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 reg = <0x30840000 0x10000>; 752 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 754 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 755 clock-names = "ipg", "per"; 756 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 757 dma-names = "rx", "tx"; 758 status = "disabled"; 759 }; 760 761 uart1: serial@30860000 { 762 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 763 reg = <0x30860000 0x10000>; 764 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 766 <&clk IMX8MN_CLK_UART1_ROOT>; 767 clock-names = "ipg", "per"; 768 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 769 dma-names = "rx", "tx"; 770 status = "disabled"; 771 }; 772 773 uart3: serial@30880000 { 774 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 775 reg = <0x30880000 0x10000>; 776 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 778 <&clk IMX8MN_CLK_UART3_ROOT>; 779 clock-names = "ipg", "per"; 780 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 781 dma-names = "rx", "tx"; 782 status = "disabled"; 783 }; 784 785 uart2: serial@30890000 { 786 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 787 reg = <0x30890000 0x10000>; 788 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 790 <&clk IMX8MN_CLK_UART2_ROOT>; 791 clock-names = "ipg", "per"; 792 status = "disabled"; 793 }; 794 }; 795 796 crypto: crypto@30900000 { 797 compatible = "fsl,sec-v4.0"; 798 #address-cells = <1>; 799 #size-cells = <1>; 800 reg = <0x30900000 0x40000>; 801 ranges = <0 0x30900000 0x40000>; 802 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clk IMX8MN_CLK_AHB>, 804 <&clk IMX8MN_CLK_IPG_ROOT>; 805 clock-names = "aclk", "ipg"; 806 807 sec_jr0: jr@1000 { 808 compatible = "fsl,sec-v4.0-job-ring"; 809 reg = <0x1000 0x1000>; 810 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 811 }; 812 813 sec_jr1: jr@2000 { 814 compatible = "fsl,sec-v4.0-job-ring"; 815 reg = <0x2000 0x1000>; 816 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 817 }; 818 819 sec_jr2: jr@3000 { 820 compatible = "fsl,sec-v4.0-job-ring"; 821 reg = <0x3000 0x1000>; 822 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 823 }; 824 }; 825 826 i2c1: i2c@30a20000 { 827 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 reg = <0x30a20000 0x10000>; 831 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 833 status = "disabled"; 834 }; 835 836 i2c2: i2c@30a30000 { 837 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 reg = <0x30a30000 0x10000>; 841 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 843 status = "disabled"; 844 }; 845 846 i2c3: i2c@30a40000 { 847 #address-cells = <1>; 848 #size-cells = <0>; 849 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 850 reg = <0x30a40000 0x10000>; 851 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 853 status = "disabled"; 854 }; 855 856 i2c4: i2c@30a50000 { 857 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 reg = <0x30a50000 0x10000>; 861 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 863 status = "disabled"; 864 }; 865 866 uart4: serial@30a60000 { 867 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 868 reg = <0x30a60000 0x10000>; 869 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 871 <&clk IMX8MN_CLK_UART4_ROOT>; 872 clock-names = "ipg", "per"; 873 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 874 dma-names = "rx", "tx"; 875 status = "disabled"; 876 }; 877 878 mu: mailbox@30aa0000 { 879 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 880 reg = <0x30aa0000 0x10000>; 881 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 883 #mbox-cells = <2>; 884 }; 885 886 usdhc1: mmc@30b40000 { 887 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 888 reg = <0x30b40000 0x10000>; 889 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 891 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 892 <&clk IMX8MN_CLK_USDHC1_ROOT>; 893 clock-names = "ipg", "ahb", "per"; 894 fsl,tuning-start-tap = <20>; 895 fsl,tuning-step= <2>; 896 bus-width = <4>; 897 status = "disabled"; 898 }; 899 900 usdhc2: mmc@30b50000 { 901 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 902 reg = <0x30b50000 0x10000>; 903 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 905 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 906 <&clk IMX8MN_CLK_USDHC2_ROOT>; 907 clock-names = "ipg", "ahb", "per"; 908 fsl,tuning-start-tap = <20>; 909 fsl,tuning-step= <2>; 910 bus-width = <4>; 911 status = "disabled"; 912 }; 913 914 usdhc3: mmc@30b60000 { 915 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 916 reg = <0x30b60000 0x10000>; 917 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 919 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 920 <&clk IMX8MN_CLK_USDHC3_ROOT>; 921 clock-names = "ipg", "ahb", "per"; 922 fsl,tuning-start-tap = <20>; 923 fsl,tuning-step= <2>; 924 bus-width = <4>; 925 status = "disabled"; 926 }; 927 928 flexspi: spi@30bb0000 { 929 #address-cells = <1>; 930 #size-cells = <0>; 931 compatible = "nxp,imx8mm-fspi"; 932 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 933 reg-names = "fspi_base", "fspi_mmap"; 934 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 936 <&clk IMX8MN_CLK_QSPI_ROOT>; 937 clock-names = "fspi_en", "fspi"; 938 status = "disabled"; 939 }; 940 941 sdma1: dma-controller@30bd0000 { 942 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 943 reg = <0x30bd0000 0x10000>; 944 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 946 <&clk IMX8MN_CLK_AHB>; 947 clock-names = "ipg", "ahb"; 948 #dma-cells = <3>; 949 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 950 }; 951 952 fec1: ethernet@30be0000 { 953 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 954 reg = <0x30be0000 0x10000>; 955 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 960 <&clk IMX8MN_CLK_ENET1_ROOT>, 961 <&clk IMX8MN_CLK_ENET_TIMER>, 962 <&clk IMX8MN_CLK_ENET_REF>, 963 <&clk IMX8MN_CLK_ENET_PHY_REF>; 964 clock-names = "ipg", "ahb", "ptp", 965 "enet_clk_ref", "enet_out"; 966 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 967 <&clk IMX8MN_CLK_ENET_TIMER>, 968 <&clk IMX8MN_CLK_ENET_REF>, 969 <&clk IMX8MN_CLK_ENET_PHY_REF>; 970 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 971 <&clk IMX8MN_SYS_PLL2_100M>, 972 <&clk IMX8MN_SYS_PLL2_125M>, 973 <&clk IMX8MN_SYS_PLL2_50M>; 974 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 975 fsl,num-tx-queues = <3>; 976 fsl,num-rx-queues = <3>; 977 nvmem-cells = <&fec_mac_address>; 978 nvmem-cell-names = "mac-address"; 979 fsl,stop-mode = <&gpr 0x10 3>; 980 status = "disabled"; 981 }; 982 983 }; 984 985 aips4: bus@32c00000 { 986 compatible = "fsl,aips-bus", "simple-bus"; 987 reg = <0x32c00000 0x400000>; 988 #address-cells = <1>; 989 #size-cells = <1>; 990 ranges; 991 992 usbotg1: usb@32e40000 { 993 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 994 reg = <0x32e40000 0x200>; 995 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 997 clock-names = "usb1_ctrl_root_clk"; 998 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 999 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1000 phys = <&usbphynop1>; 1001 fsl,usbmisc = <&usbmisc1 0>; 1002 status = "disabled"; 1003 }; 1004 1005 usbmisc1: usbmisc@32e40200 { 1006 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 1007 #index-cells = <1>; 1008 reg = <0x32e40200 0x200>; 1009 }; 1010 }; 1011 1012 dma_apbh: dma-controller@33000000 { 1013 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1014 reg = <0x33000000 0x2000>; 1015 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1020 #dma-cells = <1>; 1021 dma-channels = <4>; 1022 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1023 }; 1024 1025 gpmi: nand-controller@33002000 { 1026 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1030 reg-names = "gpmi-nand", "bch"; 1031 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupt-names = "bch"; 1033 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1034 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1035 clock-names = "gpmi_io", "gpmi_bch_apb"; 1036 dmas = <&dma_apbh 0>; 1037 dma-names = "rx-tx"; 1038 status = "disabled"; 1039 }; 1040 1041 gic: interrupt-controller@38800000 { 1042 compatible = "arm,gic-v3"; 1043 reg = <0x38800000 0x10000>, 1044 <0x38880000 0xc0000>; 1045 #interrupt-cells = <3>; 1046 interrupt-controller; 1047 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1048 }; 1049 1050 ddrc: memory-controller@3d400000 { 1051 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1052 reg = <0x3d400000 0x400000>; 1053 clock-names = "core", "pll", "alt", "apb"; 1054 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1055 <&clk IMX8MN_DRAM_PLL>, 1056 <&clk IMX8MN_CLK_DRAM_ALT>, 1057 <&clk IMX8MN_CLK_DRAM_APB>; 1058 }; 1059 1060 ddr-pmu@3d800000 { 1061 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1062 reg = <0x3d800000 0x400000>; 1063 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1064 }; 1065 }; 1066 1067 usbphynop1: usbphynop1 { 1068 #phy-cells = <0>; 1069 compatible = "usb-nop-xceiv"; 1070 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1071 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1072 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1073 clock-names = "main_clk"; 1074 }; 1075}; 1076