1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx8mn-pinfunc.h" 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 ethernet0 = &fec1; 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 gpio4 = &gpio5; 25 i2c0 = &i2c1; 26 i2c1 = &i2c2; 27 i2c2 = &i2c3; 28 i2c3 = &i2c4; 29 mmc0 = &usdhc1; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc3; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 spi0 = &ecspi1; 37 spi1 = &ecspi2; 38 spi2 = &ecspi3; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 idle-states { 46 entry-method = "psci"; 47 48 cpu_pd_wait: cpu-pd-wait { 49 compatible = "arm,idle-state"; 50 arm,psci-suspend-param = <0x0010033>; 51 local-timer-stop; 52 entry-latency-us = <1000>; 53 exit-latency-us = <700>; 54 min-residency-us = <2700>; 55 }; 56 }; 57 58 A53_0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0>; 62 clock-latency = <61036>; 63 clocks = <&clk IMX8MN_CLK_ARM>; 64 enable-method = "psci"; 65 next-level-cache = <&A53_L2>; 66 operating-points-v2 = <&a53_opp_table>; 67 nvmem-cells = <&cpu_speed_grade>; 68 nvmem-cell-names = "speed_grade"; 69 cpu-idle-states = <&cpu_pd_wait>; 70 }; 71 72 A53_1: cpu@1 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x1>; 76 clock-latency = <61036>; 77 clocks = <&clk IMX8MN_CLK_ARM>; 78 enable-method = "psci"; 79 next-level-cache = <&A53_L2>; 80 operating-points-v2 = <&a53_opp_table>; 81 cpu-idle-states = <&cpu_pd_wait>; 82 }; 83 84 A53_2: cpu@2 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x2>; 88 clock-latency = <61036>; 89 clocks = <&clk IMX8MN_CLK_ARM>; 90 enable-method = "psci"; 91 next-level-cache = <&A53_L2>; 92 operating-points-v2 = <&a53_opp_table>; 93 cpu-idle-states = <&cpu_pd_wait>; 94 }; 95 96 A53_3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x3>; 100 clock-latency = <61036>; 101 clocks = <&clk IMX8MN_CLK_ARM>; 102 enable-method = "psci"; 103 next-level-cache = <&A53_L2>; 104 operating-points-v2 = <&a53_opp_table>; 105 cpu-idle-states = <&cpu_pd_wait>; 106 }; 107 108 A53_L2: l2-cache0 { 109 compatible = "cache"; 110 }; 111 }; 112 113 a53_opp_table: opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-1200000000 { 118 opp-hz = /bits/ 64 <1200000000>; 119 opp-microvolt = <850000>; 120 opp-supported-hw = <0xb00>, <0x7>; 121 clock-latency-ns = <150000>; 122 opp-suspend; 123 }; 124 125 opp-1400000000 { 126 opp-hz = /bits/ 64 <1400000000>; 127 opp-microvolt = <950000>; 128 opp-supported-hw = <0x300>, <0x7>; 129 clock-latency-ns = <150000>; 130 opp-suspend; 131 }; 132 133 opp-1500000000 { 134 opp-hz = /bits/ 64 <1500000000>; 135 opp-microvolt = <1000000>; 136 opp-supported-hw = <0x100>, <0x3>; 137 clock-latency-ns = <150000>; 138 opp-suspend; 139 }; 140 }; 141 142 memory@40000000 { 143 device_type = "memory"; 144 reg = <0x0 0x40000000 0 0x80000000>; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0"; 191 method = "smc"; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 197 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 198 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 200 clock-frequency = <8000000>; 201 arm,no-tick-in-suspend; 202 }; 203 204 soc@0 { 205 compatible = "simple-bus"; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges = <0x0 0x0 0x0 0x3e000000>; 209 210 aips1: bus@30000000 { 211 compatible = "fsl,aips-bus", "simple-bus"; 212 reg = <0x30000000 0x400000>; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 ranges; 216 217 gpio1: gpio@30200000 { 218 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 219 reg = <0x30200000 0x10000>; 220 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 223 gpio-controller; 224 #gpio-cells = <2>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 gpio-ranges = <&iomuxc 0 10 30>; 228 }; 229 230 gpio2: gpio@30210000 { 231 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 232 reg = <0x30210000 0x10000>; 233 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 gpio-ranges = <&iomuxc 0 40 21>; 241 }; 242 243 gpio3: gpio@30220000 { 244 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 245 reg = <0x30220000 0x10000>; 246 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 gpio-ranges = <&iomuxc 0 61 26>; 254 }; 255 256 gpio4: gpio@30230000 { 257 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 258 reg = <0x30230000 0x10000>; 259 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 262 gpio-controller; 263 #gpio-cells = <2>; 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 gpio-ranges = <&iomuxc 21 108 11>; 267 }; 268 269 gpio5: gpio@30240000 { 270 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 271 reg = <0x30240000 0x10000>; 272 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 275 gpio-controller; 276 #gpio-cells = <2>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 gpio-ranges = <&iomuxc 0 119 30>; 280 }; 281 282 wdog1: watchdog@30280000 { 283 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 284 reg = <0x30280000 0x10000>; 285 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 287 status = "disabled"; 288 }; 289 290 wdog2: watchdog@30290000 { 291 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 292 reg = <0x30290000 0x10000>; 293 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 295 status = "disabled"; 296 }; 297 298 wdog3: watchdog@302a0000 { 299 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 300 reg = <0x302a0000 0x10000>; 301 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 303 status = "disabled"; 304 }; 305 306 sdma3: dma-controller@302b0000 { 307 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 308 reg = <0x302b0000 0x10000>; 309 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 311 <&clk IMX8MN_CLK_SDMA3_ROOT>; 312 clock-names = "ipg", "ahb"; 313 #dma-cells = <3>; 314 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 315 }; 316 317 sdma2: dma-controller@302c0000 { 318 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 319 reg = <0x302c0000 0x10000>; 320 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 322 <&clk IMX8MN_CLK_SDMA2_ROOT>; 323 clock-names = "ipg", "ahb"; 324 #dma-cells = <3>; 325 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 326 }; 327 328 iomuxc: pinctrl@30330000 { 329 compatible = "fsl,imx8mn-iomuxc"; 330 reg = <0x30330000 0x10000>; 331 }; 332 333 gpr: iomuxc-gpr@30340000 { 334 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 335 reg = <0x30340000 0x10000>; 336 }; 337 338 ocotp: ocotp-ctrl@30350000 { 339 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 340 reg = <0x30350000 0x10000>; 341 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 345 cpu_speed_grade: speed-grade@10 { 346 reg = <0x10 4>; 347 }; 348 }; 349 350 anatop: anatop@30360000 { 351 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 352 "syscon", "simple-bus"; 353 reg = <0x30360000 0x10000>; 354 }; 355 356 snvs: snvs@30370000 { 357 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 358 reg = <0x30370000 0x10000>; 359 360 snvs_rtc: snvs-rtc-lp { 361 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 362 regmap = <&snvs>; 363 offset = <0x34>; 364 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 366 clock-names = "snvs-rtc"; 367 }; 368 369 snvs_pwrkey: snvs-powerkey { 370 compatible = "fsl,sec-v4.0-pwrkey"; 371 regmap = <&snvs>; 372 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 373 linux,keycode = <KEY_POWER>; 374 wakeup-source; 375 status = "disabled"; 376 }; 377 }; 378 379 clk: clock-controller@30380000 { 380 compatible = "fsl,imx8mn-ccm"; 381 reg = <0x30380000 0x10000>; 382 #clock-cells = <1>; 383 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 384 <&clk_ext3>, <&clk_ext4>; 385 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 386 "clk_ext3", "clk_ext4"; 387 }; 388 389 src: reset-controller@30390000 { 390 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 391 reg = <0x30390000 0x10000>; 392 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 393 #reset-cells = <1>; 394 }; 395 }; 396 397 aips2: bus@30400000 { 398 compatible = "fsl,aips-bus", "simple-bus"; 399 reg = <0x30400000 0x400000>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 404 pwm1: pwm@30660000 { 405 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 406 reg = <0x30660000 0x10000>; 407 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 409 <&clk IMX8MN_CLK_PWM1_ROOT>; 410 clock-names = "ipg", "per"; 411 #pwm-cells = <2>; 412 status = "disabled"; 413 }; 414 415 pwm2: pwm@30670000 { 416 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 417 reg = <0x30670000 0x10000>; 418 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 420 <&clk IMX8MN_CLK_PWM2_ROOT>; 421 clock-names = "ipg", "per"; 422 #pwm-cells = <2>; 423 status = "disabled"; 424 }; 425 426 pwm3: pwm@30680000 { 427 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 428 reg = <0x30680000 0x10000>; 429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 431 <&clk IMX8MN_CLK_PWM3_ROOT>; 432 clock-names = "ipg", "per"; 433 #pwm-cells = <2>; 434 status = "disabled"; 435 }; 436 437 pwm4: pwm@30690000 { 438 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 439 reg = <0x30690000 0x10000>; 440 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 442 <&clk IMX8MN_CLK_PWM4_ROOT>; 443 clock-names = "ipg", "per"; 444 #pwm-cells = <2>; 445 status = "disabled"; 446 }; 447 448 system_counter: timer@306a0000 { 449 compatible = "nxp,sysctr-timer"; 450 reg = <0x306a0000 0x20000>; 451 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&osc_24m>; 453 clock-names = "per"; 454 }; 455 }; 456 457 aips3: bus@30800000 { 458 compatible = "fsl,aips-bus", "simple-bus"; 459 reg = <0x30800000 0x400000>; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 ranges; 463 464 ecspi1: spi@30820000 { 465 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 reg = <0x30820000 0x10000>; 469 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 471 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 472 clock-names = "ipg", "per"; 473 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 474 dma-names = "rx", "tx"; 475 status = "disabled"; 476 }; 477 478 ecspi2: spi@30830000 { 479 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 reg = <0x30830000 0x10000>; 483 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 485 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 486 clock-names = "ipg", "per"; 487 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 488 dma-names = "rx", "tx"; 489 status = "disabled"; 490 }; 491 492 ecspi3: spi@30840000 { 493 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 reg = <0x30840000 0x10000>; 497 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 499 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 500 clock-names = "ipg", "per"; 501 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 502 dma-names = "rx", "tx"; 503 status = "disabled"; 504 }; 505 506 uart1: serial@30860000 { 507 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 508 reg = <0x30860000 0x10000>; 509 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 511 <&clk IMX8MN_CLK_UART1_ROOT>; 512 clock-names = "ipg", "per"; 513 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 514 dma-names = "rx", "tx"; 515 status = "disabled"; 516 }; 517 518 uart3: serial@30880000 { 519 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 520 reg = <0x30880000 0x10000>; 521 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 523 <&clk IMX8MN_CLK_UART3_ROOT>; 524 clock-names = "ipg", "per"; 525 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 526 dma-names = "rx", "tx"; 527 status = "disabled"; 528 }; 529 530 uart2: serial@30890000 { 531 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 532 reg = <0x30890000 0x10000>; 533 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 535 <&clk IMX8MN_CLK_UART2_ROOT>; 536 clock-names = "ipg", "per"; 537 status = "disabled"; 538 }; 539 540 i2c1: i2c@30a20000 { 541 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <0x30a20000 0x10000>; 545 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 547 status = "disabled"; 548 }; 549 550 i2c2: i2c@30a30000 { 551 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 reg = <0x30a30000 0x10000>; 555 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 557 status = "disabled"; 558 }; 559 560 i2c3: i2c@30a40000 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 564 reg = <0x30a40000 0x10000>; 565 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 567 status = "disabled"; 568 }; 569 570 i2c4: i2c@30a50000 { 571 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 reg = <0x30a50000 0x10000>; 575 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 577 status = "disabled"; 578 }; 579 580 uart4: serial@30a60000 { 581 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 582 reg = <0x30a60000 0x10000>; 583 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 585 <&clk IMX8MN_CLK_UART4_ROOT>; 586 clock-names = "ipg", "per"; 587 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 588 dma-names = "rx", "tx"; 589 status = "disabled"; 590 }; 591 592 usdhc1: mmc@30b40000 { 593 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 594 reg = <0x30b40000 0x10000>; 595 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clk IMX8MN_CLK_DUMMY>, 597 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 598 <&clk IMX8MN_CLK_USDHC1_ROOT>; 599 clock-names = "ipg", "ahb", "per"; 600 fsl,tuning-start-tap = <20>; 601 fsl,tuning-step= <2>; 602 bus-width = <4>; 603 status = "disabled"; 604 }; 605 606 usdhc2: mmc@30b50000 { 607 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 608 reg = <0x30b50000 0x10000>; 609 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MN_CLK_DUMMY>, 611 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 612 <&clk IMX8MN_CLK_USDHC2_ROOT>; 613 clock-names = "ipg", "ahb", "per"; 614 fsl,tuning-start-tap = <20>; 615 fsl,tuning-step= <2>; 616 bus-width = <4>; 617 status = "disabled"; 618 }; 619 620 usdhc3: mmc@30b60000 { 621 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 622 reg = <0x30b60000 0x10000>; 623 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clk IMX8MN_CLK_DUMMY>, 625 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 626 <&clk IMX8MN_CLK_USDHC3_ROOT>; 627 clock-names = "ipg", "ahb", "per"; 628 fsl,tuning-start-tap = <20>; 629 fsl,tuning-step= <2>; 630 bus-width = <4>; 631 status = "disabled"; 632 }; 633 634 sdma1: dma-controller@30bd0000 { 635 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 636 reg = <0x30bd0000 0x10000>; 637 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 639 <&clk IMX8MN_CLK_SDMA1_ROOT>; 640 clock-names = "ipg", "ahb"; 641 #dma-cells = <3>; 642 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 643 }; 644 645 fec1: ethernet@30be0000 { 646 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; 647 reg = <0x30be0000 0x10000>; 648 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 652 <&clk IMX8MN_CLK_ENET1_ROOT>, 653 <&clk IMX8MN_CLK_ENET_TIMER>, 654 <&clk IMX8MN_CLK_ENET_REF>, 655 <&clk IMX8MN_CLK_ENET_PHY_REF>; 656 clock-names = "ipg", "ahb", "ptp", 657 "enet_clk_ref", "enet_out"; 658 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 659 <&clk IMX8MN_CLK_ENET_TIMER>, 660 <&clk IMX8MN_CLK_ENET_REF>, 661 <&clk IMX8MN_CLK_ENET_TIMER>; 662 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 663 <&clk IMX8MN_SYS_PLL2_100M>, 664 <&clk IMX8MN_SYS_PLL2_125M>; 665 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 666 fsl,num-tx-queues = <3>; 667 fsl,num-rx-queues = <3>; 668 status = "disabled"; 669 }; 670 671 }; 672 673 aips4: bus@32c00000 { 674 compatible = "fsl,aips-bus", "simple-bus"; 675 reg = <0x32c00000 0x400000>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges; 679 680 usbotg1: usb@32e40000 { 681 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 682 reg = <0x32e40000 0x200>; 683 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 685 clock-names = "usb1_ctrl_root_clk"; 686 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 687 <&clk IMX8MN_CLK_USB_CORE_REF>; 688 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 689 <&clk IMX8MN_SYS_PLL1_100M>; 690 fsl,usbphy = <&usbphynop1>; 691 fsl,usbmisc = <&usbmisc1 0>; 692 status = "disabled"; 693 }; 694 695 usbmisc1: usbmisc@32e40200 { 696 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 697 #index-cells = <1>; 698 reg = <0x32e40200 0x200>; 699 }; 700 701 usbotg2: usb@32e50000 { 702 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 703 reg = <0x32e50000 0x200>; 704 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 706 clock-names = "usb1_ctrl_root_clk"; 707 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 708 <&clk IMX8MN_CLK_USB_CORE_REF>; 709 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 710 <&clk IMX8MN_SYS_PLL1_100M>; 711 fsl,usbphy = <&usbphynop2>; 712 fsl,usbmisc = <&usbmisc2 0>; 713 status = "disabled"; 714 }; 715 716 usbmisc2: usbmisc@32e50200 { 717 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 718 #index-cells = <1>; 719 reg = <0x32e50200 0x200>; 720 }; 721 722 }; 723 724 dma_apbh: dma-controller@33000000 { 725 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 726 reg = <0x33000000 0x2000>; 727 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 732 #dma-cells = <1>; 733 dma-channels = <4>; 734 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 735 }; 736 737 gpmi: nand-controller@33002000 { 738 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 739 #address-cells = <1>; 740 #size-cells = <1>; 741 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 742 reg-names = "gpmi-nand", "bch"; 743 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 744 interrupt-names = "bch"; 745 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 746 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 747 clock-names = "gpmi_io", "gpmi_bch_apb"; 748 dmas = <&dma_apbh 0>; 749 dma-names = "rx-tx"; 750 status = "disabled"; 751 }; 752 753 gic: interrupt-controller@38800000 { 754 compatible = "arm,gic-v3"; 755 reg = <0x38800000 0x10000>, 756 <0x38880000 0xc0000>; 757 #interrupt-cells = <3>; 758 interrupt-controller; 759 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 760 }; 761 762 ddr-pmu@3d800000 { 763 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 764 reg = <0x3d800000 0x400000>; 765 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 766 }; 767 }; 768 769 usbphynop1: usbphynop1 { 770 compatible = "usb-nop-xceiv"; 771 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 772 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 773 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 774 clock-names = "main_clk"; 775 }; 776 777 usbphynop2: usbphynop2 { 778 compatible = "usb-nop-xceiv"; 779 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 780 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 781 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 782 clock-names = "main_clk"; 783 }; 784}; 785