1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx8mn-pinfunc.h" 12 13/ { 14 compatible = "fsl,imx8mn"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; 64 clocks = <&clk IMX8MN_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 }; 72 73 A53_1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x1>; 77 clock-latency = <61036>; 78 clocks = <&clk IMX8MN_CLK_ARM>; 79 enable-method = "psci"; 80 next-level-cache = <&A53_L2>; 81 operating-points-v2 = <&a53_opp_table>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 }; 84 85 A53_2: cpu@2 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x2>; 89 clock-latency = <61036>; 90 clocks = <&clk IMX8MN_CLK_ARM>; 91 enable-method = "psci"; 92 next-level-cache = <&A53_L2>; 93 operating-points-v2 = <&a53_opp_table>; 94 cpu-idle-states = <&cpu_pd_wait>; 95 }; 96 97 A53_3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x3>; 101 clock-latency = <61036>; 102 clocks = <&clk IMX8MN_CLK_ARM>; 103 enable-method = "psci"; 104 next-level-cache = <&A53_L2>; 105 operating-points-v2 = <&a53_opp_table>; 106 cpu-idle-states = <&cpu_pd_wait>; 107 }; 108 109 A53_L2: l2-cache0 { 110 compatible = "cache"; 111 }; 112 }; 113 114 a53_opp_table: opp-table { 115 compatible = "operating-points-v2"; 116 opp-shared; 117 118 opp-1200000000 { 119 opp-hz = /bits/ 64 <1200000000>; 120 opp-microvolt = <850000>; 121 opp-supported-hw = <0xb00>, <0x7>; 122 clock-latency-ns = <150000>; 123 opp-suspend; 124 }; 125 126 opp-1400000000 { 127 opp-hz = /bits/ 64 <1400000000>; 128 opp-microvolt = <950000>; 129 opp-supported-hw = <0x300>, <0x7>; 130 clock-latency-ns = <150000>; 131 opp-suspend; 132 }; 133 134 opp-1500000000 { 135 opp-hz = /bits/ 64 <1500000000>; 136 opp-microvolt = <1000000>; 137 opp-supported-hw = <0x100>, <0x3>; 138 clock-latency-ns = <150000>; 139 opp-suspend; 140 }; 141 }; 142 143 memory@40000000 { 144 device_type = "memory"; 145 reg = <0x0 0x40000000 0 0x80000000>; 146 }; 147 148 osc_32k: clock-osc-32k { 149 compatible = "fixed-clock"; 150 #clock-cells = <0>; 151 clock-frequency = <32768>; 152 clock-output-names = "osc_32k"; 153 }; 154 155 osc_24m: clock-osc-24m { 156 compatible = "fixed-clock"; 157 #clock-cells = <0>; 158 clock-frequency = <24000000>; 159 clock-output-names = "osc_24m"; 160 }; 161 162 clk_ext1: clock-ext1 { 163 compatible = "fixed-clock"; 164 #clock-cells = <0>; 165 clock-frequency = <133000000>; 166 clock-output-names = "clk_ext1"; 167 }; 168 169 clk_ext2: clock-ext2 { 170 compatible = "fixed-clock"; 171 #clock-cells = <0>; 172 clock-frequency = <133000000>; 173 clock-output-names = "clk_ext2"; 174 }; 175 176 clk_ext3: clock-ext3 { 177 compatible = "fixed-clock"; 178 #clock-cells = <0>; 179 clock-frequency = <133000000>; 180 clock-output-names = "clk_ext3"; 181 }; 182 183 clk_ext4: clock-ext4 { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency= <133000000>; 187 clock-output-names = "clk_ext4"; 188 }; 189 190 psci { 191 compatible = "arm,psci-1.0"; 192 method = "smc"; 193 }; 194 195 timer { 196 compatible = "arm,armv8-timer"; 197 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 198 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 201 clock-frequency = <8000000>; 202 arm,no-tick-in-suspend; 203 }; 204 205 soc@0 { 206 compatible = "simple-bus"; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges = <0x0 0x0 0x0 0x3e000000>; 210 211 aips1: bus@30000000 { 212 compatible = "fsl,aips-bus", "simple-bus"; 213 reg = <0x30000000 0x400000>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges; 217 218 gpio1: gpio@30200000 { 219 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 220 reg = <0x30200000 0x10000>; 221 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 224 gpio-controller; 225 #gpio-cells = <2>; 226 interrupt-controller; 227 #interrupt-cells = <2>; 228 gpio-ranges = <&iomuxc 0 10 30>; 229 }; 230 231 gpio2: gpio@30210000 { 232 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 233 reg = <0x30210000 0x10000>; 234 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 gpio-ranges = <&iomuxc 0 40 21>; 242 }; 243 244 gpio3: gpio@30220000 { 245 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 246 reg = <0x30220000 0x10000>; 247 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 250 gpio-controller; 251 #gpio-cells = <2>; 252 interrupt-controller; 253 #interrupt-cells = <2>; 254 gpio-ranges = <&iomuxc 0 61 26>; 255 }; 256 257 gpio4: gpio@30230000 { 258 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 259 reg = <0x30230000 0x10000>; 260 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 263 gpio-controller; 264 #gpio-cells = <2>; 265 interrupt-controller; 266 #interrupt-cells = <2>; 267 gpio-ranges = <&iomuxc 21 108 11>; 268 }; 269 270 gpio5: gpio@30240000 { 271 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 272 reg = <0x30240000 0x10000>; 273 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 276 gpio-controller; 277 #gpio-cells = <2>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 gpio-ranges = <&iomuxc 0 119 30>; 281 }; 282 283 wdog1: watchdog@30280000 { 284 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 285 reg = <0x30280000 0x10000>; 286 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 288 status = "disabled"; 289 }; 290 291 wdog2: watchdog@30290000 { 292 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 293 reg = <0x30290000 0x10000>; 294 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 296 status = "disabled"; 297 }; 298 299 wdog3: watchdog@302a0000 { 300 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 301 reg = <0x302a0000 0x10000>; 302 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 304 status = "disabled"; 305 }; 306 307 sdma3: dma-controller@302b0000 { 308 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 309 reg = <0x302b0000 0x10000>; 310 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 312 <&clk IMX8MN_CLK_SDMA3_ROOT>; 313 clock-names = "ipg", "ahb"; 314 #dma-cells = <3>; 315 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 316 }; 317 318 sdma2: dma-controller@302c0000 { 319 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 320 reg = <0x302c0000 0x10000>; 321 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 323 <&clk IMX8MN_CLK_SDMA2_ROOT>; 324 clock-names = "ipg", "ahb"; 325 #dma-cells = <3>; 326 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 327 }; 328 329 iomuxc: pinctrl@30330000 { 330 compatible = "fsl,imx8mn-iomuxc"; 331 reg = <0x30330000 0x10000>; 332 }; 333 334 gpr: iomuxc-gpr@30340000 { 335 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 336 reg = <0x30340000 0x10000>; 337 }; 338 339 ocotp: ocotp-ctrl@30350000 { 340 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 341 reg = <0x30350000 0x10000>; 342 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 343 #address-cells = <1>; 344 #size-cells = <1>; 345 346 cpu_speed_grade: speed-grade@10 { 347 reg = <0x10 4>; 348 }; 349 }; 350 351 anatop: anatop@30360000 { 352 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", 353 "syscon", "simple-bus"; 354 reg = <0x30360000 0x10000>; 355 }; 356 357 snvs: snvs@30370000 { 358 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 359 reg = <0x30370000 0x10000>; 360 361 snvs_rtc: snvs-rtc-lp { 362 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 363 regmap = <&snvs>; 364 offset = <0x34>; 365 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 367 clock-names = "snvs-rtc"; 368 }; 369 370 snvs_pwrkey: snvs-powerkey { 371 compatible = "fsl,sec-v4.0-pwrkey"; 372 regmap = <&snvs>; 373 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 374 linux,keycode = <KEY_POWER>; 375 wakeup-source; 376 status = "disabled"; 377 }; 378 }; 379 380 clk: clock-controller@30380000 { 381 compatible = "fsl,imx8mn-ccm"; 382 reg = <0x30380000 0x10000>; 383 #clock-cells = <1>; 384 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 385 <&clk_ext3>, <&clk_ext4>; 386 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 387 "clk_ext3", "clk_ext4"; 388 }; 389 390 src: reset-controller@30390000 { 391 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 392 reg = <0x30390000 0x10000>; 393 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 394 #reset-cells = <1>; 395 }; 396 }; 397 398 aips2: bus@30400000 { 399 compatible = "fsl,aips-bus", "simple-bus"; 400 reg = <0x30400000 0x400000>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges; 404 405 pwm1: pwm@30660000 { 406 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 407 reg = <0x30660000 0x10000>; 408 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 410 <&clk IMX8MN_CLK_PWM1_ROOT>; 411 clock-names = "ipg", "per"; 412 #pwm-cells = <2>; 413 status = "disabled"; 414 }; 415 416 pwm2: pwm@30670000 { 417 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 418 reg = <0x30670000 0x10000>; 419 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 421 <&clk IMX8MN_CLK_PWM2_ROOT>; 422 clock-names = "ipg", "per"; 423 #pwm-cells = <2>; 424 status = "disabled"; 425 }; 426 427 pwm3: pwm@30680000 { 428 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 429 reg = <0x30680000 0x10000>; 430 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 432 <&clk IMX8MN_CLK_PWM3_ROOT>; 433 clock-names = "ipg", "per"; 434 #pwm-cells = <2>; 435 status = "disabled"; 436 }; 437 438 pwm4: pwm@30690000 { 439 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 440 reg = <0x30690000 0x10000>; 441 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 443 <&clk IMX8MN_CLK_PWM4_ROOT>; 444 clock-names = "ipg", "per"; 445 #pwm-cells = <2>; 446 status = "disabled"; 447 }; 448 449 system_counter: timer@306a0000 { 450 compatible = "nxp,sysctr-timer"; 451 reg = <0x306a0000 0x20000>; 452 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&osc_24m>; 454 clock-names = "per"; 455 }; 456 }; 457 458 aips3: bus@30800000 { 459 compatible = "fsl,aips-bus", "simple-bus"; 460 reg = <0x30800000 0x400000>; 461 #address-cells = <1>; 462 #size-cells = <1>; 463 ranges; 464 465 ecspi1: spi@30820000 { 466 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <0x30820000 0x10000>; 470 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 472 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 473 clock-names = "ipg", "per"; 474 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 ecspi2: spi@30830000 { 480 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 reg = <0x30830000 0x10000>; 484 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 486 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 487 clock-names = "ipg", "per"; 488 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 489 dma-names = "rx", "tx"; 490 status = "disabled"; 491 }; 492 493 ecspi3: spi@30840000 { 494 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <0x30840000 0x10000>; 498 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 500 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 501 clock-names = "ipg", "per"; 502 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 503 dma-names = "rx", "tx"; 504 status = "disabled"; 505 }; 506 507 uart1: serial@30860000 { 508 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 509 reg = <0x30860000 0x10000>; 510 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 512 <&clk IMX8MN_CLK_UART1_ROOT>; 513 clock-names = "ipg", "per"; 514 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 uart3: serial@30880000 { 520 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 521 reg = <0x30880000 0x10000>; 522 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 524 <&clk IMX8MN_CLK_UART3_ROOT>; 525 clock-names = "ipg", "per"; 526 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 527 dma-names = "rx", "tx"; 528 status = "disabled"; 529 }; 530 531 uart2: serial@30890000 { 532 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 533 reg = <0x30890000 0x10000>; 534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 536 <&clk IMX8MN_CLK_UART2_ROOT>; 537 clock-names = "ipg", "per"; 538 status = "disabled"; 539 }; 540 541 i2c1: i2c@30a20000 { 542 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 reg = <0x30a20000 0x10000>; 546 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 548 status = "disabled"; 549 }; 550 551 i2c2: i2c@30a30000 { 552 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <0x30a30000 0x10000>; 556 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 558 status = "disabled"; 559 }; 560 561 i2c3: i2c@30a40000 { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 565 reg = <0x30a40000 0x10000>; 566 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 568 status = "disabled"; 569 }; 570 571 i2c4: i2c@30a50000 { 572 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 reg = <0x30a50000 0x10000>; 576 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 578 status = "disabled"; 579 }; 580 581 uart4: serial@30a60000 { 582 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 583 reg = <0x30a60000 0x10000>; 584 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 586 <&clk IMX8MN_CLK_UART4_ROOT>; 587 clock-names = "ipg", "per"; 588 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 589 dma-names = "rx", "tx"; 590 status = "disabled"; 591 }; 592 593 usdhc1: mmc@30b40000 { 594 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 595 reg = <0x30b40000 0x10000>; 596 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&clk IMX8MN_CLK_DUMMY>, 598 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 599 <&clk IMX8MN_CLK_USDHC1_ROOT>; 600 clock-names = "ipg", "ahb", "per"; 601 fsl,tuning-start-tap = <20>; 602 fsl,tuning-step= <2>; 603 bus-width = <4>; 604 status = "disabled"; 605 }; 606 607 usdhc2: mmc@30b50000 { 608 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 609 reg = <0x30b50000 0x10000>; 610 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&clk IMX8MN_CLK_DUMMY>, 612 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 613 <&clk IMX8MN_CLK_USDHC2_ROOT>; 614 clock-names = "ipg", "ahb", "per"; 615 fsl,tuning-start-tap = <20>; 616 fsl,tuning-step= <2>; 617 bus-width = <4>; 618 status = "disabled"; 619 }; 620 621 usdhc3: mmc@30b60000 { 622 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; 623 reg = <0x30b60000 0x10000>; 624 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX8MN_CLK_DUMMY>, 626 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 627 <&clk IMX8MN_CLK_USDHC3_ROOT>; 628 clock-names = "ipg", "ahb", "per"; 629 fsl,tuning-start-tap = <20>; 630 fsl,tuning-step= <2>; 631 bus-width = <4>; 632 status = "disabled"; 633 }; 634 635 sdma1: dma-controller@30bd0000 { 636 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; 637 reg = <0x30bd0000 0x10000>; 638 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 640 <&clk IMX8MN_CLK_SDMA1_ROOT>; 641 clock-names = "ipg", "ahb"; 642 #dma-cells = <3>; 643 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 644 }; 645 646 fec1: ethernet@30be0000 { 647 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; 648 reg = <0x30be0000 0x10000>; 649 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 653 <&clk IMX8MN_CLK_ENET1_ROOT>, 654 <&clk IMX8MN_CLK_ENET_TIMER>, 655 <&clk IMX8MN_CLK_ENET_REF>, 656 <&clk IMX8MN_CLK_ENET_PHY_REF>; 657 clock-names = "ipg", "ahb", "ptp", 658 "enet_clk_ref", "enet_out"; 659 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 660 <&clk IMX8MN_CLK_ENET_TIMER>, 661 <&clk IMX8MN_CLK_ENET_REF>, 662 <&clk IMX8MN_CLK_ENET_TIMER>; 663 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 664 <&clk IMX8MN_SYS_PLL2_100M>, 665 <&clk IMX8MN_SYS_PLL2_125M>; 666 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 667 fsl,num-tx-queues = <3>; 668 fsl,num-rx-queues = <3>; 669 status = "disabled"; 670 }; 671 672 }; 673 674 aips4: bus@32c00000 { 675 compatible = "fsl,aips-bus", "simple-bus"; 676 reg = <0x32c00000 0x400000>; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 ranges; 680 681 usbotg1: usb@32e40000 { 682 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 683 reg = <0x32e40000 0x200>; 684 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 686 clock-names = "usb1_ctrl_root_clk"; 687 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 688 <&clk IMX8MN_CLK_USB_CORE_REF>; 689 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 690 <&clk IMX8MN_SYS_PLL1_100M>; 691 fsl,usbphy = <&usbphynop1>; 692 fsl,usbmisc = <&usbmisc1 0>; 693 status = "disabled"; 694 }; 695 696 usbmisc1: usbmisc@32e40200 { 697 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 698 #index-cells = <1>; 699 reg = <0x32e40200 0x200>; 700 }; 701 702 usbotg2: usb@32e50000 { 703 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 704 reg = <0x32e50000 0x200>; 705 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 707 clock-names = "usb1_ctrl_root_clk"; 708 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, 709 <&clk IMX8MN_CLK_USB_CORE_REF>; 710 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, 711 <&clk IMX8MN_SYS_PLL1_100M>; 712 fsl,usbphy = <&usbphynop2>; 713 fsl,usbmisc = <&usbmisc2 0>; 714 status = "disabled"; 715 }; 716 717 usbmisc2: usbmisc@32e50200 { 718 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 719 #index-cells = <1>; 720 reg = <0x32e50200 0x200>; 721 }; 722 723 }; 724 725 dma_apbh: dma-controller@33000000 { 726 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 727 reg = <0x33000000 0x2000>; 728 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 733 #dma-cells = <1>; 734 dma-channels = <4>; 735 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 736 }; 737 738 gpmi: nand-controller@33002000 { 739 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 740 #address-cells = <1>; 741 #size-cells = <1>; 742 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 743 reg-names = "gpmi-nand", "bch"; 744 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 745 interrupt-names = "bch"; 746 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 747 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 748 clock-names = "gpmi_io", "gpmi_bch_apb"; 749 dmas = <&dma_apbh 0>; 750 dma-names = "rx-tx"; 751 status = "disabled"; 752 }; 753 754 gic: interrupt-controller@38800000 { 755 compatible = "arm,gic-v3"; 756 reg = <0x38800000 0x10000>, 757 <0x38880000 0xc0000>; 758 #interrupt-cells = <3>; 759 interrupt-controller; 760 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 ddr-pmu@3d800000 { 764 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 765 reg = <0x3d800000 0x400000>; 766 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 767 }; 768 }; 769 770 usbphynop1: usbphynop1 { 771 compatible = "usb-nop-xceiv"; 772 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 773 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 774 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 775 clock-names = "main_clk"; 776 }; 777 778 usbphynop2: usbphynop2 { 779 compatible = "usb-nop-xceiv"; 780 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 781 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 782 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 783 clock-names = "main_clk"; 784 }; 785}; 786