1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mn.dtsi"
14
15/ {
16	model = "Gateworks Venice GW7902 i.MX8MN board";
17	compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18
19	aliases {
20		usb0 = &usbotg1;
21	};
22
23	chosen {
24		stdout-path = &uart2;
25	};
26
27	memory@40000000 {
28		device_type = "memory";
29		reg = <0x0 0x40000000 0 0x80000000>;
30	};
31
32	can20m: can20m {
33		compatible = "fixed-clock";
34		#clock-cells = <0>;
35		clock-frequency = <20000000>;
36		clock-output-names = "can20m";
37	};
38
39	gpio-keys {
40		compatible = "gpio-keys";
41
42		key-user-pb {
43			label = "user_pb";
44			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45			linux,code = <BTN_0>;
46		};
47
48		key-user-pb1x {
49			label = "user_pb1x";
50			linux,code = <BTN_1>;
51			interrupt-parent = <&gsc>;
52			interrupts = <0>;
53		};
54
55		key-erased {
56			label = "key_erased";
57			linux,code = <BTN_2>;
58			interrupt-parent = <&gsc>;
59			interrupts = <1>;
60		};
61
62		key-eeprom-wp {
63			label = "eeprom_wp";
64			linux,code = <BTN_3>;
65			interrupt-parent = <&gsc>;
66			interrupts = <2>;
67		};
68
69		key-tamper {
70			label = "tamper";
71			linux,code = <BTN_4>;
72			interrupt-parent = <&gsc>;
73			interrupts = <5>;
74		};
75
76		switch-hold {
77			label = "switch_hold";
78			linux,code = <BTN_5>;
79			interrupt-parent = <&gsc>;
80			interrupts = <7>;
81		};
82	};
83
84	led-controller {
85		compatible = "gpio-leds";
86		pinctrl-names = "default";
87		pinctrl-0 = <&pinctrl_gpio_leds>;
88
89		led-0 {
90			function = LED_FUNCTION_STATUS;
91			color = <LED_COLOR_ID_GREEN>;
92			label = "panel1";
93			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94			default-state = "off";
95		};
96
97		led-1 {
98			function = LED_FUNCTION_STATUS;
99			color = <LED_COLOR_ID_GREEN>;
100			label = "panel2";
101			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102			default-state = "off";
103		};
104
105		led-2 {
106			function = LED_FUNCTION_STATUS;
107			color = <LED_COLOR_ID_GREEN>;
108			label = "panel3";
109			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110			default-state = "off";
111		};
112
113		led-3 {
114			function = LED_FUNCTION_STATUS;
115			color = <LED_COLOR_ID_GREEN>;
116			label = "panel4";
117			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118			default-state = "off";
119		};
120
121		led-4 {
122			function = LED_FUNCTION_STATUS;
123			color = <LED_COLOR_ID_GREEN>;
124			label = "panel5";
125			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126			default-state = "off";
127		};
128	};
129
130	pps {
131		compatible = "pps-gpio";
132		pinctrl-names = "default";
133		pinctrl-0 = <&pinctrl_pps>;
134		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135		status = "okay";
136	};
137
138	reg_3p3v: regulator-3p3v {
139		compatible = "regulator-fixed";
140		regulator-name = "3P3V";
141		regulator-min-microvolt = <3300000>;
142		regulator-max-microvolt = <3300000>;
143		regulator-always-on;
144	};
145
146	reg_usb1_vbus: regulator-usb1 {
147		compatible = "regulator-fixed";
148		pinctrl-names = "default";
149		pinctrl-0 = <&pinctrl_reg_usb1>;
150		regulator-name = "usb_usb1_vbus";
151		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152		enable-active-high;
153		regulator-min-microvolt = <5000000>;
154		regulator-max-microvolt = <5000000>;
155	};
156
157	reg_wifi: regulator-wifi {
158		compatible = "regulator-fixed";
159		pinctrl-names = "default";
160		pinctrl-0 = <&pinctrl_reg_wl>;
161		regulator-name = "wifi";
162		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163		enable-active-high;
164		startup-delay-us = <100>;
165		regulator-min-microvolt = <3300000>;
166		regulator-max-microvolt = <3300000>;
167	};
168};
169
170&A53_0 {
171	cpu-supply = <&buck2>;
172};
173
174&A53_1 {
175	cpu-supply = <&buck2>;
176};
177
178&A53_2 {
179	cpu-supply = <&buck2>;
180};
181
182&A53_3 {
183	cpu-supply = <&buck2>;
184};
185
186&ddrc {
187	operating-points-v2 = <&ddrc_opp_table>;
188
189	ddrc_opp_table: opp-table {
190		compatible = "operating-points-v2";
191
192		opp-25M {
193			opp-hz = /bits/ 64 <25000000>;
194		};
195
196		opp-100M {
197			opp-hz = /bits/ 64 <100000000>;
198		};
199
200		opp-750M {
201			opp-hz = /bits/ 64 <750000000>;
202		};
203	};
204};
205
206&ecspi1 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_spi1>;
209	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210	status = "okay";
211
212	can@0 {
213		compatible = "microchip,mcp2515";
214		reg = <0>;
215		clocks = <&can20m>;
216		interrupt-parent = <&gpio2>;
217		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218		spi-max-frequency = <10000000>;
219	};
220};
221
222&disp_blk_ctrl {
223	status = "disabled";
224};
225
226/* off-board header */
227&ecspi2 {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_spi2>;
230	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
231	status = "okay";
232};
233
234&fec1 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_fec1>;
237	phy-mode = "rgmii-id";
238	phy-handle = <&ethphy0>;
239	local-mac-address = [00 00 00 00 00 00];
240	status = "okay";
241
242	mdio {
243		#address-cells = <1>;
244		#size-cells = <0>;
245
246		ethphy0: ethernet-phy@0 {
247			compatible = "ethernet-phy-ieee802.3-c22";
248			reg = <0>;
249			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253		};
254	};
255};
256
257&gpio1 {
258	gpio-line-names = "", "", "", "", "", "", "", "",
259		"", "", "", "", "", "m2_reset", "", "m2_wdis#",
260		"", "", "", "", "", "", "", "",
261		"", "", "", "", "", "", "", "";
262};
263
264&gpio2 {
265	gpio-line-names = "", "", "", "", "", "", "", "",
266		"uart2_en#", "", "", "", "", "", "", "",
267		"", "", "", "", "", "", "", "",
268		"", "", "", "", "", "", "", "";
269};
270
271&gpio3 {
272	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
273		"", "", "", "", "", "", "", "",
274		"", "", "", "", "", "", "", "",
275		"", "", "", "", "", "", "", "";
276};
277
278&gpio4 {
279	gpio-line-names = "", "", "", "", "", "", "", "",
280		"", "", "", "", "", "", "", "",
281		"", "", "", "", "", "app_gpio1", "", "uart1_rs485",
282		"", "uart1_term", "uart1_half", "app_gpio2",
283		"mipi_gpio1", "", "", "";
284};
285
286&gpio5 {
287	gpio-line-names = "", "", "", "mipi_gpio4",
288		"mipi_gpio3", "mipi_gpio2", "", "",
289		"", "", "", "", "", "", "", "",
290		"", "", "", "", "", "", "", "",
291		"", "", "", "", "", "", "", "";
292};
293
294&gpu {
295	status = "disabled";
296};
297
298&i2c1 {
299	clock-frequency = <100000>;
300	pinctrl-names = "default";
301	pinctrl-0 = <&pinctrl_i2c1>;
302	status = "okay";
303
304	gsc: gsc@20 {
305		compatible = "gw,gsc";
306		reg = <0x20>;
307		pinctrl-0 = <&pinctrl_gsc>;
308		interrupt-parent = <&gpio2>;
309		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
310		interrupt-controller;
311		#interrupt-cells = <1>;
312
313		adc {
314			compatible = "gw,gsc-adc";
315			#address-cells = <1>;
316			#size-cells = <0>;
317
318			channel@6 {
319				gw,mode = <0>;
320				reg = <0x06>;
321				label = "temp";
322			};
323
324			channel@8 {
325				gw,mode = <1>;
326				reg = <0x08>;
327				label = "vdd_bat";
328			};
329
330			channel@82 {
331				gw,mode = <2>;
332				reg = <0x82>;
333				label = "vin";
334				gw,voltage-divider-ohms = <22100 1000>;
335				gw,voltage-offset-microvolt = <700000>;
336			};
337
338			channel@84 {
339				gw,mode = <2>;
340				reg = <0x84>;
341				label = "vin_4p0";
342				gw,voltage-divider-ohms = <10000 10000>;
343			};
344
345			channel@86 {
346				gw,mode = <2>;
347				reg = <0x86>;
348				label = "vdd_3p3";
349				gw,voltage-divider-ohms = <10000 10000>;
350			};
351
352			channel@88 {
353				gw,mode = <2>;
354				reg = <0x88>;
355				label = "vdd_0p9";
356			};
357
358			channel@8c {
359				gw,mode = <2>;
360				reg = <0x8c>;
361				label = "vdd_soc";
362			};
363
364			channel@8e {
365				gw,mode = <2>;
366				reg = <0x8e>;
367				label = "vdd_arm";
368			};
369
370			channel@90 {
371				gw,mode = <2>;
372				reg = <0x90>;
373				label = "vdd_1p8";
374			};
375
376			channel@92 {
377				gw,mode = <2>;
378				reg = <0x92>;
379				label = "vdd_dram";
380			};
381
382			channel@98 {
383				gw,mode = <2>;
384				reg = <0x98>;
385				label = "vdd_1p0";
386			};
387
388			channel@9a {
389				gw,mode = <2>;
390				reg = <0x9a>;
391				label = "vdd_2p5";
392				gw,voltage-divider-ohms = <10000 10000>;
393			};
394
395			channel@9c {
396				gw,mode = <2>;
397				reg = <0x9c>;
398				label = "vdd_5p0";
399				gw,voltage-divider-ohms = <10000 10000>;
400			};
401
402			channel@a2 {
403				gw,mode = <2>;
404				reg = <0xa2>;
405				label = "vdd_gsc";
406				gw,voltage-divider-ohms = <10000 10000>;
407			};
408		};
409	};
410
411	gpio: gpio@23 {
412		compatible = "nxp,pca9555";
413		reg = <0x23>;
414		gpio-controller;
415		#gpio-cells = <2>;
416		interrupt-parent = <&gsc>;
417		interrupts = <4>;
418	};
419
420	pmic@4b {
421		compatible = "rohm,bd71847";
422		reg = <0x4b>;
423		pinctrl-names = "default";
424		pinctrl-0 = <&pinctrl_pmic>;
425		interrupt-parent = <&gpio3>;
426		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
427		rohm,reset-snvs-powered;
428		#clock-cells = <0>;
429		clocks = <&osc_32k 0>;
430		clock-output-names = "clk-32k-out";
431
432		regulators {
433			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
434			BUCK1 {
435				regulator-name = "buck1";
436				regulator-min-microvolt = <700000>;
437				regulator-max-microvolt = <1300000>;
438				regulator-boot-on;
439				regulator-always-on;
440				regulator-ramp-delay = <1250>;
441			};
442
443			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
444			buck2: BUCK2 {
445				regulator-name = "buck2";
446				regulator-min-microvolt = <700000>;
447				regulator-max-microvolt = <1300000>;
448				regulator-boot-on;
449				regulator-always-on;
450				regulator-ramp-delay = <1250>;
451				rohm,dvs-run-voltage = <1000000>;
452				rohm,dvs-idle-voltage = <900000>;
453			};
454
455			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
456			BUCK3 {
457				regulator-name = "buck3";
458				regulator-min-microvolt = <700000>;
459				regulator-max-microvolt = <1350000>;
460				regulator-boot-on;
461				regulator-always-on;
462			};
463
464			/* vdd_3p3 */
465			BUCK4 {
466				regulator-name = "buck4";
467				regulator-min-microvolt = <3000000>;
468				regulator-max-microvolt = <3300000>;
469				regulator-boot-on;
470				regulator-always-on;
471			};
472
473			/* vdd_1p8 */
474			BUCK5 {
475				regulator-name = "buck5";
476				regulator-min-microvolt = <1605000>;
477				regulator-max-microvolt = <1995000>;
478				regulator-boot-on;
479				regulator-always-on;
480			};
481
482			/* vdd_dram */
483			BUCK6 {
484				regulator-name = "buck6";
485				regulator-min-microvolt = <800000>;
486				regulator-max-microvolt = <1400000>;
487				regulator-boot-on;
488				regulator-always-on;
489			};
490
491			/* nvcc_snvs_1p8 */
492			LDO1 {
493				regulator-name = "ldo1";
494				regulator-min-microvolt = <1600000>;
495				regulator-max-microvolt = <1900000>;
496				regulator-boot-on;
497				regulator-always-on;
498			};
499
500			/* vdd_snvs_0p8 */
501			LDO2 {
502				regulator-name = "ldo2";
503				regulator-min-microvolt = <800000>;
504				regulator-max-microvolt = <900000>;
505				regulator-boot-on;
506				regulator-always-on;
507			};
508
509			/* vdda_1p8 */
510			LDO3 {
511				regulator-name = "ldo3";
512				regulator-min-microvolt = <1800000>;
513				regulator-max-microvolt = <3300000>;
514				regulator-boot-on;
515				regulator-always-on;
516			};
517
518			LDO4 {
519				regulator-name = "ldo4";
520				regulator-min-microvolt = <900000>;
521				regulator-max-microvolt = <1800000>;
522				regulator-boot-on;
523				regulator-always-on;
524			};
525
526			LDO6 {
527				regulator-name = "ldo6";
528				regulator-min-microvolt = <900000>;
529				regulator-max-microvolt = <1800000>;
530				regulator-boot-on;
531				regulator-always-on;
532			};
533		};
534	};
535
536	eeprom@50 {
537		compatible = "atmel,24c02";
538		reg = <0x50>;
539		pagesize = <16>;
540	};
541
542	eeprom@51 {
543		compatible = "atmel,24c02";
544		reg = <0x51>;
545		pagesize = <16>;
546	};
547
548	eeprom@52 {
549		compatible = "atmel,24c02";
550		reg = <0x52>;
551		pagesize = <16>;
552	};
553
554	eeprom@53 {
555		compatible = "atmel,24c02";
556		reg = <0x53>;
557		pagesize = <16>;
558	};
559
560	rtc@68 {
561		compatible = "dallas,ds1672";
562		reg = <0x68>;
563	};
564};
565
566&i2c2 {
567	clock-frequency = <400000>;
568	pinctrl-names = "default";
569	pinctrl-0 = <&pinctrl_i2c2>;
570	status = "okay";
571
572	accelerometer@19 {
573		compatible = "st,lis2de12";
574		pinctrl-names = "default";
575		pinctrl-0 = <&pinctrl_accel>;
576		reg = <0x19>;
577		st,drdy-int-pin = <1>;
578		interrupt-parent = <&gpio1>;
579		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
580		interrupt-names = "INT1";
581	};
582};
583
584/* off-board header */
585&i2c3 {
586	clock-frequency = <400000>;
587	pinctrl-names = "default";
588	pinctrl-0 = <&pinctrl_i2c3>;
589	status = "okay";
590};
591
592/* off-board header */
593&i2c4 {
594	clock-frequency = <400000>;
595	pinctrl-names = "default";
596	pinctrl-0 = <&pinctrl_i2c4>;
597	status = "okay";
598};
599
600&pgc_gpumix {
601	status = "disabled";
602};
603
604/* off-board header */
605&sai3 {
606	pinctrl-names = "default";
607	pinctrl-0 = <&pinctrl_sai3>;
608	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
609	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
610	assigned-clock-rates = <24576000>;
611	status = "okay";
612};
613
614/* RS232/RS485/RS422 selectable */
615&uart1 {
616	pinctrl-names = "default";
617	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
618	status = "okay";
619};
620
621/* RS232 console */
622&uart2 {
623	pinctrl-names = "default";
624	pinctrl-0 = <&pinctrl_uart2>;
625	status = "okay";
626};
627
628/* bluetooth HCI */
629&uart3 {
630	pinctrl-names = "default";
631	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
632	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
633	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
634	uart-has-rtscts;
635	status = "okay";
636
637	bluetooth {
638		compatible = "brcm,bcm4330-bt";
639		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
640	};
641};
642
643/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
644&uart4 {
645	pinctrl-names = "default";
646	pinctrl-0 = <&pinctrl_uart4>;
647	status = "okay";
648};
649
650&usbotg1 {
651	dr_mode = "host";
652	vbus-supply = <&reg_usb1_vbus>;
653	disable-over-current;
654	status = "okay";
655};
656
657/* SDIO WiFi */
658&usdhc2 {
659	pinctrl-names = "default";
660	pinctrl-0 = <&pinctrl_usdhc2>;
661	bus-width = <4>;
662	non-removable;
663	vmmc-supply = <&reg_wifi>;
664	status = "okay";
665};
666
667/* eMMC */
668&usdhc3 {
669	pinctrl-names = "default", "state_100mhz", "state_200mhz";
670	pinctrl-0 = <&pinctrl_usdhc3>;
671	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
672	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
673	bus-width = <8>;
674	non-removable;
675	status = "okay";
676};
677
678&wdog1 {
679	pinctrl-names = "default";
680	pinctrl-0 = <&pinctrl_wdog>;
681	fsl,ext-reset-output;
682	status = "okay";
683};
684
685&iomuxc {
686	pinctrl-names = "default";
687	pinctrl-0 = <&pinctrl_hog>;
688
689	pinctrl_hog: hoggrp {
690		fsl,pins = <
691			MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
692			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */
693			MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
694			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
695			MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
696			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
697			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
698			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
699			MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
700			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
701			MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
702		>;
703	};
704
705	pinctrl_accel: accelgrp {
706		fsl,pins = <
707			MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
708		>;
709	};
710
711	pinctrl_fec1: fec1grp {
712		fsl,pins = <
713			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
714			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
715			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
716			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
717			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
718			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
719			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
720			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
721			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
722			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
723			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
724			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
725			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
726			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
727			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
728			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
729			MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN	0x141
730			MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT	0x141
731		>;
732	};
733
734	pinctrl_gsc: gscgrp {
735		fsl,pins = <
736			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
737		>;
738	};
739
740	pinctrl_i2c1: i2c1grp {
741		fsl,pins = <
742			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
743			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
744		>;
745	};
746
747	pinctrl_i2c2: i2c2grp {
748		fsl,pins = <
749			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
750			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
751		>;
752	};
753
754	pinctrl_i2c3: i2c3grp {
755		fsl,pins = <
756			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
757			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
758		>;
759	};
760
761	pinctrl_i2c4: i2c4grp {
762		fsl,pins = <
763			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
764			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
765		>;
766	};
767
768	pinctrl_gpio_leds: gpioledgrp {
769		fsl,pins = <
770			MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
771			MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
772			MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
773			MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
774			MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
775		>;
776	};
777
778	pinctrl_pmic: pmicgrp {
779		fsl,pins = <
780			MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
781		>;
782	};
783
784	pinctrl_pps: ppsgrp {
785		fsl,pins = <
786			MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
787		>;
788	};
789
790	pinctrl_reg_wl: regwlgrp {
791		fsl,pins = <
792			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
793		>;
794	};
795
796	pinctrl_reg_usb1: regusb1grp {
797		fsl,pins = <
798			MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
799		>;
800	};
801
802	pinctrl_sai3: sai3grp {
803		fsl,pins = <
804			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
805			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
806			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
807			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
808			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
809		>;
810	};
811
812	pinctrl_spi1: spi1grp {
813		fsl,pins = <
814			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
815			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
816			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
817			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
818			MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
819		>;
820	};
821
822	pinctrl_spi2: spi2grp {
823		fsl,pins = <
824			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
825			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
826			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
827			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
828		>;
829	};
830
831	pinctrl_uart1: uart1grp {
832		fsl,pins = <
833			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
834			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
835		>;
836	};
837
838	pinctrl_uart1_gpio: uart1gpiogrp {
839		fsl,pins = <
840			MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
841			MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
842			MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
843		>;
844	};
845
846	pinctrl_uart2: uart2grp {
847		fsl,pins = <
848			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
849			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
850		>;
851	};
852
853	pinctrl_uart3_gpio: uart3_gpiogrp {
854		fsl,pins = <
855			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
856		>;
857	};
858
859	pinctrl_uart3: uart3grp {
860		fsl,pins = <
861			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
862			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
863			MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
864			MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
865		>;
866	};
867
868	pinctrl_uart4: uart4grp {
869		fsl,pins = <
870			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
871			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
872			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
873		>;
874	};
875
876	pinctrl_usdhc2: usdhc2grp {
877		fsl,pins = <
878			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
879			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
880			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
881			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
882			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
883			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
884		>;
885	};
886
887	pinctrl_usdhc3: usdhc3grp {
888		fsl,pins = <
889			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
890			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
891			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
892			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
893			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
894			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
895			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
896			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
897			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
898			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
899			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
900		>;
901	};
902
903	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
904		fsl,pins = <
905			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
906			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
907			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
908			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
909			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
910			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
911			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
912			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
913			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
914			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
915			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
916		>;
917	};
918
919	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
920		fsl,pins = <
921			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
922			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
923			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
924			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
925			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
926			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
927			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
928			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
929			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
930			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
931			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
932		>;
933	};
934
935	pinctrl_wdog: wdoggrp {
936		fsl,pins = <
937			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
938		>;
939	};
940};
941