1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11 12#include "imx8mm.dtsi" 13 14/ { 15 model = "Gateworks Venice GW7901 i.MX8MM board"; 16 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; 17 18 aliases { 19 ethernet0 = &fec1; 20 ethernet1 = &lan1; 21 ethernet2 = &lan2; 22 ethernet3 = &lan3; 23 ethernet4 = &lan4; 24 usb0 = &usbotg1; 25 usb1 = &usbotg2; 26 }; 27 28 chosen { 29 stdout-path = &uart2; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0x80000000>; 35 }; 36 37 gpio-keys { 38 compatible = "gpio-keys"; 39 40 user-pb { 41 label = "user_pb"; 42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 43 linux,code = <BTN_0>; 44 }; 45 46 user-pb1x { 47 label = "user_pb1x"; 48 linux,code = <BTN_1>; 49 interrupt-parent = <&gsc>; 50 interrupts = <0>; 51 }; 52 53 key-erased { 54 label = "key_erased"; 55 linux,code = <BTN_2>; 56 interrupt-parent = <&gsc>; 57 interrupts = <1>; 58 }; 59 60 eeprom-wp { 61 label = "eeprom_wp"; 62 linux,code = <BTN_3>; 63 interrupt-parent = <&gsc>; 64 interrupts = <2>; 65 }; 66 67 tamper { 68 label = "tamper"; 69 linux,code = <BTN_4>; 70 interrupt-parent = <&gsc>; 71 interrupts = <5>; 72 }; 73 74 switch-hold { 75 label = "switch_hold"; 76 linux,code = <BTN_5>; 77 interrupt-parent = <&gsc>; 78 interrupts = <7>; 79 }; 80 }; 81 82 led-controller { 83 compatible = "gpio-leds"; 84 85 led-0 { 86 function = LED_FUNCTION_STATUS; 87 color = <LED_COLOR_ID_RED>; 88 label = "led01_red"; 89 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; 90 default-state = "off"; 91 }; 92 93 led-1 { 94 function = LED_FUNCTION_STATUS; 95 color = <LED_COLOR_ID_GREEN>; 96 label = "led01_grn"; 97 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; 98 default-state = "off"; 99 }; 100 101 led-2 { 102 function = LED_FUNCTION_STATUS; 103 color = <LED_COLOR_ID_RED>; 104 label = "led02_red"; 105 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; 106 default-state = "off"; 107 }; 108 109 led-3 { 110 function = LED_FUNCTION_STATUS; 111 color = <LED_COLOR_ID_GREEN>; 112 label = "led02_grn"; 113 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; 114 default-state = "off"; 115 }; 116 117 led-4 { 118 function = LED_FUNCTION_STATUS; 119 color = <LED_COLOR_ID_RED>; 120 label = "led03_red"; 121 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; 122 default-state = "off"; 123 }; 124 125 led-5 { 126 function = LED_FUNCTION_STATUS; 127 color = <LED_COLOR_ID_GREEN>; 128 label = "led03_grn"; 129 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; 130 default-state = "off"; 131 }; 132 133 led-6 { 134 function = LED_FUNCTION_STATUS; 135 color = <LED_COLOR_ID_RED>; 136 label = "led04_red"; 137 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; 138 default-state = "off"; 139 }; 140 141 led-7 { 142 function = LED_FUNCTION_STATUS; 143 color = <LED_COLOR_ID_GREEN>; 144 label = "led04_grn"; 145 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; 146 default-state = "off"; 147 }; 148 149 led-8 { 150 function = LED_FUNCTION_STATUS; 151 color = <LED_COLOR_ID_RED>; 152 label = "led05_red"; 153 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; 154 default-state = "off"; 155 }; 156 157 led-9 { 158 function = LED_FUNCTION_STATUS; 159 color = <LED_COLOR_ID_GREEN>; 160 label = "led05_grn"; 161 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; 162 default-state = "off"; 163 }; 164 165 led-a { 166 function = LED_FUNCTION_STATUS; 167 color = <LED_COLOR_ID_RED>; 168 label = "led06_red"; 169 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; 170 default-state = "off"; 171 }; 172 173 led-b { 174 function = LED_FUNCTION_STATUS; 175 color = <LED_COLOR_ID_GREEN>; 176 label = "led06_grn"; 177 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; 178 default-state = "off"; 179 }; 180 }; 181 182 reg_3p3v: regulator-3p3v { 183 compatible = "regulator-fixed"; 184 regulator-name = "3P3V"; 185 regulator-min-microvolt = <3300000>; 186 regulator-max-microvolt = <3300000>; 187 }; 188 189 regulator-ioexp { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_reg_ioexp>; 192 compatible = "regulator-fixed"; 193 regulator-name = "ioexp"; 194 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 195 enable-active-high; 196 startup-delay-us = <100>; 197 regulator-min-microvolt = <3300000>; 198 regulator-max-microvolt = <3300000>; 199 regulator-always-on; 200 }; 201 202 regulator-isouart { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_reg_isouart>; 205 compatible = "regulator-fixed"; 206 regulator-name = "iso_uart"; 207 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; 208 startup-delay-us = <100>; 209 regulator-min-microvolt = <3300000>; 210 regulator-max-microvolt = <3300000>; 211 regulator-always-on; 212 }; 213 214 reg_usb2_vbus: regulator-usb2 { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_reg_usb2>; 217 compatible = "regulator-fixed"; 218 regulator-name = "usb_usb2_vbus"; 219 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 220 enable-active-high; 221 regulator-min-microvolt = <5000000>; 222 regulator-max-microvolt = <5000000>; 223 }; 224 225 reg_wifi: regulator-wifi { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_reg_wl>; 228 compatible = "regulator-fixed"; 229 regulator-name = "wifi"; 230 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 231 enable-active-high; 232 startup-delay-us = <100>; 233 regulator-min-microvolt = <3300000>; 234 regulator-max-microvolt = <3300000>; 235 }; 236}; 237 238&ddrc { 239 operating-points-v2 = <&ddrc_opp_table>; 240 241 ddrc_opp_table: opp-table { 242 compatible = "operating-points-v2"; 243 244 opp-25M { 245 opp-hz = /bits/ 64 <25000000>; 246 }; 247 248 opp-100M { 249 opp-hz = /bits/ 64 <100000000>; 250 }; 251 252 opp-750M { 253 opp-hz = /bits/ 64 <750000000>; 254 }; 255 }; 256}; 257 258&disp_blk_ctrl { 259 status = "disabled"; 260}; 261 262&ecspi1 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_spi1>; 265 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 266 status = "okay"; 267 268 flash@0 { 269 compatible = "jedec,spi-nor"; 270 reg = <0>; 271 spi-max-frequency = <40000000>; 272 status = "okay"; 273 }; 274}; 275 276&fec1 { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_fec1>; 279 phy-mode = "rgmii-id"; 280 local-mac-address = [00 00 00 00 00 00]; 281 status = "okay"; 282 283 fixed-link { 284 speed = <1000>; 285 full-duplex; 286 }; 287}; 288 289&gpu_2d { 290 status = "disabled"; 291}; 292 293&gpu_3d { 294 status = "disabled"; 295}; 296 297&i2c1 { 298 clock-frequency = <100000>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_i2c1>; 301 status = "okay"; 302 303 gsc: gsc@20 { 304 compatible = "gw,gsc"; 305 reg = <0x20>; 306 pinctrl-0 = <&pinctrl_gsc>; 307 interrupt-parent = <&gpio4>; 308 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 309 interrupt-controller; 310 #interrupt-cells = <1>; 311 312 adc { 313 compatible = "gw,gsc-adc"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 channel@6 { 318 gw,mode = <0>; 319 reg = <0x06>; 320 label = "temp"; 321 }; 322 323 channel@8 { 324 gw,mode = <1>; 325 reg = <0x08>; 326 label = "vdd_bat"; 327 }; 328 329 channel@82 { 330 gw,mode = <2>; 331 reg = <0x82>; 332 label = "vin_aux1"; 333 gw,voltage-divider-ohms = <22100 1000>; 334 }; 335 336 channel@84 { 337 gw,mode = <2>; 338 reg = <0x84>; 339 label = "vin_aux2"; 340 gw,voltage-divider-ohms = <22100 1000>; 341 }; 342 343 channel@86 { 344 gw,mode = <2>; 345 reg = <0x86>; 346 label = "vdd_vin"; 347 gw,voltage-divider-ohms = <22100 1000>; 348 }; 349 350 channel@88 { 351 gw,mode = <2>; 352 reg = <0x88>; 353 label = "vdd_3p3"; 354 gw,voltage-divider-ohms = <10000 10000>; 355 }; 356 357 channel@8c { 358 gw,mode = <2>; 359 reg = <0x8c>; 360 label = "vdd_2p5"; 361 gw,voltage-divider-ohms = <10000 10000>; 362 }; 363 364 channel@8e { 365 gw,mode = <2>; 366 reg = <0x8e>; 367 label = "vdd_0p95"; 368 }; 369 370 channel@90 { 371 gw,mode = <2>; 372 reg = <0x90>; 373 label = "vdd_soc"; 374 }; 375 376 channel@92 { 377 gw,mode = <2>; 378 reg = <0x92>; 379 label = "vdd_arm"; 380 }; 381 382 channel@98 { 383 gw,mode = <2>; 384 reg = <0x98>; 385 label = "vdd_1p8"; 386 }; 387 388 channel@9a { 389 gw,mode = <2>; 390 reg = <0x9a>; 391 label = "vdd_1p2"; 392 }; 393 394 channel@9c { 395 gw,mode = <2>; 396 reg = <0x9c>; 397 label = "vdd_dram"; 398 }; 399 400 channel@a2 { 401 gw,mode = <2>; 402 reg = <0xa2>; 403 label = "vdd_gsc"; 404 gw,voltage-divider-ohms = <10000 10000>; 405 }; 406 }; 407 }; 408 409 gpio: gpio@23 { 410 compatible = "nxp,pca9555"; 411 reg = <0x23>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 interrupt-parent = <&gsc>; 415 interrupts = <4>; 416 }; 417 418 eeprom@50 { 419 compatible = "atmel,24c02"; 420 reg = <0x50>; 421 pagesize = <16>; 422 }; 423 424 eeprom@51 { 425 compatible = "atmel,24c02"; 426 reg = <0x51>; 427 pagesize = <16>; 428 }; 429 430 eeprom@52 { 431 compatible = "atmel,24c02"; 432 reg = <0x52>; 433 pagesize = <16>; 434 }; 435 436 eeprom@53 { 437 compatible = "atmel,24c02"; 438 reg = <0x53>; 439 pagesize = <16>; 440 }; 441 442 rtc@68 { 443 compatible = "dallas,ds1672"; 444 reg = <0x68>; 445 }; 446}; 447 448&i2c2 { 449 clock-frequency = <400000>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_i2c2>; 452 status = "okay"; 453 454 pmic@4b { 455 compatible = "rohm,bd71847"; 456 reg = <0x4b>; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_pmic>; 459 interrupt-parent = <&gpio3>; 460 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 461 rohm,reset-snvs-powered; 462 #clock-cells = <0>; 463 clocks = <&osc_32k 0>; 464 clock-output-names = "clk-32k-out"; 465 466 regulators { 467 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 468 BUCK1 { 469 regulator-name = "buck1"; 470 regulator-min-microvolt = <700000>; 471 regulator-max-microvolt = <1300000>; 472 regulator-boot-on; 473 regulator-always-on; 474 regulator-ramp-delay = <1250>; 475 }; 476 477 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 478 BUCK2 { 479 regulator-name = "buck2"; 480 regulator-min-microvolt = <700000>; 481 regulator-max-microvolt = <1300000>; 482 regulator-boot-on; 483 regulator-always-on; 484 regulator-ramp-delay = <1250>; 485 rohm,dvs-run-voltage = <1000000>; 486 rohm,dvs-idle-voltage = <900000>; 487 }; 488 489 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 490 BUCK3 { 491 regulator-name = "buck3"; 492 regulator-min-microvolt = <700000>; 493 regulator-max-microvolt = <1350000>; 494 regulator-boot-on; 495 regulator-always-on; 496 }; 497 498 /* vdd_3p3 */ 499 BUCK4 { 500 regulator-name = "buck4"; 501 regulator-min-microvolt = <3000000>; 502 regulator-max-microvolt = <3300000>; 503 regulator-boot-on; 504 regulator-always-on; 505 }; 506 507 /* vdd_1p8 */ 508 BUCK5 { 509 regulator-name = "buck5"; 510 regulator-min-microvolt = <1605000>; 511 regulator-max-microvolt = <1995000>; 512 regulator-boot-on; 513 regulator-always-on; 514 }; 515 516 /* vdd_dram */ 517 BUCK6 { 518 regulator-name = "buck6"; 519 regulator-min-microvolt = <800000>; 520 regulator-max-microvolt = <1400000>; 521 regulator-boot-on; 522 regulator-always-on; 523 }; 524 525 /* nvcc_snvs_1p8 */ 526 LDO1 { 527 regulator-name = "ldo1"; 528 regulator-min-microvolt = <1600000>; 529 regulator-max-microvolt = <1900000>; 530 regulator-boot-on; 531 regulator-always-on; 532 }; 533 534 /* vdd_snvs_0p8 */ 535 LDO2 { 536 regulator-name = "ldo2"; 537 regulator-min-microvolt = <800000>; 538 regulator-max-microvolt = <900000>; 539 regulator-boot-on; 540 regulator-always-on; 541 }; 542 543 /* vdda_1p8 */ 544 LDO3 { 545 regulator-name = "ldo3"; 546 regulator-min-microvolt = <1800000>; 547 regulator-max-microvolt = <3300000>; 548 regulator-boot-on; 549 regulator-always-on; 550 }; 551 552 LDO4 { 553 regulator-name = "ldo4"; 554 regulator-min-microvolt = <900000>; 555 regulator-max-microvolt = <1800000>; 556 regulator-boot-on; 557 regulator-always-on; 558 }; 559 560 LDO6 { 561 regulator-name = "ldo6"; 562 regulator-min-microvolt = <900000>; 563 regulator-max-microvolt = <1800000>; 564 regulator-boot-on; 565 regulator-always-on; 566 }; 567 }; 568 }; 569}; 570 571&i2c3 { 572 clock-frequency = <400000>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&pinctrl_i2c3>; 575 status = "okay"; 576 577 leds_gpio: gpio@20 { 578 compatible = "nxp,pca9555"; 579 reg = <0x20>; 580 gpio-controller; 581 #gpio-cells = <2>; 582 }; 583 584 switch: switch@5f { 585 compatible = "microchip,ksz9897"; 586 reg = <0x5f>; 587 pinctrl-0 = <&pinctrl_ksz>; 588 interrupt-parent = <&gpio4>; 589 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 590 phy-mode = "rgmii-id"; 591 592 ports { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 596 lan1: port@0 { 597 reg = <0>; 598 label = "lan1"; 599 local-mac-address = [00 00 00 00 00 00]; 600 }; 601 602 lan2: port@1 { 603 reg = <1>; 604 label = "lan2"; 605 local-mac-address = [00 00 00 00 00 00]; 606 }; 607 608 lan3: port@2 { 609 reg = <2>; 610 label = "lan3"; 611 local-mac-address = [00 00 00 00 00 00]; 612 }; 613 614 lan4: port@3 { 615 reg = <3>; 616 label = "lan4"; 617 local-mac-address = [00 00 00 00 00 00]; 618 }; 619 620 port@5 { 621 reg = <5>; 622 label = "cpu"; 623 ethernet = <&fec1>; 624 phy-mode = "rgmii-id"; 625 626 fixed-link { 627 speed = <1000>; 628 full-duplex; 629 }; 630 }; 631 }; 632 }; 633 634 crypto@60 { 635 compatible = "atmel,atecc508a"; 636 reg = <0x60>; 637 }; 638}; 639 640&i2c4 { 641 clock-frequency = <400000>; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&pinctrl_i2c4>; 644 status = "okay"; 645}; 646 647&pgc_gpu { 648 status = "disabled"; 649}; 650 651&pgc_gpumix { 652 status = "disabled"; 653}; 654 655&pgc_mipi { 656 status = "disabled"; 657}; 658 659&uart1 { 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 662 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 663 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 664 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 665 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 666 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 667 status = "okay"; 668}; 669 670/* console */ 671&uart2 { 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_uart2>; 674 status = "okay"; 675}; 676 677&uart3 { 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 680 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 681 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 682 status = "okay"; 683}; 684 685&uart4 { 686 pinctrl-names = "default"; 687 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; 688 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 689 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 690 status = "okay"; 691}; 692 693&usbotg1 { 694 dr_mode = "host"; 695 disable-over-current; 696 status = "okay"; 697}; 698 699&usbotg2 { 700 dr_mode = "host"; 701 vbus-supply = <®_usb2_vbus>; 702 status = "okay"; 703}; 704 705/* SDIO WiFi */ 706&usdhc1 { 707 pinctrl-names = "default"; 708 pinctrl-0 = <&pinctrl_usdhc1>; 709 bus-width = <4>; 710 non-removable; 711 vmmc-supply = <®_wifi>; 712 status = "okay"; 713}; 714 715/* microSD */ 716&usdhc2 { 717 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 718 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 719 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 720 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 721 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 722 bus-width = <4>; 723 vmmc-supply = <®_3p3v>; 724 status = "okay"; 725}; 726 727/* eMMC */ 728&usdhc3 { 729 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 730 pinctrl-0 = <&pinctrl_usdhc3>; 731 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 732 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 733 bus-width = <8>; 734 non-removable; 735 status = "okay"; 736}; 737 738&wdog1 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_wdog>; 741 fsl,ext-reset-output; 742 status = "okay"; 743}; 744 745&iomuxc { 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_hog>; 748 749 pinctrl_hog: hoggrp { 750 fsl,pins = < 751 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ 752 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ 753 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ 754 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ 755 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ 756 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ 757 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ 758 >; 759 }; 760 761 pinctrl_fec1: fec1grp { 762 fsl,pins = < 763 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 764 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 765 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 766 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 767 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 768 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 769 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 770 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 771 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 772 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 773 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 774 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 775 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 776 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 777 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ 778 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ 779 >; 780 }; 781 782 pinctrl_gsc: gscgrp { 783 fsl,pins = < 784 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 785 >; 786 }; 787 788 pinctrl_i2c1: i2c1grp { 789 fsl,pins = < 790 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 791 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 792 >; 793 }; 794 795 pinctrl_i2c2: i2c2grp { 796 fsl,pins = < 797 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 798 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 799 >; 800 }; 801 802 pinctrl_i2c3: i2c3grp { 803 fsl,pins = < 804 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 805 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 806 >; 807 }; 808 809 pinctrl_i2c4: i2c4grp { 810 fsl,pins = < 811 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 812 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 813 >; 814 }; 815 816 pinctrl_ksz: kszgrp { 817 fsl,pins = < 818 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 819 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ 820 >; 821 }; 822 823 pinctrl_pmic: pmicgrp { 824 fsl,pins = < 825 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 826 >; 827 }; 828 829 pinctrl_reg_isouart: regisouartgrp { 830 fsl,pins = < 831 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 832 >; 833 }; 834 835 pinctrl_reg_ioexp: regioexpgrp { 836 fsl,pins = < 837 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 838 >; 839 }; 840 841 pinctrl_reg_wl: regwlgrp { 842 fsl,pins = < 843 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 844 >; 845 }; 846 847 pinctrl_reg_usb2: regusb1grp { 848 fsl,pins = < 849 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 850 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 851 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 852 >; 853 }; 854 855 pinctrl_spi1: spi1grp { 856 fsl,pins = < 857 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 858 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 859 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 860 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 861 >; 862 }; 863 864 pinctrl_uart1: uart1grp { 865 fsl,pins = < 866 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 867 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 868 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 869 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 870 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 871 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 872 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 873 >; 874 }; 875 876 pinctrl_uart1_gpio: uart1gpiogrp { 877 fsl,pins = < 878 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ 879 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ 880 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ 881 >; 882 }; 883 884 pinctrl_uart2: uart2grp { 885 fsl,pins = < 886 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 887 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 888 >; 889 }; 890 891 pinctrl_uart3: uart3grp { 892 fsl,pins = < 893 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 894 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 895 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 896 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 897 >; 898 }; 899 900 pinctrl_uart3_gpio: uart3gpiogrp { 901 fsl,pins = < 902 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ 903 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ 904 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ 905 >; 906 }; 907 908 pinctrl_uart4: uart4grp { 909 fsl,pins = < 910 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 911 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 912 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 913 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 914 >; 915 }; 916 917 pinctrl_uart4_gpio: uart4gpiogrp { 918 fsl,pins = < 919 920 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ 921 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ 922 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ 923 >; 924 }; 925 926 pinctrl_usdhc1: usdhc1grp { 927 fsl,pins = < 928 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 929 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 930 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 931 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 932 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 933 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 934 >; 935 }; 936 937 pinctrl_usdhc2: usdhc2grp { 938 fsl,pins = < 939 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 940 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 941 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 942 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 943 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 944 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 945 >; 946 }; 947 948 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 949 fsl,pins = < 950 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 951 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 952 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 953 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 954 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 955 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 956 >; 957 }; 958 959 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 960 fsl,pins = < 961 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 962 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 963 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 964 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 965 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 966 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 967 >; 968 }; 969 970 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 971 fsl,pins = < 972 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 973 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 974 >; 975 }; 976 977 pinctrl_usdhc3: usdhc3grp { 978 fsl,pins = < 979 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 980 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 981 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 982 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 983 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 984 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 985 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 986 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 987 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 988 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 989 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 990 >; 991 }; 992 993 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 994 fsl,pins = < 995 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 996 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 997 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 998 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 999 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 1000 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 1001 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 1002 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 1003 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 1004 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 1005 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 1006 >; 1007 }; 1008 1009 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1010 fsl,pins = < 1011 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 1012 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1013 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 1014 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 1015 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 1016 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1017 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1018 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1019 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1020 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1021 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1022 >; 1023 }; 1024 1025 pinctrl_wdog: wdoggrp { 1026 fsl,pins = < 1027 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1028 >; 1029 }; 1030}; 1031 1032&cpu_alert0 { 1033 temperature = <95000>; 1034 hysteresis = <2000>; 1035 type = "passive"; 1036}; 1037 1038&cpu_crit0 { 1039 temperature = <105000>; 1040 hysteresis = <2000>; 1041 type = "critical"; 1042}; 1043