1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11 12#include "imx8mm.dtsi" 13 14/ { 15 model = "Gateworks Venice GW7901 i.MX8MM board"; 16 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; 17 18 aliases { 19 ethernet0 = &fec1; 20 ethernet1 = &lan1; 21 ethernet2 = &lan2; 22 ethernet3 = &lan3; 23 ethernet4 = &lan4; 24 usb0 = &usbotg1; 25 usb1 = &usbotg2; 26 }; 27 28 chosen { 29 stdout-path = &uart2; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0x80000000>; 35 }; 36 37 gpio-keys { 38 compatible = "gpio-keys"; 39 40 user-pb { 41 label = "user_pb"; 42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 43 linux,code = <BTN_0>; 44 }; 45 46 user-pb1x { 47 label = "user_pb1x"; 48 linux,code = <BTN_1>; 49 interrupt-parent = <&gsc>; 50 interrupts = <0>; 51 }; 52 53 key-erased { 54 label = "key_erased"; 55 linux,code = <BTN_2>; 56 interrupt-parent = <&gsc>; 57 interrupts = <1>; 58 }; 59 60 eeprom-wp { 61 label = "eeprom_wp"; 62 linux,code = <BTN_3>; 63 interrupt-parent = <&gsc>; 64 interrupts = <2>; 65 }; 66 67 tamper { 68 label = "tamper"; 69 linux,code = <BTN_4>; 70 interrupt-parent = <&gsc>; 71 interrupts = <5>; 72 }; 73 74 switch-hold { 75 label = "switch_hold"; 76 linux,code = <BTN_5>; 77 interrupt-parent = <&gsc>; 78 interrupts = <7>; 79 }; 80 }; 81 82 led-controller { 83 compatible = "gpio-leds"; 84 85 led-0 { 86 function = LED_FUNCTION_STATUS; 87 color = <LED_COLOR_ID_RED>; 88 label = "led01_red"; 89 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; 90 default-state = "off"; 91 }; 92 93 led-1 { 94 function = LED_FUNCTION_STATUS; 95 color = <LED_COLOR_ID_GREEN>; 96 label = "led01_grn"; 97 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; 98 default-state = "off"; 99 }; 100 101 led-2 { 102 function = LED_FUNCTION_STATUS; 103 color = <LED_COLOR_ID_RED>; 104 label = "led02_red"; 105 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; 106 default-state = "off"; 107 }; 108 109 led-3 { 110 function = LED_FUNCTION_STATUS; 111 color = <LED_COLOR_ID_GREEN>; 112 label = "led02_grn"; 113 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; 114 default-state = "off"; 115 }; 116 117 led-4 { 118 function = LED_FUNCTION_STATUS; 119 color = <LED_COLOR_ID_RED>; 120 label = "led03_red"; 121 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; 122 default-state = "off"; 123 }; 124 125 led-5 { 126 function = LED_FUNCTION_STATUS; 127 color = <LED_COLOR_ID_GREEN>; 128 label = "led03_grn"; 129 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; 130 default-state = "off"; 131 }; 132 133 led-6 { 134 function = LED_FUNCTION_STATUS; 135 color = <LED_COLOR_ID_RED>; 136 label = "led04_red"; 137 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; 138 default-state = "off"; 139 }; 140 141 led-7 { 142 function = LED_FUNCTION_STATUS; 143 color = <LED_COLOR_ID_GREEN>; 144 label = "led04_grn"; 145 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; 146 default-state = "off"; 147 }; 148 149 led-8 { 150 function = LED_FUNCTION_STATUS; 151 color = <LED_COLOR_ID_RED>; 152 label = "led05_red"; 153 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; 154 default-state = "off"; 155 }; 156 157 led-9 { 158 function = LED_FUNCTION_STATUS; 159 color = <LED_COLOR_ID_GREEN>; 160 label = "led05_grn"; 161 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; 162 default-state = "off"; 163 }; 164 165 led-a { 166 function = LED_FUNCTION_STATUS; 167 color = <LED_COLOR_ID_RED>; 168 label = "led06_red"; 169 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; 170 default-state = "off"; 171 }; 172 173 led-b { 174 function = LED_FUNCTION_STATUS; 175 color = <LED_COLOR_ID_GREEN>; 176 label = "led06_grn"; 177 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; 178 default-state = "off"; 179 }; 180 }; 181 182 reg_3p3v: regulator-3p3v { 183 compatible = "regulator-fixed"; 184 regulator-name = "3P3V"; 185 regulator-min-microvolt = <3300000>; 186 regulator-max-microvolt = <3300000>; 187 }; 188 189 regulator-ioexp { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_reg_ioexp>; 192 compatible = "regulator-fixed"; 193 regulator-name = "ioexp"; 194 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 195 enable-active-high; 196 startup-delay-us = <100>; 197 regulator-min-microvolt = <3300000>; 198 regulator-max-microvolt = <3300000>; 199 regulator-always-on; 200 }; 201 202 regulator-isouart { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_reg_isouart>; 205 compatible = "regulator-fixed"; 206 regulator-name = "iso_uart"; 207 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; 208 startup-delay-us = <100>; 209 regulator-min-microvolt = <3300000>; 210 regulator-max-microvolt = <3300000>; 211 regulator-always-on; 212 }; 213 214 reg_usb2_vbus: regulator-usb2 { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_reg_usb2>; 217 compatible = "regulator-fixed"; 218 regulator-name = "usb_usb2_vbus"; 219 gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; 220 enable-active-high; 221 regulator-min-microvolt = <5000000>; 222 regulator-max-microvolt = <5000000>; 223 }; 224 225 reg_wifi: regulator-wifi { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_reg_wl>; 228 compatible = "regulator-fixed"; 229 regulator-name = "wifi"; 230 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 231 enable-active-high; 232 startup-delay-us = <100>; 233 regulator-min-microvolt = <3300000>; 234 regulator-max-microvolt = <3300000>; 235 }; 236}; 237 238&ddrc { 239 operating-points-v2 = <&ddrc_opp_table>; 240 241 ddrc_opp_table: opp-table { 242 compatible = "operating-points-v2"; 243 244 opp-25M { 245 opp-hz = /bits/ 64 <25000000>; 246 }; 247 248 opp-100M { 249 opp-hz = /bits/ 64 <100000000>; 250 }; 251 252 opp-750M { 253 opp-hz = /bits/ 64 <750000000>; 254 }; 255 }; 256}; 257 258&ecspi1 { 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_spi1>; 261 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 262 status = "okay"; 263 264 flash@0 { 265 compatible = "jedec,spi-nor"; 266 reg = <0>; 267 spi-max-frequency = <40000000>; 268 status = "okay"; 269 }; 270}; 271 272&fec1 { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_fec1>; 275 phy-mode = "rgmii-id"; 276 local-mac-address = [00 00 00 00 00 00]; 277 status = "okay"; 278 279 fixed-link { 280 speed = <1000>; 281 full-duplex; 282 }; 283}; 284 285&i2c1 { 286 clock-frequency = <100000>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_i2c1>; 289 status = "okay"; 290 291 gsc: gsc@20 { 292 compatible = "gw,gsc"; 293 reg = <0x20>; 294 pinctrl-0 = <&pinctrl_gsc>; 295 interrupt-parent = <&gpio4>; 296 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 297 interrupt-controller; 298 #interrupt-cells = <1>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 302 adc { 303 compatible = "gw,gsc-adc"; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 channel@6 { 308 gw,mode = <0>; 309 reg = <0x06>; 310 label = "temp"; 311 }; 312 313 channel@8 { 314 gw,mode = <1>; 315 reg = <0x08>; 316 label = "vdd_bat"; 317 }; 318 319 channel@82 { 320 gw,mode = <2>; 321 reg = <0x82>; 322 label = "vin_aux1"; 323 gw,voltage-divider-ohms = <22100 1000>; 324 }; 325 326 channel@84 { 327 gw,mode = <2>; 328 reg = <0x84>; 329 label = "vin_aux2"; 330 gw,voltage-divider-ohms = <22100 1000>; 331 }; 332 333 channel@86 { 334 gw,mode = <2>; 335 reg = <0x86>; 336 label = "vdd_vin"; 337 gw,voltage-divider-ohms = <22100 1000>; 338 }; 339 340 channel@88 { 341 gw,mode = <2>; 342 reg = <0x88>; 343 label = "vdd_3p3"; 344 gw,voltage-divider-ohms = <10000 10000>; 345 }; 346 347 channel@8c { 348 gw,mode = <2>; 349 reg = <0x8c>; 350 label = "vdd_2p5"; 351 gw,voltage-divider-ohms = <10000 10000>; 352 }; 353 354 channel@8e { 355 gw,mode = <2>; 356 reg = <0x8e>; 357 label = "vdd_0p95"; 358 }; 359 360 channel@90 { 361 gw,mode = <2>; 362 reg = <0x90>; 363 label = "vdd_soc"; 364 }; 365 366 channel@92 { 367 gw,mode = <2>; 368 reg = <0x92>; 369 label = "vdd_arm"; 370 }; 371 372 channel@98 { 373 gw,mode = <2>; 374 reg = <0x98>; 375 label = "vdd_1p8"; 376 }; 377 378 channel@9a { 379 gw,mode = <2>; 380 reg = <0x9a>; 381 label = "vdd_1p2"; 382 }; 383 384 channel@9c { 385 gw,mode = <2>; 386 reg = <0x9c>; 387 label = "vdd_dram"; 388 }; 389 390 channel@a2 { 391 gw,mode = <2>; 392 reg = <0xa2>; 393 label = "vdd_gsc"; 394 gw,voltage-divider-ohms = <10000 10000>; 395 }; 396 }; 397 }; 398 399 gpio: gpio@23 { 400 compatible = "nxp,pca9555"; 401 reg = <0x23>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-parent = <&gsc>; 405 interrupts = <4>; 406 }; 407 408 eeprom@50 { 409 compatible = "atmel,24c02"; 410 reg = <0x50>; 411 pagesize = <16>; 412 }; 413 414 eeprom@51 { 415 compatible = "atmel,24c02"; 416 reg = <0x51>; 417 pagesize = <16>; 418 }; 419 420 eeprom@52 { 421 compatible = "atmel,24c02"; 422 reg = <0x52>; 423 pagesize = <16>; 424 }; 425 426 eeprom@53 { 427 compatible = "atmel,24c02"; 428 reg = <0x53>; 429 pagesize = <16>; 430 }; 431 432 rtc@68 { 433 compatible = "dallas,ds1672"; 434 reg = <0x68>; 435 }; 436}; 437 438&i2c2 { 439 clock-frequency = <400000>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pinctrl_i2c2>; 442 status = "okay"; 443 444 pmic@4b { 445 compatible = "rohm,bd71847"; 446 reg = <0x4b>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&pinctrl_pmic>; 449 interrupt-parent = <&gpio3>; 450 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 451 rohm,reset-snvs-powered; 452 #clock-cells = <0>; 453 clocks = <&osc_32k 0>; 454 clock-output-names = "clk-32k-out"; 455 456 regulators { 457 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 458 BUCK1 { 459 regulator-name = "buck1"; 460 regulator-min-microvolt = <700000>; 461 regulator-max-microvolt = <1300000>; 462 regulator-boot-on; 463 regulator-always-on; 464 regulator-ramp-delay = <1250>; 465 }; 466 467 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 468 BUCK2 { 469 regulator-name = "buck2"; 470 regulator-min-microvolt = <700000>; 471 regulator-max-microvolt = <1300000>; 472 regulator-boot-on; 473 regulator-always-on; 474 regulator-ramp-delay = <1250>; 475 rohm,dvs-run-voltage = <1000000>; 476 rohm,dvs-idle-voltage = <900000>; 477 }; 478 479 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 480 BUCK3 { 481 regulator-name = "buck3"; 482 regulator-min-microvolt = <700000>; 483 regulator-max-microvolt = <1350000>; 484 regulator-boot-on; 485 regulator-always-on; 486 }; 487 488 /* vdd_3p3 */ 489 BUCK4 { 490 regulator-name = "buck4"; 491 regulator-min-microvolt = <3000000>; 492 regulator-max-microvolt = <3300000>; 493 regulator-boot-on; 494 regulator-always-on; 495 }; 496 497 /* vdd_1p8 */ 498 BUCK5 { 499 regulator-name = "buck5"; 500 regulator-min-microvolt = <1605000>; 501 regulator-max-microvolt = <1995000>; 502 regulator-boot-on; 503 regulator-always-on; 504 }; 505 506 /* vdd_dram */ 507 BUCK6 { 508 regulator-name = "buck6"; 509 regulator-min-microvolt = <800000>; 510 regulator-max-microvolt = <1400000>; 511 regulator-boot-on; 512 regulator-always-on; 513 }; 514 515 /* nvcc_snvs_1p8 */ 516 LDO1 { 517 regulator-name = "ldo1"; 518 regulator-min-microvolt = <1600000>; 519 regulator-max-microvolt = <1900000>; 520 regulator-boot-on; 521 regulator-always-on; 522 }; 523 524 /* vdd_snvs_0p8 */ 525 LDO2 { 526 regulator-name = "ldo2"; 527 regulator-min-microvolt = <800000>; 528 regulator-max-microvolt = <900000>; 529 regulator-boot-on; 530 regulator-always-on; 531 }; 532 533 /* vdda_1p8 */ 534 LDO3 { 535 regulator-name = "ldo3"; 536 regulator-min-microvolt = <1800000>; 537 regulator-max-microvolt = <3300000>; 538 regulator-boot-on; 539 regulator-always-on; 540 }; 541 542 LDO4 { 543 regulator-name = "ldo4"; 544 regulator-min-microvolt = <900000>; 545 regulator-max-microvolt = <1800000>; 546 regulator-boot-on; 547 regulator-always-on; 548 }; 549 550 LDO6 { 551 regulator-name = "ldo6"; 552 regulator-min-microvolt = <900000>; 553 regulator-max-microvolt = <1800000>; 554 regulator-boot-on; 555 regulator-always-on; 556 }; 557 }; 558 }; 559}; 560 561&i2c3 { 562 clock-frequency = <400000>; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&pinctrl_i2c3>; 565 status = "okay"; 566 567 leds_gpio: gpio@20 { 568 compatible = "nxp,pca9555"; 569 reg = <0x20>; 570 gpio-controller; 571 #gpio-cells = <2>; 572 }; 573 574 switch: switch@5f { 575 compatible = "microchip,ksz9897"; 576 reg = <0x5f>; 577 pinctrl-0 = <&pinctrl_ksz>; 578 interrupt-parent = <&gpio4>; 579 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 580 phy-mode = "rgmii-id"; 581 582 ports { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 586 lan1: port@0 { 587 reg = <0>; 588 label = "lan1"; 589 local-mac-address = [00 00 00 00 00 00]; 590 }; 591 592 lan2: port@1 { 593 reg = <1>; 594 label = "lan2"; 595 local-mac-address = [00 00 00 00 00 00]; 596 }; 597 598 lan3: port@2 { 599 reg = <2>; 600 label = "lan3"; 601 local-mac-address = [00 00 00 00 00 00]; 602 }; 603 604 lan4: port@3 { 605 reg = <3>; 606 label = "lan4"; 607 local-mac-address = [00 00 00 00 00 00]; 608 }; 609 610 port@5 { 611 reg = <5>; 612 label = "cpu"; 613 ethernet = <&fec1>; 614 phy-mode = "rgmii-id"; 615 616 fixed-link { 617 speed = <1000>; 618 full-duplex; 619 }; 620 }; 621 }; 622 }; 623 624 crypto@60 { 625 compatible = "atmel,atecc508a"; 626 reg = <0x60>; 627 }; 628}; 629 630&i2c4 { 631 clock-frequency = <400000>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_i2c4>; 634 status = "okay"; 635}; 636 637&uart1 { 638 pinctrl-names = "default"; 639 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 640 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 641 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 642 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 643 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 644 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 645 status = "okay"; 646}; 647 648/* console */ 649&uart2 { 650 pinctrl-names = "default"; 651 pinctrl-0 = <&pinctrl_uart2>; 652 status = "okay"; 653}; 654 655&uart3 { 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 658 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 659 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 660 status = "okay"; 661}; 662 663&uart4 { 664 pinctrl-names = "default"; 665 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; 666 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 667 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 668 status = "okay"; 669}; 670 671&usbotg1 { 672 dr_mode = "host"; 673 disable-over-current; 674 status = "okay"; 675}; 676 677&usbotg2 { 678 dr_mode = "host"; 679 vbus-supply = <®_usb2_vbus>; 680 status = "okay"; 681}; 682 683/* SDIO WiFi */ 684&usdhc1 { 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_usdhc1>; 687 bus-width = <4>; 688 non-removable; 689 vmmc-supply = <®_wifi>; 690 status = "okay"; 691}; 692 693/* microSD */ 694&usdhc2 { 695 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 696 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 697 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 698 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 699 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 700 bus-width = <4>; 701 vmmc-supply = <®_3p3v>; 702 status = "okay"; 703}; 704 705/* eMMC */ 706&usdhc3 { 707 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 708 pinctrl-0 = <&pinctrl_usdhc3>; 709 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 710 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 711 bus-width = <8>; 712 non-removable; 713 status = "okay"; 714}; 715 716&wdog1 { 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pinctrl_wdog>; 719 fsl,ext-reset-output; 720 status = "okay"; 721}; 722 723&iomuxc { 724 pinctrl-names = "default"; 725 pinctrl-0 = <&pinctrl_hog>; 726 727 pinctrl_hog: hoggrp { 728 fsl,pins = < 729 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ 730 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ 731 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ 732 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ 733 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ 734 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ 735 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ 736 >; 737 }; 738 739 pinctrl_fec1: fec1grp { 740 fsl,pins = < 741 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 742 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 743 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 744 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 745 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 746 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 747 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 748 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 749 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 750 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 751 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 752 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 753 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 754 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 755 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ 756 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ 757 >; 758 }; 759 760 pinctrl_gsc: gscgrp { 761 fsl,pins = < 762 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 763 >; 764 }; 765 766 pinctrl_i2c1: i2c1grp { 767 fsl,pins = < 768 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 769 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 770 >; 771 }; 772 773 pinctrl_i2c2: i2c2grp { 774 fsl,pins = < 775 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 776 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 777 >; 778 }; 779 780 pinctrl_i2c3: i2c3grp { 781 fsl,pins = < 782 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 783 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 784 >; 785 }; 786 787 pinctrl_i2c4: i2c4grp { 788 fsl,pins = < 789 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 790 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 791 >; 792 }; 793 794 pinctrl_ksz: kszgrp { 795 fsl,pins = < 796 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 797 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ 798 >; 799 }; 800 801 pinctrl_pmic: pmicgrp { 802 fsl,pins = < 803 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 804 >; 805 }; 806 807 pinctrl_reg_isouart: regisouartgrp { 808 fsl,pins = < 809 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 810 >; 811 }; 812 813 pinctrl_reg_ioexp: regioexpgrp { 814 fsl,pins = < 815 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 816 >; 817 }; 818 819 pinctrl_reg_wl: regwlgrp { 820 fsl,pins = < 821 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 822 >; 823 }; 824 825 pinctrl_reg_usb2: regusb1grp { 826 fsl,pins = < 827 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x41 828 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x41 829 >; 830 }; 831 832 pinctrl_spi1: spi1grp { 833 fsl,pins = < 834 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 835 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 836 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 837 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 838 >; 839 }; 840 841 pinctrl_uart1: uart1grp { 842 fsl,pins = < 843 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 844 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 845 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 846 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 847 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 848 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 849 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 850 >; 851 }; 852 853 pinctrl_uart1_gpio: uart1gpiogrp { 854 fsl,pins = < 855 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ 856 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ 857 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ 858 >; 859 }; 860 861 pinctrl_uart2: uart2grp { 862 fsl,pins = < 863 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 864 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 865 >; 866 }; 867 868 pinctrl_uart3: uart3grp { 869 fsl,pins = < 870 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 871 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 872 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 873 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 874 >; 875 }; 876 877 pinctrl_uart3_gpio: uart3gpiogrp { 878 fsl,pins = < 879 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */ 880 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */ 881 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */ 882 >; 883 }; 884 885 pinctrl_uart4: uart4grp { 886 fsl,pins = < 887 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 888 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 889 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 890 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 891 >; 892 }; 893 894 pinctrl_uart4_gpio: uart4gpiogrp { 895 fsl,pins = < 896 897 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ 898 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ 899 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ 900 >; 901 }; 902 903 pinctrl_usdhc1: usdhc1grp { 904 fsl,pins = < 905 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 906 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 907 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 908 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 909 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 910 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 911 >; 912 }; 913 914 pinctrl_usdhc2: usdhc2grp { 915 fsl,pins = < 916 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 917 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 918 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 919 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 920 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 921 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 922 >; 923 }; 924 925 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 926 fsl,pins = < 927 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 928 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 929 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 930 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 931 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 932 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 933 >; 934 }; 935 936 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 937 fsl,pins = < 938 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 939 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 940 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 941 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 942 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 943 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 944 >; 945 }; 946 947 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 948 fsl,pins = < 949 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 950 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 951 >; 952 }; 953 954 pinctrl_usdhc3: usdhc3grp { 955 fsl,pins = < 956 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 957 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 958 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 959 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 960 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 961 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 962 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 963 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 964 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 965 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 966 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 967 >; 968 }; 969 970 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 971 fsl,pins = < 972 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 973 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 974 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 975 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 976 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 977 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 978 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 979 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 980 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 981 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 982 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 983 >; 984 }; 985 986 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 987 fsl,pins = < 988 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 989 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 990 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 991 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 992 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 993 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 994 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 995 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 996 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 997 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 998 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 999 >; 1000 }; 1001 1002 pinctrl_wdog: wdoggrp { 1003 fsl,pins = < 1004 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1005 >; 1006 }; 1007}; 1008 1009&cpu_alert0 { 1010 temperature = <95000>; 1011 hysteresis = <2000>; 1012 type = "passive"; 1013}; 1014 1015&cpu_crit0 { 1016 temperature = <105000>; 1017 hysteresis = <2000>; 1018 type = "critical"; 1019}; 1020