1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2020 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16	model = "Gateworks Venice GW7901 i.MX8MM board";
17	compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
18
19	aliases {
20		ethernet0 = &fec1;
21		ethernet1 = &lan1;
22		ethernet2 = &lan2;
23		ethernet3 = &lan3;
24		ethernet4 = &lan4;
25		usb0 = &usbotg1;
26		usb1 = &usbotg2;
27	};
28
29	chosen {
30		stdout-path = &uart2;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0 0x80000000>;
36	};
37
38	gpio-keys {
39		compatible = "gpio-keys";
40
41		key-user-pb {
42			label = "user_pb";
43			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
44			linux,code = <BTN_0>;
45		};
46
47		key-user-pb1x {
48			label = "user_pb1x";
49			linux,code = <BTN_1>;
50			interrupt-parent = <&gsc>;
51			interrupts = <0>;
52		};
53
54		key-erased {
55			label = "key_erased";
56			linux,code = <BTN_2>;
57			interrupt-parent = <&gsc>;
58			interrupts = <1>;
59		};
60
61		key-eeprom-wp {
62			label = "eeprom_wp";
63			linux,code = <BTN_3>;
64			interrupt-parent = <&gsc>;
65			interrupts = <2>;
66		};
67
68		key-tamper {
69			label = "tamper";
70			linux,code = <BTN_4>;
71			interrupt-parent = <&gsc>;
72			interrupts = <5>;
73		};
74
75		switch-hold {
76			label = "switch_hold";
77			linux,code = <BTN_5>;
78			interrupt-parent = <&gsc>;
79			interrupts = <7>;
80		};
81	};
82
83	led-controller {
84		compatible = "gpio-leds";
85
86		led-0 {
87			function = LED_FUNCTION_STATUS;
88			color = <LED_COLOR_ID_RED>;
89			label = "led01_red";
90			gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
91			default-state = "off";
92		};
93
94		led-1 {
95			function = LED_FUNCTION_STATUS;
96			color = <LED_COLOR_ID_GREEN>;
97			label = "led01_grn";
98			gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
99			default-state = "off";
100		};
101
102		led-2 {
103			function = LED_FUNCTION_STATUS;
104			color = <LED_COLOR_ID_RED>;
105			label = "led02_red";
106			gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
107			default-state = "off";
108		};
109
110		led-3 {
111			function = LED_FUNCTION_STATUS;
112			color = <LED_COLOR_ID_GREEN>;
113			label = "led02_grn";
114			gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
115			default-state = "off";
116		};
117
118		led-4 {
119			function = LED_FUNCTION_STATUS;
120			color = <LED_COLOR_ID_RED>;
121			label = "led03_red";
122			gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
123			default-state = "off";
124		};
125
126		led-5 {
127			function = LED_FUNCTION_STATUS;
128			color = <LED_COLOR_ID_GREEN>;
129			label = "led03_grn";
130			gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
131			default-state = "off";
132		};
133
134		led-6 {
135			function = LED_FUNCTION_STATUS;
136			color = <LED_COLOR_ID_RED>;
137			label = "led04_red";
138			gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
139			default-state = "off";
140		};
141
142		led-7 {
143			function = LED_FUNCTION_STATUS;
144			color = <LED_COLOR_ID_GREEN>;
145			label = "led04_grn";
146			gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
147			default-state = "off";
148		};
149
150		led-8 {
151			function = LED_FUNCTION_STATUS;
152			color = <LED_COLOR_ID_RED>;
153			label = "led05_red";
154			gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
155			default-state = "off";
156		};
157
158		led-9 {
159			function = LED_FUNCTION_STATUS;
160			color = <LED_COLOR_ID_GREEN>;
161			label = "led05_grn";
162			gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
163			default-state = "off";
164		};
165
166		led-a {
167			function = LED_FUNCTION_STATUS;
168			color = <LED_COLOR_ID_RED>;
169			label = "led06_red";
170			gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
171			default-state = "off";
172		};
173
174		led-b {
175			function = LED_FUNCTION_STATUS;
176			color = <LED_COLOR_ID_GREEN>;
177			label = "led06_grn";
178			gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
179			default-state = "off";
180		};
181	};
182
183	pcie0_refclk: pcie0-refclk {
184		compatible = "fixed-clock";
185		#clock-cells = <0>;
186		clock-frequency = <100000000>;
187	};
188
189	reg_3p3v: regulator-3p3v {
190		compatible = "regulator-fixed";
191		regulator-name = "3P3V";
192		regulator-min-microvolt = <3300000>;
193		regulator-max-microvolt = <3300000>;
194	};
195
196	regulator-ioexp {
197		pinctrl-names = "default";
198		pinctrl-0 = <&pinctrl_reg_ioexp>;
199		compatible = "regulator-fixed";
200		regulator-name = "ioexp";
201		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
202		enable-active-high;
203		startup-delay-us = <100>;
204		regulator-min-microvolt = <3300000>;
205		regulator-max-microvolt = <3300000>;
206		regulator-always-on;
207	};
208
209	regulator-isouart {
210		pinctrl-names = "default";
211		pinctrl-0 = <&pinctrl_reg_isouart>;
212		compatible = "regulator-fixed";
213		regulator-name = "iso_uart";
214		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
215		startup-delay-us = <100>;
216		regulator-min-microvolt = <3300000>;
217		regulator-max-microvolt = <3300000>;
218		regulator-always-on;
219	};
220
221	reg_usb2_vbus: regulator-usb2 {
222		pinctrl-names = "default";
223		pinctrl-0 = <&pinctrl_reg_usb2>;
224		compatible = "regulator-fixed";
225		regulator-name = "usb_usb2_vbus";
226		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
227		enable-active-high;
228		regulator-min-microvolt = <5000000>;
229		regulator-max-microvolt = <5000000>;
230	};
231
232	reg_wifi: regulator-wifi {
233		pinctrl-names = "default";
234		pinctrl-0 = <&pinctrl_reg_wl>;
235		compatible = "regulator-fixed";
236		regulator-name = "wifi";
237		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
238		enable-active-high;
239		startup-delay-us = <100>;
240		regulator-min-microvolt = <3300000>;
241		regulator-max-microvolt = <3300000>;
242	};
243};
244
245&A53_0 {
246	cpu-supply = <&buck2>;
247};
248
249&A53_1 {
250	cpu-supply = <&buck2>;
251};
252
253&A53_2 {
254	cpu-supply = <&buck2>;
255};
256
257&A53_3 {
258	cpu-supply = <&buck2>;
259};
260
261&ddrc {
262	operating-points-v2 = <&ddrc_opp_table>;
263
264	ddrc_opp_table: opp-table {
265		compatible = "operating-points-v2";
266
267		opp-25000000 {
268			opp-hz = /bits/ 64 <25000000>;
269		};
270
271		opp-100000000 {
272			opp-hz = /bits/ 64 <100000000>;
273		};
274
275		opp-750000000 {
276			opp-hz = /bits/ 64 <750000000>;
277		};
278	};
279};
280
281&disp_blk_ctrl {
282	status = "disabled";
283};
284
285&ecspi1 {
286	pinctrl-names = "default";
287	pinctrl-0 = <&pinctrl_spi1>;
288	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
289	status = "okay";
290
291	flash@0 {
292		compatible = "jedec,spi-nor";
293		reg = <0>;
294		spi-max-frequency = <40000000>;
295		status = "okay";
296	};
297};
298
299&fec1 {
300	pinctrl-names = "default";
301	pinctrl-0 = <&pinctrl_fec1>;
302	phy-mode = "rgmii-id";
303	local-mac-address = [00 00 00 00 00 00];
304	status = "okay";
305
306	fixed-link {
307		speed = <1000>;
308		full-duplex;
309	};
310};
311
312&gpio1 {
313	gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
314		"", "uart1_rs232#", "dig1_in", "dig1_out",
315		"", "", "", "", "", "", "", "",
316		"", "", "", "", "", "", "", "",
317		"", "", "", "", "", "", "", "";
318};
319
320&gpio4 {
321	gpio-line-names = "", "", "", "",
322		"", "", "uart3_rs232#", "uart3_rs422#",
323		"uart3_rs485#", "", "", "", "", "", "", "",
324		"", "", "", "", "", "", "", "",
325		"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
326};
327
328&gpio5 {
329	gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
330		"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
331		"", "", "", "", "", "", "", "",
332		"", "", "", "", "", "", "", "";
333};
334
335&gpu_2d {
336	status = "disabled";
337};
338
339&gpu_3d {
340	status = "disabled";
341};
342
343&i2c1 {
344	clock-frequency = <100000>;
345	pinctrl-names = "default", "gpio";
346	pinctrl-0 = <&pinctrl_i2c1>;
347	pinctrl-1 = <&pinctrl_i2c1_gpio>;
348	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
349	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
350	status = "okay";
351
352	gsc: gsc@20 {
353		compatible = "gw,gsc";
354		reg = <0x20>;
355		pinctrl-0 = <&pinctrl_gsc>;
356		interrupt-parent = <&gpio4>;
357		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
358		interrupt-controller;
359		#interrupt-cells = <1>;
360
361		adc {
362			compatible = "gw,gsc-adc";
363			#address-cells = <1>;
364			#size-cells = <0>;
365
366			channel@6 {
367				gw,mode = <0>;
368				reg = <0x06>;
369				label = "temp";
370			};
371
372			channel@8 {
373				gw,mode = <3>;
374				reg = <0x08>;
375				label = "vdd_bat";
376			};
377
378			channel@82 {
379				gw,mode = <2>;
380				reg = <0x82>;
381				label = "vin_aux1";
382				gw,voltage-divider-ohms = <22100 1000>;
383			};
384
385			channel@84 {
386				gw,mode = <2>;
387				reg = <0x84>;
388				label = "vin_aux2";
389				gw,voltage-divider-ohms = <22100 1000>;
390			};
391
392			channel@86 {
393				gw,mode = <2>;
394				reg = <0x86>;
395				label = "vdd_vin";
396				gw,voltage-divider-ohms = <22100 1000>;
397			};
398
399			channel@88 {
400				gw,mode = <2>;
401				reg = <0x88>;
402				label = "vdd_3p3";
403				gw,voltage-divider-ohms = <10000 10000>;
404			};
405
406			channel@8c {
407				gw,mode = <2>;
408				reg = <0x8c>;
409				label = "vdd_2p5";
410				gw,voltage-divider-ohms = <10000 10000>;
411			};
412
413			channel@8e {
414				gw,mode = <2>;
415				reg = <0x8e>;
416				label = "vdd_0p95";
417			};
418
419			channel@90 {
420				gw,mode = <2>;
421				reg = <0x90>;
422				label = "vdd_soc";
423			};
424
425			channel@92 {
426				gw,mode = <2>;
427				reg = <0x92>;
428				label = "vdd_arm";
429			};
430
431			channel@98 {
432				gw,mode = <2>;
433				reg = <0x98>;
434				label = "vdd_1p8";
435			};
436
437			channel@9a {
438				gw,mode = <2>;
439				reg = <0x9a>;
440				label = "vdd_1p2";
441			};
442
443			channel@9c {
444				gw,mode = <2>;
445				reg = <0x9c>;
446				label = "vdd_dram";
447			};
448
449			channel@a2 {
450				gw,mode = <2>;
451				reg = <0xa2>;
452				label = "vdd_gsc";
453				gw,voltage-divider-ohms = <10000 10000>;
454			};
455		};
456	};
457
458	gpio: gpio@23 {
459		compatible = "nxp,pca9555";
460		reg = <0x23>;
461		gpio-controller;
462		#gpio-cells = <2>;
463		interrupt-parent = <&gsc>;
464		interrupts = <4>;
465	};
466
467	eeprom@50 {
468		compatible = "atmel,24c02";
469		reg = <0x50>;
470		pagesize = <16>;
471	};
472
473	eeprom@51 {
474		compatible = "atmel,24c02";
475		reg = <0x51>;
476		pagesize = <16>;
477	};
478
479	eeprom@52 {
480		compatible = "atmel,24c02";
481		reg = <0x52>;
482		pagesize = <16>;
483	};
484
485	eeprom@53 {
486		compatible = "atmel,24c02";
487		reg = <0x53>;
488		pagesize = <16>;
489	};
490
491	rtc@68 {
492		compatible = "dallas,ds1672";
493		reg = <0x68>;
494	};
495};
496
497&i2c2 {
498	clock-frequency = <400000>;
499	pinctrl-names = "default", "gpio";
500	pinctrl-0 = <&pinctrl_i2c2>;
501	pinctrl-1 = <&pinctrl_i2c2_gpio>;
502	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
503	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
504	status = "okay";
505
506	pmic@4b {
507		compatible = "rohm,bd71847";
508		reg = <0x4b>;
509		pinctrl-names = "default";
510		pinctrl-0 = <&pinctrl_pmic>;
511		interrupt-parent = <&gpio3>;
512		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
513		rohm,reset-snvs-powered;
514		#clock-cells = <0>;
515		clocks = <&osc_32k 0>;
516		clock-output-names = "clk-32k-out";
517
518		regulators {
519			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
520			BUCK1 {
521				regulator-name = "buck1";
522				regulator-min-microvolt = <700000>;
523				regulator-max-microvolt = <1300000>;
524				regulator-boot-on;
525				regulator-always-on;
526				regulator-ramp-delay = <1250>;
527			};
528
529			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
530			buck2: BUCK2 {
531				regulator-name = "buck2";
532				regulator-min-microvolt = <700000>;
533				regulator-max-microvolt = <1300000>;
534				regulator-boot-on;
535				regulator-always-on;
536				regulator-ramp-delay = <1250>;
537				rohm,dvs-run-voltage = <1000000>;
538				rohm,dvs-idle-voltage = <900000>;
539			};
540
541			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
542			BUCK3 {
543				regulator-name = "buck3";
544				regulator-min-microvolt = <700000>;
545				regulator-max-microvolt = <1350000>;
546				regulator-boot-on;
547				regulator-always-on;
548			};
549
550			/* vdd_3p3 */
551			BUCK4 {
552				regulator-name = "buck4";
553				regulator-min-microvolt = <3000000>;
554				regulator-max-microvolt = <3300000>;
555				regulator-boot-on;
556				regulator-always-on;
557			};
558
559			/* vdd_1p8 */
560			BUCK5 {
561				regulator-name = "buck5";
562				regulator-min-microvolt = <1605000>;
563				regulator-max-microvolt = <1995000>;
564				regulator-boot-on;
565				regulator-always-on;
566			};
567
568			/* vdd_dram */
569			BUCK6 {
570				regulator-name = "buck6";
571				regulator-min-microvolt = <800000>;
572				regulator-max-microvolt = <1400000>;
573				regulator-boot-on;
574				regulator-always-on;
575			};
576
577			/* nvcc_snvs_1p8 */
578			LDO1 {
579				regulator-name = "ldo1";
580				regulator-min-microvolt = <1600000>;
581				regulator-max-microvolt = <1900000>;
582				regulator-boot-on;
583				regulator-always-on;
584			};
585
586			/* vdd_snvs_0p8 */
587			LDO2 {
588				regulator-name = "ldo2";
589				regulator-min-microvolt = <800000>;
590				regulator-max-microvolt = <900000>;
591				regulator-boot-on;
592				regulator-always-on;
593			};
594
595			/* vdda_1p8 */
596			LDO3 {
597				regulator-name = "ldo3";
598				regulator-min-microvolt = <1800000>;
599				regulator-max-microvolt = <3300000>;
600				regulator-boot-on;
601				regulator-always-on;
602			};
603
604			LDO4 {
605				regulator-name = "ldo4";
606				regulator-min-microvolt = <900000>;
607				regulator-max-microvolt = <1800000>;
608				regulator-boot-on;
609				regulator-always-on;
610			};
611
612			LDO6 {
613				regulator-name = "ldo6";
614				regulator-min-microvolt = <900000>;
615				regulator-max-microvolt = <1800000>;
616				regulator-boot-on;
617				regulator-always-on;
618			};
619		};
620	};
621};
622
623&i2c3 {
624	clock-frequency = <400000>;
625	pinctrl-names = "default", "gpio";
626	pinctrl-0 = <&pinctrl_i2c3>;
627	pinctrl-1 = <&pinctrl_i2c3_gpio>;
628	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
629	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
630	status = "okay";
631
632	leds_gpio: gpio@20 {
633		compatible = "nxp,pca9555";
634		reg = <0x20>;
635		gpio-controller;
636		#gpio-cells = <2>;
637	};
638
639	switch: switch@5f {
640		compatible = "microchip,ksz9897";
641		reg = <0x5f>;
642		pinctrl-0 = <&pinctrl_ksz>;
643		interrupt-parent = <&gpio4>;
644		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
645		phy-mode = "rgmii-id";
646
647		ports {
648			#address-cells = <1>;
649			#size-cells = <0>;
650
651			lan1: port@0 {
652				reg = <0>;
653				label = "lan1";
654				phy-mode = "internal";
655				local-mac-address = [00 00 00 00 00 00];
656			};
657
658			lan2: port@1 {
659				reg = <1>;
660				label = "lan2";
661				phy-mode = "internal";
662				local-mac-address = [00 00 00 00 00 00];
663			};
664
665			lan3: port@2 {
666				reg = <2>;
667				label = "lan3";
668				phy-mode = "internal";
669				local-mac-address = [00 00 00 00 00 00];
670			};
671
672			lan4: port@3 {
673				reg = <3>;
674				label = "lan4";
675				phy-mode = "internal";
676				local-mac-address = [00 00 00 00 00 00];
677			};
678
679			port@5 {
680				reg = <5>;
681				label = "cpu";
682				ethernet = <&fec1>;
683				phy-mode = "rgmii-id";
684
685				fixed-link {
686					speed = <1000>;
687					full-duplex;
688				};
689			};
690		};
691	};
692
693	crypto@60 {
694		compatible = "atmel,atecc508a";
695		reg = <0x60>;
696	};
697};
698
699&i2c4 {
700	clock-frequency = <400000>;
701	pinctrl-names = "default", "gpio";
702	pinctrl-0 = <&pinctrl_i2c4>;
703	pinctrl-1 = <&pinctrl_i2c4_gpio>;
704	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
705	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
706	status = "okay";
707};
708
709&pcie_phy {
710	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
711	fsl,clkreq-unsupported;
712	clocks = <&pcie0_refclk>;
713	clock-names = "ref";
714	status = "okay";
715};
716
717&pcie0 {
718	pinctrl-names = "default";
719	pinctrl-0 = <&pinctrl_pcie0>;
720	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
721	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
722		 <&clk IMX8MM_CLK_PCIE1_AUX>;
723	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
724			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
725	assigned-clock-rates = <10000000>, <250000000>;
726	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
727				 <&clk IMX8MM_SYS_PLL2_250M>;
728	status = "okay";
729};
730
731&pgc_gpu {
732	status = "disabled";
733};
734
735&pgc_gpumix {
736	status = "disabled";
737};
738
739&pgc_mipi {
740	status = "disabled";
741};
742
743&uart1 {
744	pinctrl-names = "default";
745	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
746	rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
747	cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
748	dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
749	dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
750	dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
751	status = "okay";
752};
753
754/* console */
755&uart2 {
756	pinctrl-names = "default";
757	pinctrl-0 = <&pinctrl_uart2>;
758	status = "okay";
759};
760
761&uart3 {
762	pinctrl-names = "default";
763	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
764	cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
765	rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
766	status = "okay";
767};
768
769&uart4 {
770	pinctrl-names = "default";
771	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
772	cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
773	rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
774	status = "okay";
775};
776
777&usbotg1 {
778	dr_mode = "host";
779	disable-over-current;
780	status = "okay";
781};
782
783&usbotg2 {
784	dr_mode = "host";
785	vbus-supply = <&reg_usb2_vbus>;
786	over-current-active-low;
787	status = "okay";
788};
789
790/* SDIO WiFi */
791&usdhc1 {
792	pinctrl-names = "default", "state_100mhz", "state_200mhz";
793	pinctrl-0 = <&pinctrl_usdhc1>;
794	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
795	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
796	bus-width = <4>;
797	non-removable;
798	vmmc-supply = <&reg_wifi>;
799	#address-cells = <1>;
800	#size-cells = <0>;
801	status = "okay";
802
803	wifi@0 {
804		compatible = "brcm,bcm43455-fmac";
805		reg = <0>;
806	};
807};
808
809/* microSD */
810&usdhc2 {
811	pinctrl-names = "default", "state_100mhz", "state_200mhz";
812	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
813	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
814	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
815	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
816	bus-width = <4>;
817	vmmc-supply = <&reg_3p3v>;
818	status = "okay";
819};
820
821/* eMMC */
822&usdhc3 {
823	pinctrl-names = "default", "state_100mhz", "state_200mhz";
824	pinctrl-0 = <&pinctrl_usdhc3>;
825	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
826	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
827	bus-width = <8>;
828	non-removable;
829	status = "okay";
830};
831
832&wdog1 {
833	pinctrl-names = "default";
834	pinctrl-0 = <&pinctrl_wdog>;
835	fsl,ext-reset-output;
836	status = "okay";
837};
838
839&iomuxc {
840	pinctrl-names = "default";
841	pinctrl-0 = <&pinctrl_hog>;
842
843	pinctrl_hog: hoggrp {
844		fsl,pins = <
845			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* DIG2_OUT */
846			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* DIG2_IN */
847			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* DIG1_IN */
848			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIG1_OUT */
849			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x40000041 /* SIM2DET# */
850			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x40000041 /* SIM1DET# */
851			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* SIM2SEL */
852		>;
853	};
854
855	pinctrl_fec1: fec1grp {
856		fsl,pins = <
857			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
858			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
859			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
860			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
861			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
862			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
863			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
864			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
865			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
866			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
867			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
868			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
869			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
870			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
871			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19 /* IRQ# */
872			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19 /* RST# */
873		>;
874	};
875
876	pinctrl_gsc: gscgrp {
877		fsl,pins = <
878			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16	0x159
879		>;
880	};
881
882	pinctrl_i2c1: i2c1grp {
883		fsl,pins = <
884			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
885			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
886		>;
887	};
888
889	pinctrl_i2c1_gpio: i2c1gpiogrp {
890		fsl,pins = <
891			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
892			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
893		>;
894	};
895
896	pinctrl_i2c2: i2c2grp {
897		fsl,pins = <
898			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
899			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
900		>;
901	};
902
903	pinctrl_i2c2_gpio: i2c2gpiogrp {
904		fsl,pins = <
905			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
906			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
907		>;
908	};
909
910	pinctrl_i2c3: i2c3grp {
911		fsl,pins = <
912			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
913			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
914		>;
915	};
916
917	pinctrl_i2c3_gpio: i2c3gpiogrp {
918		fsl,pins = <
919			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
920			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
921		>;
922	};
923
924	pinctrl_i2c4: i2c4grp {
925		fsl,pins = <
926			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
927			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
928		>;
929	};
930
931	pinctrl_i2c4_gpio: i2c4gpiogrp {
932		fsl,pins = <
933			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
934			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
935		>;
936	};
937
938	pinctrl_ksz: kszgrp {
939		fsl,pins = <
940			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18	0x41
941			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x41 /* RST# */
942		>;
943	};
944
945	pinctrl_pcie0: pciegrp {
946		fsl,pins = <
947			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x40000041 /* WDIS# */
948			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x41
949		>;
950	};
951
952	pinctrl_pmic: pmicgrp {
953		fsl,pins = <
954			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x41
955		>;
956	};
957
958	pinctrl_reg_isouart: regisouartgrp {
959		fsl,pins = <
960			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041
961		>;
962	};
963
964	pinctrl_reg_ioexp: regioexpgrp {
965		fsl,pins = <
966			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041
967		>;
968	};
969
970	pinctrl_reg_wl: regwlgrp {
971		fsl,pins = <
972			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x40000041
973		>;
974	};
975
976	pinctrl_reg_usb2: regusb1grp {
977		fsl,pins = <
978			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x41
979			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17	0x140
980			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC	0x140
981		>;
982	};
983
984	pinctrl_spi1: spi1grp {
985		fsl,pins = <
986			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
987			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
988			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
989			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140
990		>;
991	};
992
993	pinctrl_uart1: uart1grp {
994		fsl,pins = <
995			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
996			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
997			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x140
998			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x140
999			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x140
1000			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x140
1001			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x140
1002		>;
1003	};
1004
1005	pinctrl_uart1_gpio: uart1gpiogrp {
1006		fsl,pins = <
1007			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000041 /* RS422# */
1008			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x40000041 /* RS485# */
1009			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x40000041 /* RS232# */
1010		>;
1011	};
1012
1013	pinctrl_uart2: uart2grp {
1014		fsl,pins = <
1015			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
1016			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
1017		>;
1018	};
1019
1020	pinctrl_uart3: uart3grp {
1021		fsl,pins = <
1022			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
1023			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
1024			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x140
1025			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140
1026		>;
1027	};
1028
1029	pinctrl_uart3_gpio: uart3gpiogrp {
1030		fsl,pins = <
1031			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x40000110 /* RS232# */
1032			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000110 /* RS422# */
1033			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8	0x40000110 /* RS485# */
1034		>;
1035	};
1036
1037	pinctrl_uart4: uart4grp {
1038		fsl,pins = <
1039			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
1040			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
1041			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x140
1042			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x140
1043		>;
1044	};
1045
1046	pinctrl_uart4_gpio: uart4gpiogrp {
1047		fsl,pins = <
1048
1049			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10	0x40000041 /* RS232# */
1050			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40000041 /* RS422# */
1051			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* RS485# */
1052		>;
1053	};
1054
1055	pinctrl_usdhc1: usdhc1grp {
1056		fsl,pins = <
1057			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
1058			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
1059			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
1060			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
1061			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
1062			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
1063		>;
1064	};
1065
1066	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1067		fsl,pins = <
1068			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
1069			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
1070			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
1071			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
1072			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
1073			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
1074		>;
1075	};
1076
1077	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1078		fsl,pins = <
1079			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
1080			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
1081			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
1082			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
1083			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
1084			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
1085		>;
1086	};
1087
1088	pinctrl_usdhc2: usdhc2grp {
1089		fsl,pins = <
1090			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
1091			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
1092			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
1093			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
1094			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
1095			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
1096		>;
1097	};
1098
1099	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1100		fsl,pins = <
1101			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
1102			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
1103			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
1104			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
1105			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
1106			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
1107		>;
1108	};
1109
1110	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1111		fsl,pins = <
1112			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
1113			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
1114			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
1115			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
1116			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
1117			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
1118		>;
1119	};
1120
1121	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
1122		fsl,pins = <
1123			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
1124			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
1125		>;
1126	};
1127
1128	pinctrl_usdhc3: usdhc3grp {
1129		fsl,pins = <
1130			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
1131			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
1132			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
1133			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
1134			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
1135			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
1136			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
1137			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
1138			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
1139			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
1140			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
1141		>;
1142	};
1143
1144	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1145		fsl,pins = <
1146			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
1147			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
1148			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
1149			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
1150			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
1151			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
1152			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
1153			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
1154			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
1155			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
1156			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
1157		>;
1158	};
1159
1160	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1161		fsl,pins = <
1162			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
1163			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
1164			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
1165			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
1166			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
1167			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
1168			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
1169			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
1170			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
1171			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
1172			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
1173		>;
1174	};
1175
1176	pinctrl_wdog: wdoggrp {
1177		fsl,pins = <
1178			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
1179		>;
1180	};
1181};
1182