1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2020 Compass Electronics Group, LLC
4 */
5
6#include <dt-bindings/phy/phy-imx8-pcie.h>
7
8/ {
9	leds {
10		compatible = "gpio-leds";
11
12		led0 {
13			label = "gen_led0";
14			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
15			default-state = "off";
16		};
17
18		led1 {
19			label = "gen_led1";
20			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
21			default-state = "off";
22		};
23
24		led2 {
25			label = "gen_led2";
26			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
27			default-state = "off";
28		};
29
30		led3 {
31			pinctrl-names = "default";
32			pinctrl-0 = <&pinctrl_led3>;
33			label = "heartbeat";
34			gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
35			linux,default-trigger = "heartbeat";
36		};
37	};
38
39	pcie0_refclk: pcie0-refclk {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <100000000>;
43	};
44
45	pcie0_refclk_gated:  pcie0-refclk-gated {
46		compatible = "gpio-gate-clock";
47		clocks = <&pcie0_refclk>;
48		#clock-cells = <0>;
49		enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
50	};
51
52	reg_audio: regulator-audio {
53		compatible = "regulator-fixed";
54		regulator-name = "3v3_aud";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
58		enable-active-high;
59	};
60
61	reg_usbotg1: regulator-usbotg1 {
62		compatible = "regulator-fixed";
63		pinctrl-names = "default";
64		pinctrl-0 = <&pinctrl_reg_usb_otg1>;
65		regulator-name = "usb_otg_vbus";
66		regulator-min-microvolt = <5000000>;
67		regulator-max-microvolt = <5000000>;
68		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
69		enable-active-high;
70	};
71
72	reg_camera: regulator-camera {
73		compatible = "regulator-fixed";
74		regulator-name = "mipi_pwr";
75		regulator-min-microvolt = <2800000>;
76		regulator-max-microvolt = <2800000>;
77		gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
78		enable-active-high;
79		startup-delay-us = <100000>;
80	};
81
82	reg_pcie0: regulator-pcie {
83		compatible = "regulator-fixed";
84		regulator-name = "pci_pwr_en";
85		regulator-min-microvolt = <3300000>;
86		regulator-max-microvolt = <3300000>;
87		enable-active-high;
88		gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
89		startup-delay-us = <100000>;
90	};
91
92	reg_usdhc2_vmmc: regulator-usdhc2 {
93		compatible = "regulator-fixed";
94		regulator-name = "VSD_3V3";
95		regulator-min-microvolt = <3300000>;
96		regulator-max-microvolt = <3300000>;
97		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
98		enable-active-high;
99	};
100
101	sound {
102		compatible = "fsl,imx-audio-wm8962";
103		model = "wm8962-audio";
104		audio-cpu = <&sai3>;
105		audio-codec = <&wm8962>;
106		audio-routing =
107			"Headphone Jack", "HPOUTL",
108			"Headphone Jack", "HPOUTR",
109			"Ext Spk", "SPKOUTL",
110			"Ext Spk", "SPKOUTR",
111			"AMIC", "MICBIAS",
112			"IN3R", "AMIC";
113	};
114};
115
116&csi {
117	status = "okay";
118};
119
120&ecspi2 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&pinctrl_espi2>;
123	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
124	status = "okay";
125
126	eeprom@0 {
127		compatible = "microchip,at25160bn", "atmel,at25";
128		reg = <0>;
129		spi-max-frequency = <5000000>;
130		spi-cpha;
131		spi-cpol;
132		pagesize = <32>;
133		size = <2048>;
134		address-width = <16>;
135	};
136};
137
138&i2c2 {
139	clock-frequency = <400000>;
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_i2c2>;
142	status = "okay";
143
144	camera@3c {
145		compatible = "ovti,ov5640";
146		pinctrl-names = "default";
147		pinctrl-0 = <&pinctrl_ov5640>;
148		reg = <0x3c>;
149		clocks = <&clk IMX8MM_CLK_CLKO1>;
150		clock-names = "xclk";
151		assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
152		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
153		assigned-clock-rates = <24000000>;
154		AVDD-supply = <&reg_camera>;  /* 2.8v */
155		powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
156		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
157
158		port {
159			/* MIPI CSI-2 bus endpoint */
160			ov5640_to_mipi_csi2: endpoint {
161				remote-endpoint = <&imx8mm_mipi_csi_in>;
162				clock-lanes = <0>;
163				data-lanes = <1 2>;
164			};
165		};
166	};
167};
168
169&i2c4 {
170	clock-frequency = <400000>;
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_i2c4>;
173	status = "okay";
174
175	wm8962: audio-codec@1a {
176		compatible = "wlf,wm8962";
177		reg = <0x1a>;
178		clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
179		DCVDD-supply = <&reg_audio>;
180		DBVDD-supply = <&reg_audio>;
181		AVDD-supply = <&reg_audio>;
182		CPVDD-supply = <&reg_audio>;
183		MICVDD-supply = <&reg_audio>;
184		PLLVDD-supply = <&reg_audio>;
185		SPKVDD1-supply = <&reg_audio>;
186		SPKVDD2-supply = <&reg_audio>;
187		gpio-cfg = <
188			0x0000 /* 0:Default */
189			0x0000 /* 1:Default */
190			0x0000 /* 2:FN_DMICCLK */
191			0x0000 /* 3:Default */
192			0x0000 /* 4:FN_DMICCDAT */
193			0x0000 /* 5:Default */
194		>;
195	};
196
197	pca6416_0: gpio@20 {
198		compatible = "nxp,pcal6416";
199		reg = <0x20>;
200		pinctrl-names = "default";
201		pinctrl-0 = <&pinctrl_pcal6414>;
202		gpio-controller;
203		#gpio-cells = <2>;
204		interrupt-parent = <&gpio4>;
205		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
206	};
207
208	pca6416_1: gpio@21 {
209		compatible = "nxp,pcal6416";
210		reg = <0x21>;
211		gpio-controller;
212		#gpio-cells = <2>;
213		interrupt-parent = <&gpio4>;
214		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
215	};
216};
217
218&mipi_csi {
219	status = "okay";
220	ports {
221		port@0 {
222			imx8mm_mipi_csi_in: endpoint {
223				remote-endpoint = <&ov5640_to_mipi_csi2>;
224				data-lanes = <1 2>;
225			};
226		};
227	};
228};
229
230&pcie_phy {
231	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
232	fsl,tx-deemph-gen1 = <0x2d>;
233	fsl,tx-deemph-gen2 = <0xf>;
234	fsl,clkreq-unsupported;
235	clocks = <&pcie0_refclk_gated>;
236	clock-names = "ref";
237	status = "okay";
238};
239
240&pcie0 {
241	pinctrl-names = "default";
242	pinctrl-0 = <&pinctrl_pcie0>;
243	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
244	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
245		 <&pcie0_refclk_gated>;
246	clock-names = "pcie", "pcie_aux", "pcie_bus";
247	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
248			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
249	assigned-clock-rates = <10000000>, <250000000>;
250	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
251				 <&clk IMX8MM_SYS_PLL2_250M>;
252	vpcie-supply = <&reg_pcie0>;
253	status = "okay";
254};
255
256&sai3 {
257	pinctrl-names = "default";
258	pinctrl-0 = <&pinctrl_sai3>;
259	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
260	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
261	assigned-clock-rates = <24576000>;
262	fsl,sai-mclk-direction-output;
263	status = "okay";
264};
265
266&snvs_pwrkey {
267	status = "okay";
268};
269
270&uart2 { /* console */
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_uart2>;
273	status = "okay";
274};
275
276&uart3 {
277	pinctrl-names = "default";
278	pinctrl-0 = <&pinctrl_uart3>;
279	assigned-clocks = <&clk IMX8MM_CLK_UART3>;
280	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
281	status = "okay";
282};
283
284&usbotg1 {
285	vbus-supply = <&reg_usbotg1>;
286	disable-over-current;
287	dr_mode="otg";
288	status = "okay";
289};
290
291&usbotg2 {
292	pinctrl-names = "default";
293	disable-over-current;
294	dr_mode="host";
295	status = "okay";
296};
297
298&usbphynop2 {
299	reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
300};
301
302&usdhc2 {
303	pinctrl-names = "default", "state_100mhz", "state_200mhz";
304	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
305	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
306	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
307	bus-width = <4>;
308	vmmc-supply = <&reg_usdhc2_vmmc>;
309	status = "okay";
310};
311
312&iomuxc {
313	pinctrl_espi2: espi2grp {
314		fsl,pins = <
315			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
316			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
317			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
318			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
319		>;
320	};
321
322	pinctrl_i2c2: i2c2grp {
323		fsl,pins = <
324			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
325			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
326		>;
327	};
328
329	pinctrl_i2c4: i2c4grp {
330		fsl,pins = <
331			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
332			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
333		>;
334	};
335
336	pinctrl_led3: led3grp {
337		fsl,pins = <
338			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41
339		>;
340	};
341
342	pinctrl_ov5640: ov5640grp {
343		fsl,pins = <
344			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
345			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
346			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
347		>;
348	};
349
350	pinctrl_pcal6414: pcal6414-gpiogrp {
351		fsl,pins = <
352			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
353		>;
354	};
355
356	pinctrl_reg_usb_otg1: usbotg1grp {
357		fsl,pins = <
358			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19
359		>;
360	};
361
362	pinctrl_pcie0: pcie0grp {
363		fsl,pins = <
364			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
365		>;
366	};
367
368	pinctrl_sai3: sai3grp {
369		fsl,pins = <
370			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
371			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
372			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
373			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
374			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
375		>;
376	};
377
378	pinctrl_uart2: uart2grp {
379		fsl,pins = <
380			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
381			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
382		>;
383	};
384
385	pinctrl_uart3: uart3grp {
386		fsl,pins = <
387			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40
388			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40
389		>;
390	};
391
392	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
393		fsl,pins = <
394			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
395			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
396		>;
397	};
398
399	pinctrl_usdhc2: usdhc2grp {
400		fsl,pins = <
401			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x190
402			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0
403			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
404			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
405			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
406			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
407			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
408		>;
409	};
410
411	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
412		fsl,pins = <
413			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
414			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
415			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
416			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
417			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
418			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
419			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
420		>;
421	};
422
423	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
424		fsl,pins = <
425			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
426			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
427			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
428			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
429			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
430			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
431			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
432		>;
433	};
434};
435