1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11	model = "Freescale i.MX8DXL EVK";
12	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14	aliases {
15		i2c2 = &i2c2;
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc2;
18		serial0 = &lpuart0;
19	};
20
21	chosen {
22		stdout-path = &lpuart0;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x00000000 0x80000000 0 0x40000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		/*
36		 * Memory reserved for optee usage. Please do not use.
37		 * This will be automatically added to dtb if OP-TEE is installed.
38		 * optee@96000000 {
39		 *     reg = <0 0x96000000 0 0x2000000>;
40		 *     no-map;
41		 * };
42		 */
43
44		/* global autoconfigured region for contiguous allocations */
45		linux,cma {
46			compatible = "shared-dma-pool";
47			reusable;
48			size = <0 0x14000000>;
49			alloc-ranges = <0 0x98000000 0 0x14000000>;
50			linux,cma-default;
51		};
52	};
53
54	mux3_en: regulator-0 {
55		compatible = "regulator-fixed";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "mux3_en";
59		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
60		regulator-always-on;
61	};
62
63	reg_fec1_sel: regulator-1 {
64		compatible = "regulator-fixed";
65		regulator-name = "fec1_supply";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
69		regulator-always-on;
70		status = "disabled";
71	};
72
73	reg_fec1_io: regulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "fec1_io_supply";
76		regulator-min-microvolt = <1800000>;
77		regulator-max-microvolt = <1800000>;
78		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		regulator-always-on;
81		status = "disabled";
82	};
83
84	reg_usdhc2_vmmc: regulator-3 {
85		compatible = "regulator-fixed";
86		regulator-name = "SD1_SPWR";
87		regulator-min-microvolt = <3000000>;
88		regulator-max-microvolt = <3000000>;
89		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
90		enable-active-high;
91		off-on-delay-us = <3480>;
92	};
93
94	reg_vref_1v8: regulator-adc-vref {
95		compatible = "regulator-fixed";
96		regulator-name = "vref_1v8";
97		regulator-min-microvolt = <1800000>;
98		regulator-max-microvolt = <1800000>;
99	};
100
101	mii_select: regulator-4 {
102		compatible = "regulator-fixed";
103		regulator-name = "mii-select";
104		regulator-min-microvolt = <3300000>;
105		regulator-max-microvolt = <3300000>;
106		gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
107		enable-active-high;
108		regulator-always-on;
109	};
110};
111
112&adc0 {
113	vref-supply = <&reg_vref_1v8>;
114	status = "okay";
115};
116
117&eqos {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_eqos>;
120	phy-mode = "rgmii-id";
121	phy-handle = <&ethphy0>;
122	nvmem-cells = <&fec_mac1>;
123	nvmem-cell-names = "mac-address";
124	snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
125	snps,reset-delays-us = <10 20 200000>;
126	status = "okay";
127
128	mdio {
129		compatible = "snps,dwmac-mdio";
130		#address-cells = <1>;
131		#size-cells = <0>;
132
133		ethphy0: ethernet-phy@0 {
134			compatible = "ethernet-phy-ieee802.3-c22";
135			reg = <0>;
136			eee-broken-1000t;
137			qca,disable-smarteee;
138			vddio-supply = <&vddio0>;
139
140			vddio0: vddio-regulator {
141				regulator-min-microvolt = <1800000>;
142				regulator-max-microvolt = <1800000>;
143			};
144		};
145	};
146};
147
148/*
149 * fec1 shares the some PINs with usdhc2.
150 * by default usdhc2 is enabled in this dts.
151 * Please disable usdhc2 to enable fec1
152 */
153&fec1 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_fec1>;
156	phy-mode = "rgmii-txid";
157	phy-handle = <&ethphy1>;
158	fsl,magic-packet;
159	rx-internal-delay-ps = <2000>;
160	nvmem-cells = <&fec_mac0>;
161	nvmem-cell-names = "mac-address";
162	status = "disabled";
163
164	mdio {
165		#address-cells = <1>;
166		#size-cells = <0>;
167
168		ethphy1: ethernet-phy@1 {
169			compatible = "ethernet-phy-ieee802.3-c22";
170			reg = <1>;
171			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
172			reset-assert-us = <10000>;
173			qca,disable-smarteee;
174			vddio-supply = <&vddio1>;
175
176			vddio1: vddio-regulator {
177				regulator-min-microvolt = <1800000>;
178				regulator-max-microvolt = <1800000>;
179			};
180		};
181	};
182};
183
184&i2c2 {
185	#address-cells = <1>;
186	#size-cells = <0>;
187	clock-frequency = <100000>;
188	pinctrl-names = "default";
189	pinctrl-0 = <&pinctrl_i2c2>;
190	status = "okay";
191
192	pca6416_1: gpio@20 {
193		compatible = "ti,tca6416";
194		reg = <0x20>;
195		gpio-controller;
196		#gpio-cells = <2>;
197	};
198
199	pca6416_2: gpio@21 {
200		compatible = "ti,tca6416";
201		reg = <0x21>;
202		gpio-controller;
203		#gpio-cells = <2>;
204	};
205
206	pca9548_1: i2c-mux@70 {
207		compatible = "nxp,pca9548";
208		#address-cells = <1>;
209		#size-cells = <0>;
210		reg = <0x70>;
211
212		i2c@0 {
213			#address-cells = <1>;
214			#size-cells = <0>;
215			reg = <0x0>;
216
217			max7322: gpio@68 {
218				compatible = "maxim,max7322";
219				reg = <0x68>;
220				gpio-controller;
221				#gpio-cells = <2>;
222				status = "disabled";
223			};
224		};
225
226		i2c@4 {
227			#address-cells = <1>;
228			#size-cells = <0>;
229			reg = <0x4>;
230		};
231
232		i2c@5 {
233			#address-cells = <1>;
234			#size-cells = <0>;
235			reg = <0x5>;
236		};
237
238		i2c@6 {
239			#address-cells = <1>;
240			#size-cells = <0>;
241			reg = <0x6>;
242		};
243	};
244};
245
246&lpuart0 {
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_lpuart0>;
249	status = "okay";
250};
251
252&lsio_gpio4 {
253	status = "okay";
254};
255
256&lsio_gpio5 {
257	status = "okay";
258};
259
260&thermal_zones {
261	pmic-thermal0 {
262		polling-delay-passive = <250>;
263		polling-delay = <2000>;
264		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
265
266		trips {
267			pmic_alert0: trip0 {
268				temperature = <110000>;
269				hysteresis = <2000>;
270				type = "passive";
271			};
272
273			pmic_crit0: trip1 {
274				temperature = <125000>;
275				hysteresis = <2000>;
276				type = "critical";
277			};
278		};
279
280		cooling-maps {
281			map0 {
282				trip = <&pmic_alert0>;
283				cooling-device =
284					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
285					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
286			};
287		};
288	};
289};
290
291&usbphy1 {
292	/* USB eye diagram tests result */
293	fsl,tx-d-cal = <114>;
294	status = "okay";
295};
296
297&usbotg1 {
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_usbotg1>;
300	srp-disable;
301	hnp-disable;
302	adp-disable;
303	power-active-high;
304	disable-over-current;
305	status = "okay";
306};
307
308&usbphy2 {
309	/* USB eye diagram tests result */
310	fsl,tx-d-cal = <111>;
311	status = "okay";
312};
313
314&usbotg2 {
315	pinctrl-names = "default";
316	pinctrl-0 = <&pinctrl_usbotg2>;
317	srp-disable;
318	hnp-disable;
319	adp-disable;
320	power-active-high;
321	disable-over-current;
322	status = "okay";
323};
324
325&usdhc1 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&pinctrl_usdhc1>;
328	bus-width = <8>;
329	no-sd;
330	no-sdio;
331	non-removable;
332	status = "okay";
333};
334
335&usdhc2 {
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
338	bus-width = <4>;
339	vmmc-supply = <&reg_usdhc2_vmmc>;
340	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
341	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
342	status = "okay";
343};
344
345&iomuxc {
346	pinctrl-names = "default";
347	pinctrl-0 = <&pinctrl_hog>;
348
349	pinctrl_hog: hoggrp {
350		fsl,pins = <
351			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
352			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
353			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
354			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
355		>;
356	};
357
358	pinctrl_usbotg1: usbotg1grp {
359		fsl,pins = <
360			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
361		>;
362	};
363
364	pinctrl_usbotg2: usbotg2grp {
365		fsl,pins = <
366			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
367		>;
368	};
369
370	pinctrl_eqos: eqosgrp {
371		fsl,pins = <
372			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
373			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
374			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
375			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
376			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
377			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
378			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
379			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
380			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
381			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
382			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
383			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
384			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
385			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
386		>;
387	};
388
389	pinctrl_fec1: fec1grp {
390		fsl,pins = <
391			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
392			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
393			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
394			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
395			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
396			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
397			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
398			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
399			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
400			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
401			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
402			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
403			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
404			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
405			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
406			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
407		>;
408	};
409
410	pinctrl_lpspi3: lpspi3grp {
411		fsl,pins = <
412			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
413			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
414			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
415			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
416		>;
417	};
418
419	pinctrl_i2c2: i2c2grp {
420		fsl,pins = <
421			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
422			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
423		>;
424	};
425
426	pinctrl_cm40_lpuart: cm40lpuartgrp {
427		fsl,pins = <
428			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
429			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
430		>;
431	};
432
433	pinctrl_i2c3: i2c3grp {
434		fsl,pins = <
435			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
436			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
437		>;
438	};
439
440	pinctrl_lpuart0: lpuart0grp {
441		fsl,pins = <
442			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
443			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
444		>;
445	};
446
447	pinctrl_usdhc1: usdhc1grp {
448		fsl,pins = <
449			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
450			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
451			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
452			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
453			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
454			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
455			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
456			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
457			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
458			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
459			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
460		>;
461	};
462
463	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
464		fsl,pins = <
465			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
466			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
467			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
468		>;
469	};
470
471	pinctrl_usdhc2: usdhc2grp {
472		fsl,pins = <
473			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
474			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
475			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
476			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
477			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
478			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
479			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
480		>;
481	};
482};
483