1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11	model = "Freescale i.MX8DXL EVK";
12	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14	aliases {
15		i2c2 = &i2c2;
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc2;
18		serial0 = &lpuart0;
19	};
20
21	chosen {
22		stdout-path = &lpuart0;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x00000000 0x80000000 0 0x40000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		/*
36		 * Memory reserved for optee usage. Please do not use.
37		 * This will be automatically added to dtb if OP-TEE is installed.
38		 * optee@96000000 {
39		 *     reg = <0 0x96000000 0 0x2000000>;
40		 *     no-map;
41		 * };
42		 */
43
44		/* global autoconfigured region for contiguous allocations */
45		linux,cma {
46			compatible = "shared-dma-pool";
47			reusable;
48			size = <0 0x14000000>;
49			alloc-ranges = <0 0x98000000 0 0x14000000>;
50			linux,cma-default;
51		};
52	};
53
54	mux3_en: regulator-0 {
55		compatible = "regulator-fixed";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "mux3_en";
59		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
60		regulator-always-on;
61	};
62
63	reg_fec1_sel: regulator-1 {
64		compatible = "regulator-fixed";
65		regulator-name = "fec1_supply";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
69		regulator-always-on;
70		status = "disabled";
71	};
72
73	reg_fec1_io: regulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "fec1_io_supply";
76		regulator-min-microvolt = <1800000>;
77		regulator-max-microvolt = <1800000>;
78		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		regulator-always-on;
81		status = "disabled";
82	};
83
84	reg_usdhc2_vmmc: regulator-3 {
85		compatible = "regulator-fixed";
86		regulator-name = "SD1_SPWR";
87		regulator-min-microvolt = <3000000>;
88		regulator-max-microvolt = <3000000>;
89		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
90		enable-active-high;
91		off-on-delay-us = <3480>;
92	};
93
94	reg_vref_1v8: regulator-adc-vref {
95		compatible = "regulator-fixed";
96		regulator-name = "vref_1v8";
97		regulator-min-microvolt = <1800000>;
98		regulator-max-microvolt = <1800000>;
99	};
100
101	mii_select: regulator-4 {
102		compatible = "regulator-fixed";
103		regulator-name = "mii-select";
104		regulator-min-microvolt = <3300000>;
105		regulator-max-microvolt = <3300000>;
106		gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
107		enable-active-high;
108		regulator-always-on;
109	};
110};
111
112&adc0 {
113	vref-supply = <&reg_vref_1v8>;
114	status = "okay";
115};
116
117&eqos {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_eqos>;
120	phy-mode = "rgmii-id";
121	phy-handle = <&ethphy0>;
122	nvmem-cells = <&fec_mac1>;
123	nvmem-cell-names = "mac-address";
124	snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
125	snps,reset-delays-us = <10 20 200000>;
126	status = "okay";
127
128	mdio {
129		compatible = "snps,dwmac-mdio";
130		#address-cells = <1>;
131		#size-cells = <0>;
132
133		ethphy0: ethernet-phy@0 {
134			compatible = "ethernet-phy-ieee802.3-c22";
135			reg = <0>;
136			eee-broken-1000t;
137			qca,disable-smarteee;
138			qca,disable-hibernation-mode;
139			vddio-supply = <&vddio0>;
140
141			vddio0: vddio-regulator {
142				regulator-min-microvolt = <1800000>;
143				regulator-max-microvolt = <1800000>;
144			};
145		};
146	};
147};
148
149/*
150 * fec1 shares the some PINs with usdhc2.
151 * by default usdhc2 is enabled in this dts.
152 * Please disable usdhc2 to enable fec1
153 */
154&fec1 {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_fec1>;
157	phy-mode = "rgmii-txid";
158	phy-handle = <&ethphy1>;
159	fsl,magic-packet;
160	rx-internal-delay-ps = <2000>;
161	nvmem-cells = <&fec_mac0>;
162	nvmem-cell-names = "mac-address";
163	status = "disabled";
164
165	mdio {
166		#address-cells = <1>;
167		#size-cells = <0>;
168
169		ethphy1: ethernet-phy@1 {
170			compatible = "ethernet-phy-ieee802.3-c22";
171			reg = <1>;
172			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
173			reset-assert-us = <10000>;
174			qca,disable-smarteee;
175			vddio-supply = <&vddio1>;
176
177			vddio1: vddio-regulator {
178				regulator-min-microvolt = <1800000>;
179				regulator-max-microvolt = <1800000>;
180			};
181		};
182	};
183};
184
185&flexspi0 {
186	pinctrl-names = "default";
187	pinctrl-0 = <&pinctrl_flexspi0>;
188	nxp,fspi-dll-slvdly = <4>;
189	status = "okay";
190
191	mt35xu512aba0: flash@0 {
192		reg = <0>;
193		#address-cells = <1>;
194		#size-cells = <1>;
195		compatible = "jedec,spi-nor";
196		spi-max-frequency = <133000000>;
197		spi-tx-bus-width = <8>;
198		spi-rx-bus-width = <8>;
199	};
200};
201
202&i2c2 {
203	#address-cells = <1>;
204	#size-cells = <0>;
205	clock-frequency = <100000>;
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_i2c2>;
208	status = "okay";
209
210	pca6416_1: gpio@20 {
211		compatible = "ti,tca6416";
212		reg = <0x20>;
213		gpio-controller;
214		#gpio-cells = <2>;
215	};
216
217	pca6416_2: gpio@21 {
218		compatible = "ti,tca6416";
219		reg = <0x21>;
220		gpio-controller;
221		#gpio-cells = <2>;
222	};
223
224	pca9548_1: i2c-mux@70 {
225		compatible = "nxp,pca9548";
226		#address-cells = <1>;
227		#size-cells = <0>;
228		reg = <0x70>;
229
230		i2c@0 {
231			#address-cells = <1>;
232			#size-cells = <0>;
233			reg = <0x0>;
234
235			max7322: gpio@68 {
236				compatible = "maxim,max7322";
237				reg = <0x68>;
238				gpio-controller;
239				#gpio-cells = <2>;
240				status = "disabled";
241			};
242		};
243
244		i2c@4 {
245			#address-cells = <1>;
246			#size-cells = <0>;
247			reg = <0x4>;
248		};
249
250		i2c@5 {
251			#address-cells = <1>;
252			#size-cells = <0>;
253			reg = <0x5>;
254		};
255
256		i2c@6 {
257			#address-cells = <1>;
258			#size-cells = <0>;
259			reg = <0x6>;
260		};
261	};
262};
263
264&lpuart0 {
265	pinctrl-names = "default";
266	pinctrl-0 = <&pinctrl_lpuart0>;
267	status = "okay";
268};
269
270&lsio_gpio4 {
271	status = "okay";
272};
273
274&lsio_gpio5 {
275	status = "okay";
276};
277
278&thermal_zones {
279	pmic-thermal0 {
280		polling-delay-passive = <250>;
281		polling-delay = <2000>;
282		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
283
284		trips {
285			pmic_alert0: trip0 {
286				temperature = <110000>;
287				hysteresis = <2000>;
288				type = "passive";
289			};
290
291			pmic_crit0: trip1 {
292				temperature = <125000>;
293				hysteresis = <2000>;
294				type = "critical";
295			};
296		};
297
298		cooling-maps {
299			map0 {
300				trip = <&pmic_alert0>;
301				cooling-device =
302					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
303					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
304			};
305		};
306	};
307};
308
309&usbphy1 {
310	/* USB eye diagram tests result */
311	fsl,tx-d-cal = <114>;
312	status = "okay";
313};
314
315&usbotg1 {
316	pinctrl-names = "default";
317	pinctrl-0 = <&pinctrl_usbotg1>;
318	srp-disable;
319	hnp-disable;
320	adp-disable;
321	power-active-high;
322	disable-over-current;
323	status = "okay";
324};
325
326&usbphy2 {
327	/* USB eye diagram tests result */
328	fsl,tx-d-cal = <111>;
329	status = "okay";
330};
331
332&usbotg2 {
333	pinctrl-names = "default";
334	pinctrl-0 = <&pinctrl_usbotg2>;
335	srp-disable;
336	hnp-disable;
337	adp-disable;
338	power-active-high;
339	disable-over-current;
340	status = "okay";
341};
342
343&usdhc1 {
344	pinctrl-names = "default";
345	pinctrl-0 = <&pinctrl_usdhc1>;
346	bus-width = <8>;
347	no-sd;
348	no-sdio;
349	non-removable;
350	status = "okay";
351};
352
353&usdhc2 {
354	pinctrl-names = "default";
355	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
356	bus-width = <4>;
357	vmmc-supply = <&reg_usdhc2_vmmc>;
358	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
359	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
360	status = "okay";
361};
362
363&lpspi3 {
364	fsl,spi-num-chipselects = <1>;
365	fsl,spi-only-use-cs1-sel;
366	pinctrl-names = "default";
367	pinctrl-0 = <&pinctrl_lpspi3>;
368	pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
369	status = "okay";
370
371	spidev0: spi@0 {
372		reg = <0>;
373		compatible = "rohm,dh2228fv";
374		spi-max-frequency = <30000000>;
375	};
376};
377
378&iomuxc {
379	pinctrl-names = "default";
380	pinctrl-0 = <&pinctrl_hog>;
381
382	pinctrl_hog: hoggrp {
383		fsl,pins = <
384			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
385			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
386			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
387			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
388		>;
389	};
390
391	pinctrl_usbotg1: usbotg1grp {
392		fsl,pins = <
393			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
394		>;
395	};
396
397	pinctrl_usbotg2: usbotg2grp {
398		fsl,pins = <
399			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
400		>;
401	};
402
403	pinctrl_eqos: eqosgrp {
404		fsl,pins = <
405			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
406			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
407			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
408			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
409			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
410			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
411			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
412			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
413			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
414			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
415			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
416			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
417			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
418			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
419		>;
420	};
421
422	pinctrl_flexspi0: flexspi0grp {
423		fsl,pins = <
424			IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
425			IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
426			IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
427			IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
428			IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
429			IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
430			IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
431			IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
432			IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
433			IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
434			IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
435			IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
436			IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
437			IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
438		>;
439	};
440
441	pinctrl_fec1: fec1grp {
442		fsl,pins = <
443			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
444			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
445			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
446			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
447			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
448			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
449			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
450			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
451			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
452			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
453			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
454			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
455			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
456			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
457			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
458			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
459		>;
460	};
461
462	pinctrl_lpspi3: lpspi3grp {
463		fsl,pins = <
464			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
465			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
466			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
467			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
468		>;
469	};
470
471	pinctrl_i2c2: i2c2grp {
472		fsl,pins = <
473			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
474			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
475		>;
476	};
477
478	pinctrl_cm40_lpuart: cm40lpuartgrp {
479		fsl,pins = <
480			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
481			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
482		>;
483	};
484
485	pinctrl_i2c3: i2c3grp {
486		fsl,pins = <
487			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
488			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
489		>;
490	};
491
492	pinctrl_lpuart0: lpuart0grp {
493		fsl,pins = <
494			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
495			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
496		>;
497	};
498
499	pinctrl_usdhc1: usdhc1grp {
500		fsl,pins = <
501			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
502			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
503			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
504			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
505			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
506			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
507			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
508			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
509			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
510			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
511			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
512		>;
513	};
514
515	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
516		fsl,pins = <
517			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
518			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
519			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
520		>;
521	};
522
523	pinctrl_usdhc2: usdhc2grp {
524		fsl,pins = <
525			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
526			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
527			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
528			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
529			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
530			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
531			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
532		>;
533	};
534};
535