1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11	model = "Freescale i.MX8DXL EVK";
12	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14	aliases {
15		i2c2 = &i2c2;
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc2;
18		serial0 = &lpuart0;
19	};
20
21	chosen {
22		stdout-path = &lpuart0;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x00000000 0x80000000 0 0x40000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		/*
36		 * Memory reserved for optee usage. Please do not use.
37		 * This will be automatically added to dtb if OP-TEE is installed.
38		 * optee@96000000 {
39		 *     reg = <0 0x96000000 0 0x2000000>;
40		 *     no-map;
41		 * };
42		 */
43
44		/* global autoconfigured region for contiguous allocations */
45		linux,cma {
46			compatible = "shared-dma-pool";
47			reusable;
48			size = <0 0x14000000>;
49			alloc-ranges = <0 0x98000000 0 0x14000000>;
50			linux,cma-default;
51		};
52	};
53
54	mux3_en: regulator-0 {
55		compatible = "regulator-fixed";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "mux3_en";
59		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
60		regulator-always-on;
61	};
62
63	reg_fec1_sel: regulator-1 {
64		compatible = "regulator-fixed";
65		regulator-name = "fec1_supply";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
69		regulator-always-on;
70		status = "disabled";
71	};
72
73	reg_fec1_io: regulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "fec1_io_supply";
76		regulator-min-microvolt = <1800000>;
77		regulator-max-microvolt = <1800000>;
78		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		regulator-always-on;
81		status = "disabled";
82	};
83
84	reg_usdhc2_vmmc: regulator-3 {
85		compatible = "regulator-fixed";
86		regulator-name = "SD1_SPWR";
87		regulator-min-microvolt = <3000000>;
88		regulator-max-microvolt = <3000000>;
89		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
90		enable-active-high;
91		off-on-delay-us = <3480>;
92	};
93
94	reg_vref_1v8: regulator-adc-vref {
95		compatible = "regulator-fixed";
96		regulator-name = "vref_1v8";
97		regulator-min-microvolt = <1800000>;
98		regulator-max-microvolt = <1800000>;
99	};
100
101	mii_select: regulator-4 {
102		compatible = "regulator-fixed";
103		regulator-name = "mii-select";
104		regulator-min-microvolt = <3300000>;
105		regulator-max-microvolt = <3300000>;
106		gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
107		enable-active-high;
108		regulator-always-on;
109	};
110};
111
112&adc0 {
113	vref-supply = <&reg_vref_1v8>;
114	status = "okay";
115};
116
117&eqos {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_eqos>;
120	phy-mode = "rgmii-id";
121	phy-handle = <&ethphy0>;
122	nvmem-cells = <&fec_mac1>;
123	nvmem-cell-names = "mac-address";
124	snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
125	snps,reset-delays-us = <10 20 200000>;
126	status = "okay";
127
128	mdio {
129		compatible = "snps,dwmac-mdio";
130		#address-cells = <1>;
131		#size-cells = <0>;
132
133		ethphy0: ethernet-phy@0 {
134			compatible = "ethernet-phy-ieee802.3-c22";
135			reg = <0>;
136			eee-broken-1000t;
137			qca,disable-smarteee;
138			vddio-supply = <&vddio0>;
139
140			vddio0: vddio-regulator {
141				regulator-min-microvolt = <1800000>;
142				regulator-max-microvolt = <1800000>;
143			};
144		};
145	};
146};
147
148/*
149 * fec1 shares the some PINs with usdhc2.
150 * by default usdhc2 is enabled in this dts.
151 * Please disable usdhc2 to enable fec1
152 */
153&fec1 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_fec1>;
156	phy-mode = "rgmii-txid";
157	phy-handle = <&ethphy1>;
158	fsl,magic-packet;
159	rx-internal-delay-ps = <2000>;
160	nvmem-cells = <&fec_mac0>;
161	nvmem-cell-names = "mac-address";
162	status = "disabled";
163
164	mdio {
165		#address-cells = <1>;
166		#size-cells = <0>;
167
168		ethphy1: ethernet-phy@1 {
169			compatible = "ethernet-phy-ieee802.3-c22";
170			reg = <1>;
171			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
172			reset-assert-us = <10000>;
173			qca,disable-smarteee;
174			vddio-supply = <&vddio1>;
175
176			vddio1: vddio-regulator {
177				regulator-min-microvolt = <1800000>;
178				regulator-max-microvolt = <1800000>;
179			};
180		};
181	};
182};
183
184&flexspi0 {
185	pinctrl-names = "default";
186	pinctrl-0 = <&pinctrl_flexspi0>;
187	nxp,fspi-dll-slvdly = <4>;
188	status = "okay";
189
190	mt35xu512aba0: flash@0 {
191		reg = <0>;
192		#address-cells = <1>;
193		#size-cells = <1>;
194		compatible = "jedec,spi-nor";
195		spi-max-frequency = <133000000>;
196		spi-tx-bus-width = <8>;
197		spi-rx-bus-width = <8>;
198	};
199};
200
201&i2c2 {
202	#address-cells = <1>;
203	#size-cells = <0>;
204	clock-frequency = <100000>;
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_i2c2>;
207	status = "okay";
208
209	pca6416_1: gpio@20 {
210		compatible = "ti,tca6416";
211		reg = <0x20>;
212		gpio-controller;
213		#gpio-cells = <2>;
214	};
215
216	pca6416_2: gpio@21 {
217		compatible = "ti,tca6416";
218		reg = <0x21>;
219		gpio-controller;
220		#gpio-cells = <2>;
221	};
222
223	pca9548_1: i2c-mux@70 {
224		compatible = "nxp,pca9548";
225		#address-cells = <1>;
226		#size-cells = <0>;
227		reg = <0x70>;
228
229		i2c@0 {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			reg = <0x0>;
233
234			max7322: gpio@68 {
235				compatible = "maxim,max7322";
236				reg = <0x68>;
237				gpio-controller;
238				#gpio-cells = <2>;
239				status = "disabled";
240			};
241		};
242
243		i2c@4 {
244			#address-cells = <1>;
245			#size-cells = <0>;
246			reg = <0x4>;
247		};
248
249		i2c@5 {
250			#address-cells = <1>;
251			#size-cells = <0>;
252			reg = <0x5>;
253		};
254
255		i2c@6 {
256			#address-cells = <1>;
257			#size-cells = <0>;
258			reg = <0x6>;
259		};
260	};
261};
262
263&lpuart0 {
264	pinctrl-names = "default";
265	pinctrl-0 = <&pinctrl_lpuart0>;
266	status = "okay";
267};
268
269&lsio_gpio4 {
270	status = "okay";
271};
272
273&lsio_gpio5 {
274	status = "okay";
275};
276
277&thermal_zones {
278	pmic-thermal0 {
279		polling-delay-passive = <250>;
280		polling-delay = <2000>;
281		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
282
283		trips {
284			pmic_alert0: trip0 {
285				temperature = <110000>;
286				hysteresis = <2000>;
287				type = "passive";
288			};
289
290			pmic_crit0: trip1 {
291				temperature = <125000>;
292				hysteresis = <2000>;
293				type = "critical";
294			};
295		};
296
297		cooling-maps {
298			map0 {
299				trip = <&pmic_alert0>;
300				cooling-device =
301					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
302					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
303			};
304		};
305	};
306};
307
308&usbphy1 {
309	/* USB eye diagram tests result */
310	fsl,tx-d-cal = <114>;
311	status = "okay";
312};
313
314&usbotg1 {
315	pinctrl-names = "default";
316	pinctrl-0 = <&pinctrl_usbotg1>;
317	srp-disable;
318	hnp-disable;
319	adp-disable;
320	power-active-high;
321	disable-over-current;
322	status = "okay";
323};
324
325&usbphy2 {
326	/* USB eye diagram tests result */
327	fsl,tx-d-cal = <111>;
328	status = "okay";
329};
330
331&usbotg2 {
332	pinctrl-names = "default";
333	pinctrl-0 = <&pinctrl_usbotg2>;
334	srp-disable;
335	hnp-disable;
336	adp-disable;
337	power-active-high;
338	disable-over-current;
339	status = "okay";
340};
341
342&usdhc1 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_usdhc1>;
345	bus-width = <8>;
346	no-sd;
347	no-sdio;
348	non-removable;
349	status = "okay";
350};
351
352&usdhc2 {
353	pinctrl-names = "default";
354	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
355	bus-width = <4>;
356	vmmc-supply = <&reg_usdhc2_vmmc>;
357	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
358	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
359	status = "okay";
360};
361
362&lpspi3 {
363	fsl,spi-num-chipselects = <1>;
364	fsl,spi-only-use-cs1-sel;
365	pinctrl-names = "default";
366	pinctrl-0 = <&pinctrl_lpspi3>;
367	pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
368	status = "okay";
369
370	spidev0: spi@0 {
371		reg = <0>;
372		compatible = "rohm,dh2228fv";
373		spi-max-frequency = <30000000>;
374	};
375};
376
377&iomuxc {
378	pinctrl-names = "default";
379	pinctrl-0 = <&pinctrl_hog>;
380
381	pinctrl_hog: hoggrp {
382		fsl,pins = <
383			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
384			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
385			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
386			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
387		>;
388	};
389
390	pinctrl_usbotg1: usbotg1grp {
391		fsl,pins = <
392			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
393		>;
394	};
395
396	pinctrl_usbotg2: usbotg2grp {
397		fsl,pins = <
398			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
399		>;
400	};
401
402	pinctrl_eqos: eqosgrp {
403		fsl,pins = <
404			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
405			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
406			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
407			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
408			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
409			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
410			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
411			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
412			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
413			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
414			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
415			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
416			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
417			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
418		>;
419	};
420
421	pinctrl_flexspi0: flexspi0grp {
422		fsl,pins = <
423			IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
424			IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
425			IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
426			IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
427			IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
428			IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
429			IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
430			IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
431			IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
432			IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
433			IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
434			IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
435			IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
436			IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
437		>;
438	};
439
440	pinctrl_fec1: fec1grp {
441		fsl,pins = <
442			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
443			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
444			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
445			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
446			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
447			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
448			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
449			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
450			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
451			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
452			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
453			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
454			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
455			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
456			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
457			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
458		>;
459	};
460
461	pinctrl_lpspi3: lpspi3grp {
462		fsl,pins = <
463			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
464			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
465			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
466			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
467		>;
468	};
469
470	pinctrl_i2c2: i2c2grp {
471		fsl,pins = <
472			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
473			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
474		>;
475	};
476
477	pinctrl_cm40_lpuart: cm40lpuartgrp {
478		fsl,pins = <
479			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
480			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
481		>;
482	};
483
484	pinctrl_i2c3: i2c3grp {
485		fsl,pins = <
486			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
487			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
488		>;
489	};
490
491	pinctrl_lpuart0: lpuart0grp {
492		fsl,pins = <
493			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
494			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
495		>;
496	};
497
498	pinctrl_usdhc1: usdhc1grp {
499		fsl,pins = <
500			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
501			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
502			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
503			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
504			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
505			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
506			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
507			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
508			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
509			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
510			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
511		>;
512	};
513
514	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
515		fsl,pins = <
516			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
517			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
518			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
519		>;
520	};
521
522	pinctrl_usdhc2: usdhc2grp {
523		fsl,pins = <
524			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
525			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
526			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
527			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
528			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
529			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
530			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
531		>;
532	};
533};
534