1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11	model = "Freescale i.MX8DXL EVK";
12	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14	aliases {
15		i2c2 = &i2c2;
16		mmc0 = &usdhc1;
17		mmc1 = &usdhc2;
18		serial0 = &lpuart0;
19	};
20
21	chosen {
22		stdout-path = &lpuart0;
23	};
24
25	memory@80000000 {
26		device_type = "memory";
27		reg = <0x00000000 0x80000000 0 0x40000000>;
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		/*
36		 * Memory reserved for optee usage. Please do not use.
37		 * This will be automatically added to dtb if OP-TEE is installed.
38		 * optee@96000000 {
39		 *     reg = <0 0x96000000 0 0x2000000>;
40		 *     no-map;
41		 * };
42		 */
43
44		/* global autoconfigured region for contiguous allocations */
45		linux,cma {
46			compatible = "shared-dma-pool";
47			reusable;
48			size = <0 0x14000000>;
49			alloc-ranges = <0 0x98000000 0 0x14000000>;
50			linux,cma-default;
51		};
52	};
53
54	mux3_en: regulator-0 {
55		compatible = "regulator-fixed";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-name = "mux3_en";
59		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
60		regulator-always-on;
61	};
62
63	reg_fec1_sel: regulator-1 {
64		compatible = "regulator-fixed";
65		regulator-name = "fec1_supply";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
69		regulator-always-on;
70		status = "disabled";
71	};
72
73	reg_fec1_io: regulator-2 {
74		compatible = "regulator-fixed";
75		regulator-name = "fec1_io_supply";
76		regulator-min-microvolt = <1800000>;
77		regulator-max-microvolt = <1800000>;
78		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		regulator-always-on;
81		status = "disabled";
82	};
83
84	reg_usdhc2_vmmc: regulator-3 {
85		compatible = "regulator-fixed";
86		regulator-name = "SD1_SPWR";
87		regulator-min-microvolt = <3000000>;
88		regulator-max-microvolt = <3000000>;
89		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
90		enable-active-high;
91		off-on-delay-us = <3480>;
92	};
93
94	mii_select: regulator-4 {
95		compatible = "regulator-fixed";
96		regulator-name = "mii-select";
97		regulator-min-microvolt = <3300000>;
98		regulator-max-microvolt = <3300000>;
99		gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
100		enable-active-high;
101		regulator-always-on;
102	};
103};
104
105&eqos {
106	pinctrl-names = "default";
107	pinctrl-0 = <&pinctrl_eqos>;
108	phy-mode = "rgmii-id";
109	phy-handle = <&ethphy0>;
110	nvmem-cells = <&fec_mac1>;
111	nvmem-cell-names = "mac-address";
112	snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
113	snps,reset-delays-us = <10 20 200000>;
114	status = "okay";
115
116	mdio {
117		compatible = "snps,dwmac-mdio";
118		#address-cells = <1>;
119		#size-cells = <0>;
120
121		ethphy0: ethernet-phy@0 {
122			compatible = "ethernet-phy-ieee802.3-c22";
123			reg = <0>;
124			eee-broken-1000t;
125			qca,disable-smarteee;
126			vddio-supply = <&vddio0>;
127
128			vddio0: vddio-regulator {
129				regulator-min-microvolt = <1800000>;
130				regulator-max-microvolt = <1800000>;
131			};
132		};
133	};
134};
135
136/*
137 * fec1 shares the some PINs with usdhc2.
138 * by default usdhc2 is enabled in this dts.
139 * Please disable usdhc2 to enable fec1
140 */
141&fec1 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_fec1>;
144	phy-mode = "rgmii-txid";
145	phy-handle = <&ethphy1>;
146	fsl,magic-packet;
147	rx-internal-delay-ps = <2000>;
148	nvmem-cells = <&fec_mac0>;
149	nvmem-cell-names = "mac-address";
150	status = "disabled";
151
152	mdio {
153		#address-cells = <1>;
154		#size-cells = <0>;
155
156		ethphy1: ethernet-phy@1 {
157			compatible = "ethernet-phy-ieee802.3-c22";
158			reg = <1>;
159			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
160			reset-assert-us = <10000>;
161			qca,disable-smarteee;
162			vddio-supply = <&vddio1>;
163
164			vddio1: vddio-regulator {
165				regulator-min-microvolt = <1800000>;
166				regulator-max-microvolt = <1800000>;
167			};
168		};
169	};
170};
171
172&i2c2 {
173	#address-cells = <1>;
174	#size-cells = <0>;
175	clock-frequency = <100000>;
176	pinctrl-names = "default";
177	pinctrl-0 = <&pinctrl_i2c2>;
178	status = "okay";
179
180	pca6416_1: gpio@20 {
181		compatible = "ti,tca6416";
182		reg = <0x20>;
183		gpio-controller;
184		#gpio-cells = <2>;
185	};
186
187	pca6416_2: gpio@21 {
188		compatible = "ti,tca6416";
189		reg = <0x21>;
190		gpio-controller;
191		#gpio-cells = <2>;
192	};
193
194	pca9548_1: i2c-mux@70 {
195		compatible = "nxp,pca9548";
196		#address-cells = <1>;
197		#size-cells = <0>;
198		reg = <0x70>;
199
200		i2c@0 {
201			#address-cells = <1>;
202			#size-cells = <0>;
203			reg = <0x0>;
204
205			max7322: gpio@68 {
206				compatible = "maxim,max7322";
207				reg = <0x68>;
208				gpio-controller;
209				#gpio-cells = <2>;
210				status = "disabled";
211			};
212		};
213
214		i2c@4 {
215			#address-cells = <1>;
216			#size-cells = <0>;
217			reg = <0x4>;
218		};
219
220		i2c@5 {
221			#address-cells = <1>;
222			#size-cells = <0>;
223			reg = <0x5>;
224		};
225
226		i2c@6 {
227			#address-cells = <1>;
228			#size-cells = <0>;
229			reg = <0x6>;
230		};
231	};
232};
233
234&lpuart0 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_lpuart0>;
237	status = "okay";
238};
239
240&lsio_gpio4 {
241	status = "okay";
242};
243
244&lsio_gpio5 {
245	status = "okay";
246};
247
248&thermal_zones {
249	pmic-thermal0 {
250		polling-delay-passive = <250>;
251		polling-delay = <2000>;
252		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
253
254		trips {
255			pmic_alert0: trip0 {
256				temperature = <110000>;
257				hysteresis = <2000>;
258				type = "passive";
259			};
260
261			pmic_crit0: trip1 {
262				temperature = <125000>;
263				hysteresis = <2000>;
264				type = "critical";
265			};
266		};
267
268		cooling-maps {
269			map0 {
270				trip = <&pmic_alert0>;
271				cooling-device =
272					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
273					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
274			};
275		};
276	};
277};
278
279&usbphy1 {
280	/* USB eye diagram tests result */
281	fsl,tx-d-cal = <114>;
282	status = "okay";
283};
284
285&usbotg1 {
286	pinctrl-names = "default";
287	pinctrl-0 = <&pinctrl_usbotg1>;
288	srp-disable;
289	hnp-disable;
290	adp-disable;
291	power-active-high;
292	disable-over-current;
293	status = "okay";
294};
295
296&usbphy2 {
297	/* USB eye diagram tests result */
298	fsl,tx-d-cal = <111>;
299	status = "okay";
300};
301
302&usbotg2 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&pinctrl_usbotg2>;
305	srp-disable;
306	hnp-disable;
307	adp-disable;
308	power-active-high;
309	disable-over-current;
310	status = "okay";
311};
312
313&usdhc1 {
314	pinctrl-names = "default";
315	pinctrl-0 = <&pinctrl_usdhc1>;
316	bus-width = <8>;
317	no-sd;
318	no-sdio;
319	non-removable;
320	status = "okay";
321};
322
323&usdhc2 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
326	bus-width = <4>;
327	vmmc-supply = <&reg_usdhc2_vmmc>;
328	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
329	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
330	status = "okay";
331};
332
333&iomuxc {
334	pinctrl-names = "default";
335	pinctrl-0 = <&pinctrl_hog>;
336
337	pinctrl_hog: hoggrp {
338		fsl,pins = <
339			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
340			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
341			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
342			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
343		>;
344	};
345
346	pinctrl_usbotg1: usbotg1grp {
347		fsl,pins = <
348			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
349		>;
350	};
351
352	pinctrl_usbotg2: usbotg2grp {
353		fsl,pins = <
354			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
355		>;
356	};
357
358	pinctrl_eqos: eqosgrp {
359		fsl,pins = <
360			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
361			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
362			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
363			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
364			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
365			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
366			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
367			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
368			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
369			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
370			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
371			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
372			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
373			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
374		>;
375	};
376
377	pinctrl_fec1: fec1grp {
378		fsl,pins = <
379			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
380			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
381			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
382			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
383			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
384			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
385			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
386			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
387			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
388			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
389			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
390			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
391			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
392			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
393			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
394			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
395		>;
396	};
397
398	pinctrl_lpspi3: lpspi3grp {
399		fsl,pins = <
400			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
401			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
402			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
403			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
404		>;
405	};
406
407	pinctrl_i2c2: i2c2grp {
408		fsl,pins = <
409			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
410			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
411		>;
412	};
413
414	pinctrl_cm40_lpuart: cm40lpuartgrp {
415		fsl,pins = <
416			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
417			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
418		>;
419	};
420
421	pinctrl_i2c3: i2c3grp {
422		fsl,pins = <
423			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
424			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
425		>;
426	};
427
428	pinctrl_lpuart0: lpuart0grp {
429		fsl,pins = <
430			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
431			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
432		>;
433	};
434
435	pinctrl_usdhc1: usdhc1grp {
436		fsl,pins = <
437			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
438			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
439			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
440			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
441			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
442			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
443			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
444			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
445			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
446			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
447			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
448		>;
449	};
450
451	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
452		fsl,pins = <
453			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
454			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
455			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
456		>;
457	};
458
459	pinctrl_usdhc2: usdhc2grp {
460		fsl,pins = <
461			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
462			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
463			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
464			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
465			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
466			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
467			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
468		>;
469	};
470};
471