1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10conn_subsys: bus@5b000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 15 16 conn_axi_clk: clock-conn-axi { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <333333333>; 20 clock-output-names = "conn_axi_clk"; 21 }; 22 23 conn_ahb_clk: clock-conn-ahb { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <166666666>; 27 clock-output-names = "conn_ahb_clk"; 28 }; 29 30 conn_ipg_clk: clock-conn-ipg { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <83333333>; 34 clock-output-names = "conn_ipg_clk"; 35 }; 36 37 usbotg1: usb@5b0d0000 { 38 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; 39 reg = <0x5b0d0000 0x200>; 40 interrupt-parent = <&gic>; 41 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 42 fsl,usbphy = <&usbphy1>; 43 fsl,usbmisc = <&usbmisc1 0>; 44 clocks = <&usb2_lpcg 0>; 45 ahb-burst-config = <0x0>; 46 tx-burst-size-dword = <0x10>; 47 rx-burst-size-dword = <0x10>; 48 power-domains = <&pd IMX_SC_R_USB_0>; 49 status = "disabled"; 50 }; 51 52 usbmisc1: usbmisc@5b0d0200 { 53 #index-cells = <1>; 54 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 55 reg = <0x5b0d0200 0x200>; 56 }; 57 58 usbphy1: usbphy@5b100000 { 59 compatible = "fsl,imx7ulp-usbphy"; 60 reg = <0x5b100000 0x1000>; 61 clocks = <&usb2_lpcg 1>; 62 power-domains = <&pd IMX_SC_R_USB_0_PHY>; 63 status = "disabled"; 64 }; 65 66 usdhc1: mmc@5b010000 { 67 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 68 reg = <0x5b010000 0x10000>; 69 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 70 <&sdhc0_lpcg IMX_LPCG_CLK_0>, 71 <&sdhc0_lpcg IMX_LPCG_CLK_5>; 72 clock-names = "ipg", "ahb", "per"; 73 power-domains = <&pd IMX_SC_R_SDHC_0>; 74 status = "disabled"; 75 }; 76 77 usdhc2: mmc@5b020000 { 78 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 79 reg = <0x5b020000 0x10000>; 80 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 81 <&sdhc1_lpcg IMX_LPCG_CLK_0>, 82 <&sdhc1_lpcg IMX_LPCG_CLK_5>; 83 clock-names = "ipg", "ahb", "per"; 84 power-domains = <&pd IMX_SC_R_SDHC_1>; 85 fsl,tuning-start-tap = <20>; 86 fsl,tuning-step = <2>; 87 status = "disabled"; 88 }; 89 90 usdhc3: mmc@5b030000 { 91 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 92 reg = <0x5b030000 0x10000>; 93 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 94 <&sdhc2_lpcg IMX_LPCG_CLK_0>, 95 <&sdhc2_lpcg IMX_LPCG_CLK_5>; 96 clock-names = "ipg", "ahb", "per"; 97 power-domains = <&pd IMX_SC_R_SDHC_2>; 98 status = "disabled"; 99 }; 100 101 fec1: ethernet@5b040000 { 102 reg = <0x5b040000 0x10000>; 103 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, 108 <&enet0_lpcg IMX_LPCG_CLK_2>, 109 <&enet0_lpcg IMX_LPCG_CLK_3>, 110 <&enet0_lpcg IMX_LPCG_CLK_0>; 111 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 112 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 113 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 114 assigned-clock-rates = <250000000>, <125000000>; 115 fsl,num-tx-queues = <3>; 116 fsl,num-rx-queues = <3>; 117 power-domains = <&pd IMX_SC_R_ENET_0>; 118 status = "disabled"; 119 }; 120 121 fec2: ethernet@5b050000 { 122 reg = <0x5b050000 0x10000>; 123 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, 128 <&enet1_lpcg IMX_LPCG_CLK_2>, 129 <&enet1_lpcg IMX_LPCG_CLK_3>, 130 <&enet1_lpcg IMX_LPCG_CLK_0>; 131 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 132 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 133 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; 134 assigned-clock-rates = <250000000>, <125000000>; 135 fsl,num-tx-queues = <3>; 136 fsl,num-rx-queues = <3>; 137 power-domains = <&pd IMX_SC_R_ENET_1>; 138 status = "disabled"; 139 }; 140 141 usbotg3: usb@5b110000 { 142 compatible = "fsl,imx8qm-usb3"; 143 reg = <0x5b110000 0x10000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges; 147 clocks = <&usb3_lpcg IMX_LPCG_CLK_1>, 148 <&usb3_lpcg IMX_LPCG_CLK_0>, 149 <&usb3_lpcg IMX_LPCG_CLK_7>, 150 <&usb3_lpcg IMX_LPCG_CLK_4>, 151 <&usb3_lpcg IMX_LPCG_CLK_5>; 152 clock-names = "lpm", "bus", "aclk", "ipg", "core"; 153 assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; 154 assigned-clock-rates = <250000000>; 155 power-domains = <&pd IMX_SC_R_USB_2>; 156 status = "disabled"; 157 158 usbotg3_cdns3: usb@5b120000 { 159 compatible = "cdns,usb3"; 160 reg = <0x5b130000 0x10000>, /* memory area for HOST registers */ 161 <0x5b140000 0x10000>, /* memory area for DEVICE registers */ 162 <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */ 163 reg-names = "xhci", "dev", "otg"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 interrupt-parent = <&gic>; 167 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-names = "host", "peripheral", "otg", "wakeup"; 172 phys = <&usb3_phy>; 173 phy-names = "cdns3,usb3-phy"; 174 status = "disabled"; 175 }; 176 }; 177 178 usb3_phy: usb-phy@5b160000 { 179 compatible = "nxp,salvo-phy"; 180 reg = <0x5b160000 0x40000>; 181 clocks = <&usb3_lpcg IMX_LPCG_CLK_6>; 182 clock-names = "salvo_phy_clk"; 183 power-domains = <&pd IMX_SC_R_USB_2_PHY>; 184 #phy-cells = <0>; 185 status = "disabled"; 186 }; 187 188 /* LPCG clocks */ 189 sdhc0_lpcg: clock-controller@5b200000 { 190 compatible = "fsl,imx8qxp-lpcg"; 191 reg = <0x5b200000 0x10000>; 192 #clock-cells = <1>; 193 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, 194 <&conn_ipg_clk>, <&conn_axi_clk>; 195 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 196 <IMX_LPCG_CLK_5>; 197 clock-output-names = "sdhc0_lpcg_per_clk", 198 "sdhc0_lpcg_ipg_clk", 199 "sdhc0_lpcg_ahb_clk"; 200 power-domains = <&pd IMX_SC_R_SDHC_0>; 201 }; 202 203 sdhc1_lpcg: clock-controller@5b210000 { 204 compatible = "fsl,imx8qxp-lpcg"; 205 reg = <0x5b210000 0x10000>; 206 #clock-cells = <1>; 207 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, 208 <&conn_ipg_clk>, <&conn_axi_clk>; 209 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 210 <IMX_LPCG_CLK_5>; 211 clock-output-names = "sdhc1_lpcg_per_clk", 212 "sdhc1_lpcg_ipg_clk", 213 "sdhc1_lpcg_ahb_clk"; 214 power-domains = <&pd IMX_SC_R_SDHC_1>; 215 }; 216 217 sdhc2_lpcg: clock-controller@5b220000 { 218 compatible = "fsl,imx8qxp-lpcg"; 219 reg = <0x5b220000 0x10000>; 220 #clock-cells = <1>; 221 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, 222 <&conn_ipg_clk>, <&conn_axi_clk>; 223 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 224 <IMX_LPCG_CLK_5>; 225 clock-output-names = "sdhc2_lpcg_per_clk", 226 "sdhc2_lpcg_ipg_clk", 227 "sdhc2_lpcg_ahb_clk"; 228 power-domains = <&pd IMX_SC_R_SDHC_2>; 229 }; 230 231 enet0_lpcg: clock-controller@5b230000 { 232 compatible = "fsl,imx8qxp-lpcg"; 233 reg = <0x5b230000 0x10000>; 234 #clock-cells = <1>; 235 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 236 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 237 <&conn_axi_clk>, 238 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 239 <&conn_ipg_clk>, 240 <&conn_ipg_clk>; 241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 242 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 243 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 244 clock-output-names = "enet0_lpcg_timer_clk", 245 "enet0_lpcg_txc_sampling_clk", 246 "enet0_lpcg_ahb_clk", 247 "enet0_lpcg_rgmii_txc_clk", 248 "enet0_lpcg_ipg_clk", 249 "enet0_lpcg_ipg_s_clk"; 250 power-domains = <&pd IMX_SC_R_ENET_0>; 251 }; 252 253 enet1_lpcg: clock-controller@5b240000 { 254 compatible = "fsl,imx8qxp-lpcg"; 255 reg = <0x5b240000 0x10000>; 256 #clock-cells = <1>; 257 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 258 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 259 <&conn_axi_clk>, 260 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, 261 <&conn_ipg_clk>, 262 <&conn_ipg_clk>; 263 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 264 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 265 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 266 clock-output-names = "enet1_lpcg_timer_clk", 267 "enet1_lpcg_txc_sampling_clk", 268 "enet1_lpcg_ahb_clk", 269 "enet1_lpcg_rgmii_txc_clk", 270 "enet1_lpcg_ipg_clk", 271 "enet1_lpcg_ipg_s_clk"; 272 power-domains = <&pd IMX_SC_R_ENET_1>; 273 }; 274 275 usb2_lpcg: clock-controller@5b270000 { 276 compatible = "fsl,imx8qxp-lpcg"; 277 reg = <0x5b270000 0x10000>; 278 #clock-cells = <1>; 279 clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; 280 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 281 clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; 282 power-domains = <&pd IMX_SC_R_USB_0_PHY>; 283 }; 284 285 usb3_lpcg: clock-controller@5b280000 { 286 compatible = "fsl,imx8qxp-lpcg"; 287 reg = <0x5b280000 0x10000>; 288 #clock-cells = <1>; 289 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 290 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 291 <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 292 clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, 293 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, 294 <&conn_ipg_clk>, 295 <&conn_ipg_clk>, 296 <&conn_ipg_clk>, 297 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; 298 clock-output-names = "usb3_app_clk", 299 "usb3_lpm_clk", 300 "usb3_ipg_clk", 301 "usb3_core_pclk", 302 "usb3_phy_clk", 303 "usb3_aclk"; 304 power-domains = <&pd IMX_SC_R_USB_2_PHY>; 305 }; 306}; 307