1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9
10conn_subsys: bus@5b000000 {
11	compatible = "simple-bus";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
15
16	conn_axi_clk: clock-conn-axi {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		clock-frequency = <333333333>;
20		clock-output-names = "conn_axi_clk";
21	};
22
23	conn_ahb_clk: clock-conn-ahb {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		clock-frequency = <166666666>;
27		clock-output-names = "conn_ahb_clk";
28	};
29
30	conn_ipg_clk: clock-conn-ipg {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <83333333>;
34		clock-output-names = "conn_ipg_clk";
35	};
36
37	usbotg1: usb@5b0d0000 {
38		compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
39		reg = <0x5b0d0000 0x200>;
40		interrupt-parent = <&gic>;
41		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
42		fsl,usbphy = <&usbphy1>;
43		fsl,usbmisc = <&usbmisc1 0>;
44		clocks = <&usb2_lpcg 0>;
45		ahb-burst-config = <0x0>;
46		tx-burst-size-dword = <0x10>;
47		rx-burst-size-dword = <0x10>;
48		power-domains = <&pd IMX_SC_R_USB_0>;
49		status = "disabled";
50	};
51
52	usbmisc1: usbmisc@5b0d0200 {
53		#index-cells = <1>;
54		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
55		reg = <0x5b0d0200 0x200>;
56	};
57
58	usbphy1: usbphy@5b100000 {
59		compatible = "fsl,imx7ulp-usbphy";
60		reg = <0x5b100000 0x1000>;
61		clocks = <&usb2_lpcg 1>;
62		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
63		status = "disabled";
64	};
65
66	usdhc1: mmc@5b010000 {
67		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
68		reg = <0x5b010000 0x10000>;
69		clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
70			 <&sdhc0_lpcg IMX_LPCG_CLK_0>,
71			 <&sdhc0_lpcg IMX_LPCG_CLK_5>;
72		clock-names = "ipg", "ahb", "per";
73		power-domains = <&pd IMX_SC_R_SDHC_0>;
74		status = "disabled";
75	};
76
77	usdhc2: mmc@5b020000 {
78		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
79		reg = <0x5b020000 0x10000>;
80		clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
81			 <&sdhc1_lpcg IMX_LPCG_CLK_0>,
82			 <&sdhc1_lpcg IMX_LPCG_CLK_5>;
83		clock-names = "ipg", "ahb", "per";
84		power-domains = <&pd IMX_SC_R_SDHC_1>;
85		fsl,tuning-start-tap = <20>;
86		fsl,tuning-step = <2>;
87		status = "disabled";
88	};
89
90	usdhc3: mmc@5b030000 {
91		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
92		reg = <0x5b030000 0x10000>;
93		clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
94			 <&sdhc2_lpcg IMX_LPCG_CLK_0>,
95			 <&sdhc2_lpcg IMX_LPCG_CLK_5>;
96		clock-names = "ipg", "ahb", "per";
97		power-domains = <&pd IMX_SC_R_SDHC_2>;
98		status = "disabled";
99	};
100
101	fec1: ethernet@5b040000 {
102		reg = <0x5b040000 0x10000>;
103		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
104			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
105			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
107		clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
108			 <&enet0_lpcg IMX_LPCG_CLK_2>,
109			 <&enet0_lpcg IMX_LPCG_CLK_3>,
110			 <&enet0_lpcg IMX_LPCG_CLK_0>;
111		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
112		assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
113				  <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
114		assigned-clock-rates = <250000000>, <125000000>;
115		fsl,num-tx-queues = <3>;
116		fsl,num-rx-queues = <3>;
117		power-domains = <&pd IMX_SC_R_ENET_0>;
118		status = "disabled";
119	};
120
121	fec2: ethernet@5b050000 {
122		reg = <0x5b050000 0x10000>;
123		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
124				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
125				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
126				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
127		clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
128			 <&enet1_lpcg IMX_LPCG_CLK_2>,
129			 <&enet1_lpcg IMX_LPCG_CLK_3>,
130			 <&enet1_lpcg IMX_LPCG_CLK_0>;
131		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
132		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
133				  <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
134		assigned-clock-rates = <250000000>, <125000000>;
135		fsl,num-tx-queues = <3>;
136		fsl,num-rx-queues = <3>;
137		power-domains = <&pd IMX_SC_R_ENET_1>;
138		status = "disabled";
139	};
140
141	usbotg3: usb@5b110000 {
142		compatible = "fsl,imx8qm-usb3";
143		reg = <0x5b110000 0x10000>;
144		#address-cells = <1>;
145		#size-cells = <1>;
146		ranges;
147		clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
148			 <&usb3_lpcg IMX_LPCG_CLK_0>,
149			 <&usb3_lpcg IMX_LPCG_CLK_7>,
150			 <&usb3_lpcg IMX_LPCG_CLK_4>,
151			 <&usb3_lpcg IMX_LPCG_CLK_5>;
152		clock-names = "lpm", "bus", "aclk", "ipg", "core";
153		assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
154		assigned-clock-rates = <250000000>;
155		power-domains = <&pd IMX_SC_R_USB_2>;
156		status = "disabled";
157
158		usbotg3_cdns3: usb@5b120000 {
159			compatible = "cdns,usb3";
160			reg = <0x5b120000 0x10000>,   /* memory area for OTG/DRD registers */
161			      <0x5b130000 0x10000>,   /* memory area for HOST registers */
162			      <0x5b140000 0x10000>;   /* memory area for DEVICE registers */
163			reg-names = "otg", "xhci", "dev";
164			interrupt-parent = <&gic>;
165			interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
166				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
167				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
168				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
169			interrupt-names = "host", "peripheral", "otg", "wakeup";
170			phys = <&usb3_phy>;
171			phy-names = "cdns3,usb3-phy";
172			cdns,on-chip-buff-size = /bits/ 16 <18>;
173			status = "disabled";
174		};
175	};
176
177	usb3_phy: usb-phy@5b160000 {
178		compatible = "nxp,salvo-phy";
179		reg = <0x5b160000 0x40000>;
180		clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
181		clock-names = "salvo_phy_clk";
182		power-domains = <&pd IMX_SC_R_USB_2_PHY>;
183		#phy-cells = <0>;
184		status = "disabled";
185	};
186
187	/* LPCG clocks */
188	sdhc0_lpcg: clock-controller@5b200000 {
189		compatible = "fsl,imx8qxp-lpcg";
190		reg = <0x5b200000 0x10000>;
191		#clock-cells = <1>;
192		clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
193			 <&conn_ipg_clk>, <&conn_axi_clk>;
194		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
195				<IMX_LPCG_CLK_5>;
196		clock-output-names = "sdhc0_lpcg_per_clk",
197				     "sdhc0_lpcg_ipg_clk",
198				     "sdhc0_lpcg_ahb_clk";
199		power-domains = <&pd IMX_SC_R_SDHC_0>;
200	};
201
202	sdhc1_lpcg: clock-controller@5b210000 {
203		compatible = "fsl,imx8qxp-lpcg";
204		reg = <0x5b210000 0x10000>;
205		#clock-cells = <1>;
206		clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
207			 <&conn_ipg_clk>, <&conn_axi_clk>;
208		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
209				<IMX_LPCG_CLK_5>;
210		clock-output-names = "sdhc1_lpcg_per_clk",
211				     "sdhc1_lpcg_ipg_clk",
212				     "sdhc1_lpcg_ahb_clk";
213		power-domains = <&pd IMX_SC_R_SDHC_1>;
214	};
215
216	sdhc2_lpcg: clock-controller@5b220000 {
217		compatible = "fsl,imx8qxp-lpcg";
218		reg = <0x5b220000 0x10000>;
219		#clock-cells = <1>;
220		clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
221			 <&conn_ipg_clk>, <&conn_axi_clk>;
222		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
223				<IMX_LPCG_CLK_5>;
224		clock-output-names = "sdhc2_lpcg_per_clk",
225				     "sdhc2_lpcg_ipg_clk",
226				     "sdhc2_lpcg_ahb_clk";
227		power-domains = <&pd IMX_SC_R_SDHC_2>;
228	};
229
230	enet0_lpcg: clock-controller@5b230000 {
231		compatible = "fsl,imx8qxp-lpcg";
232		reg = <0x5b230000 0x10000>;
233		#clock-cells = <1>;
234		clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
235			 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
236			 <&conn_axi_clk>,
237			 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
238			 <&conn_ipg_clk>,
239			 <&conn_ipg_clk>;
240		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
241				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
242				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
243		clock-output-names = "enet0_lpcg_timer_clk",
244				     "enet0_lpcg_txc_sampling_clk",
245				     "enet0_lpcg_ahb_clk",
246				     "enet0_lpcg_rgmii_txc_clk",
247				     "enet0_lpcg_ipg_clk",
248				     "enet0_lpcg_ipg_s_clk";
249		power-domains = <&pd IMX_SC_R_ENET_0>;
250	};
251
252	enet1_lpcg: clock-controller@5b240000 {
253		compatible = "fsl,imx8qxp-lpcg";
254		reg = <0x5b240000 0x10000>;
255		#clock-cells = <1>;
256		clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
257			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
258			 <&conn_axi_clk>,
259			 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
260			 <&conn_ipg_clk>,
261			 <&conn_ipg_clk>;
262		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
263				<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
264				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
265		clock-output-names = "enet1_lpcg_timer_clk",
266				     "enet1_lpcg_txc_sampling_clk",
267				     "enet1_lpcg_ahb_clk",
268				     "enet1_lpcg_rgmii_txc_clk",
269				     "enet1_lpcg_ipg_clk",
270				     "enet1_lpcg_ipg_s_clk";
271		power-domains = <&pd IMX_SC_R_ENET_1>;
272	};
273
274	usb2_lpcg: clock-controller@5b270000 {
275		compatible = "fsl,imx8qxp-lpcg";
276		reg = <0x5b270000 0x10000>;
277		#clock-cells = <1>;
278		clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
279		clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
280		clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
281		power-domains = <&pd IMX_SC_R_USB_0_PHY>;
282	};
283
284	usb3_lpcg: clock-controller@5b280000 {
285		compatible = "fsl,imx8qxp-lpcg";
286		reg = <0x5b280000 0x10000>;
287		#clock-cells = <1>;
288		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
289				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
290				<IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
291		clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
292			 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
293			 <&conn_ipg_clk>,
294			 <&conn_ipg_clk>,
295			 <&conn_ipg_clk>,
296			 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
297		clock-output-names = "usb3_app_clk",
298				     "usb3_lpm_clk",
299				     "usb3_ipg_clk",
300				     "usb3_core_pclk",
301				     "usb3_phy_clk",
302				     "usb3_aclk";
303		power-domains = <&pd IMX_SC_R_USB_2_PHY>;
304	};
305};
306