1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7conn_subsys: bus@5b000000 {
8	compatible = "simple-bus";
9	#address-cells = <1>;
10	#size-cells = <1>;
11	ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
12
13	conn_lpcg: clock-controller@5b200000 {
14		reg = <0x5b200000 0xb0000>;
15		#clock-cells = <1>;
16	};
17
18	usdhc1: mmc@5b010000 {
19		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
20		reg = <0x5b010000 0x10000>;
21		clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
22			 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,
23			 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;
24		clock-names = "ipg", "ahb", "per";
25		power-domains = <&pd IMX_SC_R_SDHC_0>;
26		status = "disabled";
27	};
28
29	usdhc2: mmc@5b020000 {
30		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
31		reg = <0x5b020000 0x10000>;
32		clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
33			 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,
34			 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;
35		clock-names = "ipg", "ahb", "per";
36		power-domains = <&pd IMX_SC_R_SDHC_1>;
37		fsl,tuning-start-tap = <20>;
38		fsl,tuning-step= <2>;
39		status = "disabled";
40	};
41
42	usdhc3: mmc@5b030000 {
43		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
44		reg = <0x5b030000 0x10000>;
45		clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
46			 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,
47			 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;
48		clock-names = "ipg", "ahb", "per";
49		power-domains = <&pd IMX_SC_R_SDHC_2>;
50		status = "disabled";
51	};
52
53	fec1: ethernet@5b040000 {
54		reg = <0x5b040000 0x10000>;
55		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
56			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
57			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
58			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
59		clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
60			 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
61			 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
62			 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
63		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
64		fsl,num-tx-queues=<3>;
65		fsl,num-rx-queues=<3>;
66		power-domains = <&pd IMX_SC_R_ENET_0>;
67		status = "disabled";
68	};
69
70	fec2: ethernet@5b050000 {
71		reg = <0x5b050000 0x10000>;
72		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
73				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
74				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
75				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
76		clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
77			 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
78			 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
79			 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
80		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
81		fsl,num-tx-queues=<3>;
82		fsl,num-rx-queues=<3>;
83		power-domains = <&pd IMX_SC_R_ENET_1>;
84		status = "disabled";
85	};
86};
87