10dcd27bdSDong Aisheng// SPDX-License-Identifier: GPL-2.0+ 20dcd27bdSDong Aisheng/* 30dcd27bdSDong Aisheng * Copyright 2018-2019 NXP 40dcd27bdSDong Aisheng * Dong Aisheng <aisheng.dong@nxp.com> 50dcd27bdSDong Aisheng */ 60dcd27bdSDong Aisheng 79de8a226SDong Aisheng#include <dt-bindings/clock/imx8-lpcg.h> 89de8a226SDong Aisheng#include <dt-bindings/firmware/imx/rsrc.h> 99de8a226SDong Aisheng 100dcd27bdSDong Aishengconn_subsys: bus@5b000000 { 110dcd27bdSDong Aisheng compatible = "simple-bus"; 120dcd27bdSDong Aisheng #address-cells = <1>; 130dcd27bdSDong Aisheng #size-cells = <1>; 140dcd27bdSDong Aisheng ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 150dcd27bdSDong Aisheng 169de8a226SDong Aisheng conn_axi_clk: clock-conn-axi { 179de8a226SDong Aisheng compatible = "fixed-clock"; 189de8a226SDong Aisheng #clock-cells = <0>; 199de8a226SDong Aisheng clock-frequency = <333333333>; 209de8a226SDong Aisheng clock-output-names = "conn_axi_clk"; 219de8a226SDong Aisheng }; 229de8a226SDong Aisheng 239de8a226SDong Aisheng conn_ahb_clk: clock-conn-ahb { 249de8a226SDong Aisheng compatible = "fixed-clock"; 259de8a226SDong Aisheng #clock-cells = <0>; 269de8a226SDong Aisheng clock-frequency = <166666666>; 279de8a226SDong Aisheng clock-output-names = "conn_ahb_clk"; 289de8a226SDong Aisheng }; 299de8a226SDong Aisheng 309de8a226SDong Aisheng conn_ipg_clk: clock-conn-ipg { 319de8a226SDong Aisheng compatible = "fixed-clock"; 329de8a226SDong Aisheng #clock-cells = <0>; 339de8a226SDong Aisheng clock-frequency = <83333333>; 349de8a226SDong Aisheng clock-output-names = "conn_ipg_clk"; 350dcd27bdSDong Aisheng }; 360dcd27bdSDong Aisheng 370dcd27bdSDong Aisheng usdhc1: mmc@5b010000 { 380dcd27bdSDong Aisheng interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 390dcd27bdSDong Aisheng reg = <0x5b010000 0x10000>; 4016c4ea75SDong Aisheng clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 4116c4ea75SDong Aisheng <&sdhc0_lpcg IMX_LPCG_CLK_5>, 4216c4ea75SDong Aisheng <&sdhc0_lpcg IMX_LPCG_CLK_0>; 4316c4ea75SDong Aisheng clock-names = "ipg", "per", "ahb"; 440dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 450dcd27bdSDong Aisheng status = "disabled"; 460dcd27bdSDong Aisheng }; 470dcd27bdSDong Aisheng 480dcd27bdSDong Aisheng usdhc2: mmc@5b020000 { 490dcd27bdSDong Aisheng interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 500dcd27bdSDong Aisheng reg = <0x5b020000 0x10000>; 5116c4ea75SDong Aisheng clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 5216c4ea75SDong Aisheng <&sdhc1_lpcg IMX_LPCG_CLK_5>, 5316c4ea75SDong Aisheng <&sdhc1_lpcg IMX_LPCG_CLK_0>; 5416c4ea75SDong Aisheng clock-names = "ipg", "per", "ahb"; 550dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_1>; 560dcd27bdSDong Aisheng fsl,tuning-start-tap = <20>; 570dcd27bdSDong Aisheng fsl,tuning-step= <2>; 580dcd27bdSDong Aisheng status = "disabled"; 590dcd27bdSDong Aisheng }; 600dcd27bdSDong Aisheng 610dcd27bdSDong Aisheng usdhc3: mmc@5b030000 { 620dcd27bdSDong Aisheng interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 630dcd27bdSDong Aisheng reg = <0x5b030000 0x10000>; 6416c4ea75SDong Aisheng clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 6516c4ea75SDong Aisheng <&sdhc2_lpcg IMX_LPCG_CLK_5>, 6616c4ea75SDong Aisheng <&sdhc2_lpcg IMX_LPCG_CLK_0>; 6716c4ea75SDong Aisheng clock-names = "ipg", "per", "ahb"; 680dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_2>; 690dcd27bdSDong Aisheng status = "disabled"; 700dcd27bdSDong Aisheng }; 710dcd27bdSDong Aisheng 720dcd27bdSDong Aisheng fec1: ethernet@5b040000 { 730dcd27bdSDong Aisheng reg = <0x5b040000 0x10000>; 740dcd27bdSDong Aisheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 750dcd27bdSDong Aisheng <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 760dcd27bdSDong Aisheng <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 770dcd27bdSDong Aisheng <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 7816c4ea75SDong Aisheng clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, 7916c4ea75SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_2>, 80*dfda1fd1SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_3>, 8116c4ea75SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_0>; 820dcd27bdSDong Aisheng clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 83*dfda1fd1SDong Aisheng assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 84*dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 85*dfda1fd1SDong Aisheng assigned-clock-rates = <250000000>, <125000000>; 860dcd27bdSDong Aisheng fsl,num-tx-queues=<3>; 870dcd27bdSDong Aisheng fsl,num-rx-queues=<3>; 880dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_ENET_0>; 890dcd27bdSDong Aisheng status = "disabled"; 900dcd27bdSDong Aisheng }; 910dcd27bdSDong Aisheng 920dcd27bdSDong Aisheng fec2: ethernet@5b050000 { 930dcd27bdSDong Aisheng reg = <0x5b050000 0x10000>; 940dcd27bdSDong Aisheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 950dcd27bdSDong Aisheng <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 960dcd27bdSDong Aisheng <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 970dcd27bdSDong Aisheng <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 9816c4ea75SDong Aisheng clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, 9916c4ea75SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_2>, 100*dfda1fd1SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_3>, 10116c4ea75SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_0>; 1020dcd27bdSDong Aisheng clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 103*dfda1fd1SDong Aisheng assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 104*dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; 105*dfda1fd1SDong Aisheng assigned-clock-rates = <250000000>, <125000000>; 1060dcd27bdSDong Aisheng fsl,num-tx-queues=<3>; 1070dcd27bdSDong Aisheng fsl,num-rx-queues=<3>; 1080dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_ENET_1>; 1090dcd27bdSDong Aisheng status = "disabled"; 1100dcd27bdSDong Aisheng }; 1119de8a226SDong Aisheng 1129de8a226SDong Aisheng /* LPCG clocks */ 1139de8a226SDong Aisheng sdhc0_lpcg: clock-controller@5b200000 { 11416c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1159de8a226SDong Aisheng reg = <0x5b200000 0x10000>; 1169de8a226SDong Aisheng #clock-cells = <1>; 11726de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, 1189de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1199de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1209de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1219de8a226SDong Aisheng clock-output-names = "sdhc0_lpcg_per_clk", 1229de8a226SDong Aisheng "sdhc0_lpcg_ipg_clk", 1239de8a226SDong Aisheng "sdhc0_lpcg_ahb_clk"; 1249de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 1259de8a226SDong Aisheng }; 1269de8a226SDong Aisheng 1279de8a226SDong Aisheng sdhc1_lpcg: clock-controller@5b210000 { 12816c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1299de8a226SDong Aisheng reg = <0x5b210000 0x10000>; 1309de8a226SDong Aisheng #clock-cells = <1>; 13126de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, 1329de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1339de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1349de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1359de8a226SDong Aisheng clock-output-names = "sdhc1_lpcg_per_clk", 1369de8a226SDong Aisheng "sdhc1_lpcg_ipg_clk", 1379de8a226SDong Aisheng "sdhc1_lpcg_ahb_clk"; 1389de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_1>; 1399de8a226SDong Aisheng }; 1409de8a226SDong Aisheng 1419de8a226SDong Aisheng sdhc2_lpcg: clock-controller@5b220000 { 14216c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1439de8a226SDong Aisheng reg = <0x5b220000 0x10000>; 1449de8a226SDong Aisheng #clock-cells = <1>; 14526de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, 1469de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1479de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1489de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1499de8a226SDong Aisheng clock-output-names = "sdhc2_lpcg_per_clk", 1509de8a226SDong Aisheng "sdhc2_lpcg_ipg_clk", 1519de8a226SDong Aisheng "sdhc2_lpcg_ahb_clk"; 1529de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_2>; 1539de8a226SDong Aisheng }; 1549de8a226SDong Aisheng 1559de8a226SDong Aisheng enet0_lpcg: clock-controller@5b230000 { 15616c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1579de8a226SDong Aisheng reg = <0x5b230000 0x10000>; 1589de8a226SDong Aisheng #clock-cells = <1>; 15926de33a1SDong Aisheng clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 16026de33a1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 161*dfda1fd1SDong Aisheng <&conn_axi_clk>, 162*dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 163*dfda1fd1SDong Aisheng <&conn_ipg_clk>, 164*dfda1fd1SDong Aisheng <&conn_ipg_clk>; 1659de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 166*dfda1fd1SDong Aisheng <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 167*dfda1fd1SDong Aisheng <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 168*dfda1fd1SDong Aisheng clock-output-names = "enet0_lpcg_timer_clk", 169*dfda1fd1SDong Aisheng "enet0_lpcg_txc_sampling_clk", 170*dfda1fd1SDong Aisheng "enet0_lpcg_ahb_clk", 171*dfda1fd1SDong Aisheng "enet0_lpcg_rgmii_txc_clk", 172*dfda1fd1SDong Aisheng "enet0_lpcg_ipg_clk", 173*dfda1fd1SDong Aisheng "enet0_lpcg_ipg_s_clk"; 1749de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_ENET_0>; 1759de8a226SDong Aisheng }; 1769de8a226SDong Aisheng 1779de8a226SDong Aisheng enet1_lpcg: clock-controller@5b240000 { 17816c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1799de8a226SDong Aisheng reg = <0x5b240000 0x10000>; 1809de8a226SDong Aisheng #clock-cells = <1>; 18126de33a1SDong Aisheng clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 18226de33a1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 183*dfda1fd1SDong Aisheng <&conn_axi_clk>, 184*dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, 185*dfda1fd1SDong Aisheng <&conn_ipg_clk>, 186*dfda1fd1SDong Aisheng <&conn_ipg_clk>; 1879de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 188*dfda1fd1SDong Aisheng <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 189*dfda1fd1SDong Aisheng <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 190*dfda1fd1SDong Aisheng clock-output-names = "enet1_lpcg_timer_clk", 191*dfda1fd1SDong Aisheng "enet1_lpcg_txc_sampling_clk", 192*dfda1fd1SDong Aisheng "enet1_lpcg_ahb_clk", 193*dfda1fd1SDong Aisheng "enet1_lpcg_rgmii_txc_clk", 194*dfda1fd1SDong Aisheng "enet1_lpcg_ipg_clk", 195*dfda1fd1SDong Aisheng "enet1_lpcg_ipg_s_clk"; 1969de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_ENET_1>; 1979de8a226SDong Aisheng }; 1980dcd27bdSDong Aisheng}; 199