10dcd27bdSDong Aisheng// SPDX-License-Identifier: GPL-2.0+ 20dcd27bdSDong Aisheng/* 30dcd27bdSDong Aisheng * Copyright 2018-2019 NXP 40dcd27bdSDong Aisheng * Dong Aisheng <aisheng.dong@nxp.com> 50dcd27bdSDong Aisheng */ 60dcd27bdSDong Aisheng 79de8a226SDong Aisheng#include <dt-bindings/clock/imx8-lpcg.h> 89de8a226SDong Aisheng#include <dt-bindings/firmware/imx/rsrc.h> 99de8a226SDong Aisheng 100dcd27bdSDong Aishengconn_subsys: bus@5b000000 { 110dcd27bdSDong Aisheng compatible = "simple-bus"; 120dcd27bdSDong Aisheng #address-cells = <1>; 130dcd27bdSDong Aisheng #size-cells = <1>; 140dcd27bdSDong Aisheng ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 150dcd27bdSDong Aisheng 169de8a226SDong Aisheng conn_axi_clk: clock-conn-axi { 179de8a226SDong Aisheng compatible = "fixed-clock"; 189de8a226SDong Aisheng #clock-cells = <0>; 199de8a226SDong Aisheng clock-frequency = <333333333>; 209de8a226SDong Aisheng clock-output-names = "conn_axi_clk"; 219de8a226SDong Aisheng }; 229de8a226SDong Aisheng 239de8a226SDong Aisheng conn_ahb_clk: clock-conn-ahb { 249de8a226SDong Aisheng compatible = "fixed-clock"; 259de8a226SDong Aisheng #clock-cells = <0>; 269de8a226SDong Aisheng clock-frequency = <166666666>; 279de8a226SDong Aisheng clock-output-names = "conn_ahb_clk"; 289de8a226SDong Aisheng }; 299de8a226SDong Aisheng 309de8a226SDong Aisheng conn_ipg_clk: clock-conn-ipg { 319de8a226SDong Aisheng compatible = "fixed-clock"; 329de8a226SDong Aisheng #clock-cells = <0>; 339de8a226SDong Aisheng clock-frequency = <83333333>; 349de8a226SDong Aisheng clock-output-names = "conn_ipg_clk"; 350dcd27bdSDong Aisheng }; 360dcd27bdSDong Aisheng 378065fc93SFrank Li usbotg1: usb@5b0d0000 { 38276dd9a6SPeng Fan compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; 398065fc93SFrank Li reg = <0x5b0d0000 0x200>; 408065fc93SFrank Li interrupt-parent = <&gic>; 418065fc93SFrank Li interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 428065fc93SFrank Li fsl,usbphy = <&usbphy1>; 438065fc93SFrank Li fsl,usbmisc = <&usbmisc1 0>; 4416c2dd96SFrank Li clocks = <&usb2_lpcg IMX_LPCG_CLK_6>; 458065fc93SFrank Li ahb-burst-config = <0x0>; 468065fc93SFrank Li tx-burst-size-dword = <0x10>; 478065fc93SFrank Li rx-burst-size-dword = <0x10>; 488065fc93SFrank Li power-domains = <&pd IMX_SC_R_USB_0>; 498065fc93SFrank Li status = "disabled"; 508065fc93SFrank Li }; 518065fc93SFrank Li 528065fc93SFrank Li usbmisc1: usbmisc@5b0d0200 { 538065fc93SFrank Li #index-cells = <1>; 54276dd9a6SPeng Fan compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 558065fc93SFrank Li reg = <0x5b0d0200 0x200>; 568065fc93SFrank Li }; 578065fc93SFrank Li 588065fc93SFrank Li usbphy1: usbphy@5b100000 { 598065fc93SFrank Li compatible = "fsl,imx7ulp-usbphy"; 608065fc93SFrank Li reg = <0x5b100000 0x1000>; 6116c2dd96SFrank Li clocks = <&usb2_lpcg IMX_LPCG_CLK_7>; 628065fc93SFrank Li power-domains = <&pd IMX_SC_R_USB_0_PHY>; 638065fc93SFrank Li status = "disabled"; 648065fc93SFrank Li }; 658065fc93SFrank Li 660dcd27bdSDong Aisheng usdhc1: mmc@5b010000 { 670dcd27bdSDong Aisheng interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 680dcd27bdSDong Aisheng reg = <0x5b010000 0x10000>; 6916c4ea75SDong Aisheng clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 70ea16e637SFrank Li <&sdhc0_lpcg IMX_LPCG_CLK_5>, 71ea16e637SFrank Li <&sdhc0_lpcg IMX_LPCG_CLK_0>; 7206acb824SPeng Fan clock-names = "ipg", "ahb", "per"; 730dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 740dcd27bdSDong Aisheng status = "disabled"; 750dcd27bdSDong Aisheng }; 760dcd27bdSDong Aisheng 770dcd27bdSDong Aisheng usdhc2: mmc@5b020000 { 780dcd27bdSDong Aisheng interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 790dcd27bdSDong Aisheng reg = <0x5b020000 0x10000>; 8016c4ea75SDong Aisheng clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 81ea16e637SFrank Li <&sdhc1_lpcg IMX_LPCG_CLK_5>, 82ea16e637SFrank Li <&sdhc1_lpcg IMX_LPCG_CLK_0>; 8306acb824SPeng Fan clock-names = "ipg", "ahb", "per"; 840dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_1>; 850dcd27bdSDong Aisheng fsl,tuning-start-tap = <20>; 860dcd27bdSDong Aisheng fsl,tuning-step = <2>; 870dcd27bdSDong Aisheng status = "disabled"; 880dcd27bdSDong Aisheng }; 890dcd27bdSDong Aisheng 900dcd27bdSDong Aisheng usdhc3: mmc@5b030000 { 910dcd27bdSDong Aisheng interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 920dcd27bdSDong Aisheng reg = <0x5b030000 0x10000>; 9316c4ea75SDong Aisheng clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 94ea16e637SFrank Li <&sdhc2_lpcg IMX_LPCG_CLK_5>, 95ea16e637SFrank Li <&sdhc2_lpcg IMX_LPCG_CLK_0>; 9606acb824SPeng Fan clock-names = "ipg", "ahb", "per"; 970dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_2>; 980dcd27bdSDong Aisheng status = "disabled"; 990dcd27bdSDong Aisheng }; 1000dcd27bdSDong Aisheng 1010dcd27bdSDong Aisheng fec1: ethernet@5b040000 { 1020dcd27bdSDong Aisheng reg = <0x5b040000 0x10000>; 1030dcd27bdSDong Aisheng interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1040dcd27bdSDong Aisheng <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1050dcd27bdSDong Aisheng <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1060dcd27bdSDong Aisheng <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 10716c4ea75SDong Aisheng clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, 10816c4ea75SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_2>, 109dfda1fd1SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_3>, 11016c4ea75SDong Aisheng <&enet0_lpcg IMX_LPCG_CLK_0>; 1110dcd27bdSDong Aisheng clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 112dfda1fd1SDong Aisheng assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 113dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 114dfda1fd1SDong Aisheng assigned-clock-rates = <250000000>, <125000000>; 1150dcd27bdSDong Aisheng fsl,num-tx-queues = <3>; 1160dcd27bdSDong Aisheng fsl,num-rx-queues = <3>; 1170dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_ENET_0>; 1180dcd27bdSDong Aisheng status = "disabled"; 1190dcd27bdSDong Aisheng }; 1200dcd27bdSDong Aisheng 1210dcd27bdSDong Aisheng fec2: ethernet@5b050000 { 1220dcd27bdSDong Aisheng reg = <0x5b050000 0x10000>; 1230dcd27bdSDong Aisheng interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1240dcd27bdSDong Aisheng <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1250dcd27bdSDong Aisheng <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1260dcd27bdSDong Aisheng <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 12716c4ea75SDong Aisheng clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, 12816c4ea75SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_2>, 129dfda1fd1SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_3>, 13016c4ea75SDong Aisheng <&enet1_lpcg IMX_LPCG_CLK_0>; 1310dcd27bdSDong Aisheng clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 132dfda1fd1SDong Aisheng assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 133dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>; 134dfda1fd1SDong Aisheng assigned-clock-rates = <250000000>, <125000000>; 1350dcd27bdSDong Aisheng fsl,num-tx-queues = <3>; 1360dcd27bdSDong Aisheng fsl,num-rx-queues = <3>; 1370dcd27bdSDong Aisheng power-domains = <&pd IMX_SC_R_ENET_1>; 1380dcd27bdSDong Aisheng status = "disabled"; 1390dcd27bdSDong Aisheng }; 1409de8a226SDong Aisheng 141a8bd7f15SFrank Li usbotg3: usb@5b110000 { 142a8bd7f15SFrank Li compatible = "fsl,imx8qm-usb3"; 143a8bd7f15SFrank Li reg = <0x5b110000 0x10000>; 144a8bd7f15SFrank Li #address-cells = <1>; 145a8bd7f15SFrank Li #size-cells = <1>; 146a8bd7f15SFrank Li ranges; 147a8bd7f15SFrank Li clocks = <&usb3_lpcg IMX_LPCG_CLK_1>, 148a8bd7f15SFrank Li <&usb3_lpcg IMX_LPCG_CLK_0>, 149a8bd7f15SFrank Li <&usb3_lpcg IMX_LPCG_CLK_7>, 150a8bd7f15SFrank Li <&usb3_lpcg IMX_LPCG_CLK_4>, 151a8bd7f15SFrank Li <&usb3_lpcg IMX_LPCG_CLK_5>; 152a8bd7f15SFrank Li clock-names = "lpm", "bus", "aclk", "ipg", "core"; 153a8bd7f15SFrank Li assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; 154a8bd7f15SFrank Li assigned-clock-rates = <250000000>; 155a8bd7f15SFrank Li power-domains = <&pd IMX_SC_R_USB_2>; 156a8bd7f15SFrank Li status = "disabled"; 157a8bd7f15SFrank Li 158a8bd7f15SFrank Li usbotg3_cdns3: usb@5b120000 { 159a8bd7f15SFrank Li compatible = "cdns,usb3"; 1606b15a78fSAlexander Stein reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */ 1616b15a78fSAlexander Stein <0x5b130000 0x10000>, /* memory area for HOST registers */ 1626b15a78fSAlexander Stein <0x5b140000 0x10000>; /* memory area for DEVICE registers */ 1636b15a78fSAlexander Stein reg-names = "otg", "xhci", "dev"; 164a8bd7f15SFrank Li interrupt-parent = <&gic>; 165a8bd7f15SFrank Li interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 166a8bd7f15SFrank Li <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 167a8bd7f15SFrank Li <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 168a8bd7f15SFrank Li <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; 169a8bd7f15SFrank Li interrupt-names = "host", "peripheral", "otg", "wakeup"; 170a8bd7f15SFrank Li phys = <&usb3_phy>; 171a8bd7f15SFrank Li phy-names = "cdns3,usb3-phy"; 1720f554e37SFrank Li cdns,on-chip-buff-size = /bits/ 16 <18>; 173a8bd7f15SFrank Li status = "disabled"; 174a8bd7f15SFrank Li }; 175a8bd7f15SFrank Li }; 176a8bd7f15SFrank Li 177a8bd7f15SFrank Li usb3_phy: usb-phy@5b160000 { 178a8bd7f15SFrank Li compatible = "nxp,salvo-phy"; 179a8bd7f15SFrank Li reg = <0x5b160000 0x40000>; 180a8bd7f15SFrank Li clocks = <&usb3_lpcg IMX_LPCG_CLK_6>; 181a8bd7f15SFrank Li clock-names = "salvo_phy_clk"; 182a8bd7f15SFrank Li power-domains = <&pd IMX_SC_R_USB_2_PHY>; 183a8bd7f15SFrank Li #phy-cells = <0>; 184a8bd7f15SFrank Li status = "disabled"; 185a8bd7f15SFrank Li }; 186a8bd7f15SFrank Li 1879de8a226SDong Aisheng /* LPCG clocks */ 1889de8a226SDong Aisheng sdhc0_lpcg: clock-controller@5b200000 { 18916c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 1909de8a226SDong Aisheng reg = <0x5b200000 0x10000>; 1919de8a226SDong Aisheng #clock-cells = <1>; 19226de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, 1939de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 1949de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 1959de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 1969de8a226SDong Aisheng clock-output-names = "sdhc0_lpcg_per_clk", 1979de8a226SDong Aisheng "sdhc0_lpcg_ipg_clk", 1989de8a226SDong Aisheng "sdhc0_lpcg_ahb_clk"; 1999de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 2009de8a226SDong Aisheng }; 2019de8a226SDong Aisheng 2029de8a226SDong Aisheng sdhc1_lpcg: clock-controller@5b210000 { 20316c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 2049de8a226SDong Aisheng reg = <0x5b210000 0x10000>; 2059de8a226SDong Aisheng #clock-cells = <1>; 20626de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, 2079de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 2089de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 2099de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 2109de8a226SDong Aisheng clock-output-names = "sdhc1_lpcg_per_clk", 2119de8a226SDong Aisheng "sdhc1_lpcg_ipg_clk", 2129de8a226SDong Aisheng "sdhc1_lpcg_ahb_clk"; 2139de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_1>; 2149de8a226SDong Aisheng }; 2159de8a226SDong Aisheng 2169de8a226SDong Aisheng sdhc2_lpcg: clock-controller@5b220000 { 21716c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 2189de8a226SDong Aisheng reg = <0x5b220000 0x10000>; 2199de8a226SDong Aisheng #clock-cells = <1>; 22026de33a1SDong Aisheng clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, 2219de8a226SDong Aisheng <&conn_ipg_clk>, <&conn_axi_clk>; 2229de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 2239de8a226SDong Aisheng <IMX_LPCG_CLK_5>; 2249de8a226SDong Aisheng clock-output-names = "sdhc2_lpcg_per_clk", 2259de8a226SDong Aisheng "sdhc2_lpcg_ipg_clk", 2269de8a226SDong Aisheng "sdhc2_lpcg_ahb_clk"; 2279de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_2>; 2289de8a226SDong Aisheng }; 2299de8a226SDong Aisheng 2309de8a226SDong Aisheng enet0_lpcg: clock-controller@5b230000 { 23116c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 2329de8a226SDong Aisheng reg = <0x5b230000 0x10000>; 2339de8a226SDong Aisheng #clock-cells = <1>; 23426de33a1SDong Aisheng clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 23526de33a1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 236dfda1fd1SDong Aisheng <&conn_axi_clk>, 237dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 238dfda1fd1SDong Aisheng <&conn_ipg_clk>, 239dfda1fd1SDong Aisheng <&conn_ipg_clk>; 2409de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 241dfda1fd1SDong Aisheng <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 242dfda1fd1SDong Aisheng <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 243dfda1fd1SDong Aisheng clock-output-names = "enet0_lpcg_timer_clk", 244dfda1fd1SDong Aisheng "enet0_lpcg_txc_sampling_clk", 245dfda1fd1SDong Aisheng "enet0_lpcg_ahb_clk", 246dfda1fd1SDong Aisheng "enet0_lpcg_rgmii_txc_clk", 247dfda1fd1SDong Aisheng "enet0_lpcg_ipg_clk", 248dfda1fd1SDong Aisheng "enet0_lpcg_ipg_s_clk"; 2499de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_ENET_0>; 2509de8a226SDong Aisheng }; 2519de8a226SDong Aisheng 2529de8a226SDong Aisheng enet1_lpcg: clock-controller@5b240000 { 25316c4ea75SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 2549de8a226SDong Aisheng reg = <0x5b240000 0x10000>; 2559de8a226SDong Aisheng #clock-cells = <1>; 25626de33a1SDong Aisheng clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 25726de33a1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 258dfda1fd1SDong Aisheng <&conn_axi_clk>, 259dfda1fd1SDong Aisheng <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>, 260dfda1fd1SDong Aisheng <&conn_ipg_clk>, 261dfda1fd1SDong Aisheng <&conn_ipg_clk>; 2629de8a226SDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 263dfda1fd1SDong Aisheng <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>, 264dfda1fd1SDong Aisheng <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 265dfda1fd1SDong Aisheng clock-output-names = "enet1_lpcg_timer_clk", 266dfda1fd1SDong Aisheng "enet1_lpcg_txc_sampling_clk", 267dfda1fd1SDong Aisheng "enet1_lpcg_ahb_clk", 268dfda1fd1SDong Aisheng "enet1_lpcg_rgmii_txc_clk", 269dfda1fd1SDong Aisheng "enet1_lpcg_ipg_clk", 270dfda1fd1SDong Aisheng "enet1_lpcg_ipg_s_clk"; 2719de8a226SDong Aisheng power-domains = <&pd IMX_SC_R_ENET_1>; 2729de8a226SDong Aisheng }; 2738065fc93SFrank Li 2748065fc93SFrank Li usb2_lpcg: clock-controller@5b270000 { 2758065fc93SFrank Li compatible = "fsl,imx8qxp-lpcg"; 2768065fc93SFrank Li reg = <0x5b270000 0x10000>; 2778065fc93SFrank Li #clock-cells = <1>; 2788065fc93SFrank Li clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; 2798065fc93SFrank Li clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 2808065fc93SFrank Li clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; 2818065fc93SFrank Li power-domains = <&pd IMX_SC_R_USB_0_PHY>; 2828065fc93SFrank Li }; 283a8bd7f15SFrank Li 284a8bd7f15SFrank Li usb3_lpcg: clock-controller@5b280000 { 285a8bd7f15SFrank Li compatible = "fsl,imx8qxp-lpcg"; 286a8bd7f15SFrank Li reg = <0x5b280000 0x10000>; 287a8bd7f15SFrank Li #clock-cells = <1>; 288a8bd7f15SFrank Li clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 289a8bd7f15SFrank Li <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 290a8bd7f15SFrank Li <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; 291a8bd7f15SFrank Li clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, 292a8bd7f15SFrank Li <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, 293a8bd7f15SFrank Li <&conn_ipg_clk>, 294a8bd7f15SFrank Li <&conn_ipg_clk>, 295a8bd7f15SFrank Li <&conn_ipg_clk>, 296a8bd7f15SFrank Li <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; 297a8bd7f15SFrank Li clock-output-names = "usb3_app_clk", 298a8bd7f15SFrank Li "usb3_lpm_clk", 299a8bd7f15SFrank Li "usb3_ipg_clk", 300a8bd7f15SFrank Li "usb3_core_pclk", 301a8bd7f15SFrank Li "usb3_phy_clk", 302a8bd7f15SFrank Li "usb3_aclk"; 303a8bd7f15SFrank Li power-domains = <&pd IMX_SC_R_USB_2_PHY>; 304a8bd7f15SFrank Li }; 3050dcd27bdSDong Aisheng}; 306