1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a72"; 38 reg = <0x1>; 39 enable-method = "psci"; 40 clocks = <&clockgen 1 0>; 41 next-level-cache = <&l2>; 42 cpu-idle-states = <&CPU_PW20>; 43 #cooling-cells = <2>; 44 }; 45 46 l2: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 idle-states { 52 /* 53 * PSCI node is not added default, U-boot will add missing 54 * parts if it determines to use PSCI. 55 */ 56 entry-method = "arm,psci"; 57 58 CPU_PW20: cpu-pw20 { 59 compatible = "arm,idle-state"; 60 idle-state-name = "PW20"; 61 arm,psci-suspend-param = <0x0>; 62 entry-latency-us = <2000>; 63 exit-latency-us = <2000>; 64 min-residency-us = <6000>; 65 }; 66 }; 67 68 sysclk: clock-sysclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "sysclk"; 73 }; 74 75 osc_27m: clock-osc-27m { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <27000000>; 79 clock-output-names = "phy_27m"; 80 }; 81 82 dpclk: clock-controller@f1f0000 { 83 compatible = "fsl,ls1028a-plldig"; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; 85 #clock-cells = <1>; 86 clocks = <&osc_27m>; 87 }; 88 89 aclk: clock-axi { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <650000000>; 93 clock-output-names= "aclk"; 94 }; 95 96 pclk: clock-apb { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <650000000>; 100 clock-output-names= "pclk"; 101 }; 102 103 reboot { 104 compatible ="syscon-reboot"; 105 regmap = <&dcfg>; 106 offset = <0xb0>; 107 mask = <0x02>; 108 }; 109 110 timer { 111 compatible = "arm,armv8-timer"; 112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 113 IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 115 IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 117 IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 119 IRQ_TYPE_LEVEL_LOW)>; 120 }; 121 122 pmu { 123 compatible = "arm,cortex-a72-pmu"; 124 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 gic: interrupt-controller@6000000 { 128 compatible= "arm,gic-v3"; 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 133 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 134 #interrupt-cells= <3>; 135 interrupt-controller; 136 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 137 IRQ_TYPE_LEVEL_LOW)>; 138 its: gic-its@6020000 { 139 compatible = "arm,gic-v3-its"; 140 msi-controller; 141 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 142 }; 143 }; 144 145 soc: soc { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 ddr: memory-controller@1080000 { 152 compatible = "fsl,qoriq-memory-controller"; 153 reg = <0x0 0x1080000 0x0 0x1000>; 154 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 155 big-endian; 156 }; 157 158 dcfg: syscon@1e00000 { 159 compatible = "fsl,ls1028a-dcfg", "syscon"; 160 reg = <0x0 0x1e00000 0x0 0x10000>; 161 big-endian; 162 }; 163 164 scfg: syscon@1fc0000 { 165 compatible = "fsl,ls1028a-scfg", "syscon"; 166 reg = <0x0 0x1fc0000 0x0 0x10000>; 167 big-endian; 168 }; 169 170 clockgen: clock-controller@1300000 { 171 compatible = "fsl,ls1028a-clockgen"; 172 reg = <0x0 0x1300000 0x0 0xa0000>; 173 #clock-cells = <2>; 174 clocks = <&sysclk>; 175 }; 176 177 i2c0: i2c@2000000 { 178 compatible = "fsl,vf610-i2c"; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 reg = <0x0 0x2000000 0x0 0x10000>; 182 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&clockgen 4 3>; 184 status = "disabled"; 185 }; 186 187 i2c1: i2c@2010000 { 188 compatible = "fsl,vf610-i2c"; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 reg = <0x0 0x2010000 0x0 0x10000>; 192 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&clockgen 4 3>; 194 status = "disabled"; 195 }; 196 197 i2c2: i2c@2020000 { 198 compatible = "fsl,vf610-i2c"; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 reg = <0x0 0x2020000 0x0 0x10000>; 202 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&clockgen 4 3>; 204 status = "disabled"; 205 }; 206 207 i2c3: i2c@2030000 { 208 compatible = "fsl,vf610-i2c"; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 reg = <0x0 0x2030000 0x0 0x10000>; 212 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&clockgen 4 3>; 214 status = "disabled"; 215 }; 216 217 i2c4: i2c@2040000 { 218 compatible = "fsl,vf610-i2c"; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 reg = <0x0 0x2040000 0x0 0x10000>; 222 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&clockgen 4 3>; 224 status = "disabled"; 225 }; 226 227 i2c5: i2c@2050000 { 228 compatible = "fsl,vf610-i2c"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 reg = <0x0 0x2050000 0x0 0x10000>; 232 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&clockgen 4 3>; 234 status = "disabled"; 235 }; 236 237 i2c6: i2c@2060000 { 238 compatible = "fsl,vf610-i2c"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0x0 0x2060000 0x0 0x10000>; 242 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&clockgen 4 3>; 244 status = "disabled"; 245 }; 246 247 i2c7: i2c@2070000 { 248 compatible = "fsl,vf610-i2c"; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 reg = <0x0 0x2070000 0x0 0x10000>; 252 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&clockgen 4 3>; 254 status = "disabled"; 255 }; 256 257 esdhc: mmc@2140000 { 258 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 259 reg = <0x0 0x2140000 0x0 0x10000>; 260 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 261 clock-frequency = <0>; /* fixed up by bootloader */ 262 clocks = <&clockgen 2 1>; 263 voltage-ranges = <1800 1800 3300 3300>; 264 sdhci,auto-cmd12; 265 little-endian; 266 bus-width = <4>; 267 status = "disabled"; 268 }; 269 270 esdhc1: mmc@2150000 { 271 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 272 reg = <0x0 0x2150000 0x0 0x10000>; 273 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 274 clock-frequency = <0>; /* fixed up by bootloader */ 275 clocks = <&clockgen 2 1>; 276 voltage-ranges = <1800 1800 3300 3300>; 277 sdhci,auto-cmd12; 278 broken-cd; 279 little-endian; 280 bus-width = <4>; 281 status = "disabled"; 282 }; 283 284 duart0: serial@21c0500 { 285 compatible = "fsl,ns16550", "ns16550a"; 286 reg = <0x00 0x21c0500 0x0 0x100>; 287 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clockgen 4 1>; 289 status = "disabled"; 290 }; 291 292 duart1: serial@21c0600 { 293 compatible = "fsl,ns16550", "ns16550a"; 294 reg = <0x00 0x21c0600 0x0 0x100>; 295 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&clockgen 4 1>; 297 status = "disabled"; 298 }; 299 300 edma0: dma-controller@22c0000 { 301 #dma-cells = <2>; 302 compatible = "fsl,vf610-edma"; 303 reg = <0x0 0x22c0000 0x0 0x10000>, 304 <0x0 0x22d0000 0x0 0x10000>, 305 <0x0 0x22e0000 0x0 0x10000>; 306 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "edma-tx", "edma-err"; 309 dma-channels = <32>; 310 clock-names = "dmamux0", "dmamux1"; 311 clocks = <&clockgen 4 1>, 312 <&clockgen 4 1>; 313 }; 314 315 gpio1: gpio@2300000 { 316 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 317 reg = <0x0 0x2300000 0x0 0x10000>; 318 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 319 gpio-controller; 320 #gpio-cells = <2>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 little-endian; 324 }; 325 326 gpio2: gpio@2310000 { 327 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 328 reg = <0x0 0x2310000 0x0 0x10000>; 329 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 little-endian; 335 }; 336 337 gpio3: gpio@2320000 { 338 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 339 reg = <0x0 0x2320000 0x0 0x10000>; 340 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 little-endian; 346 }; 347 348 usb0: usb@3100000 { 349 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 350 reg = <0x0 0x3100000 0x0 0x10000>; 351 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 352 dr_mode = "host"; 353 snps,dis_rxdet_inp3_quirk; 354 snps,quirk-frame-length-adjustment = <0x20>; 355 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 356 }; 357 358 usb1: usb@3110000 { 359 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 360 reg = <0x0 0x3110000 0x0 0x10000>; 361 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 362 dr_mode = "host"; 363 snps,dis_rxdet_inp3_quirk; 364 snps,quirk-frame-length-adjustment = <0x20>; 365 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 366 }; 367 368 sata: sata@3200000 { 369 compatible = "fsl,ls1028a-ahci"; 370 reg = <0x0 0x3200000 0x0 0x10000>, 371 <0x7 0x100520 0x0 0x4>; 372 reg-names = "ahci", "sata-ecc"; 373 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&clockgen 4 1>; 375 status = "disabled"; 376 }; 377 378 smmu: iommu@5000000 { 379 compatible = "arm,mmu-500"; 380 reg = <0 0x5000000 0 0x800000>; 381 #global-interrupts = <8>; 382 #iommu-cells = <1>; 383 stream-match-mask = <0x7c00>; 384 /* global secure fault */ 385 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 386 /* combined secure interrupt */ 387 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 388 /* global non-secure fault */ 389 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 390 /* combined non-secure interrupt */ 391 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 392 /* performance counter interrupts 0-7 */ 393 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 395 /* per context interrupt, 64 interrupts */ 396 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 428 }; 429 430 crypto: crypto@8000000 { 431 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 432 fsl,sec-era = <10>; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 ranges = <0x0 0x00 0x8000000 0x100000>; 436 reg = <0x00 0x8000000 0x0 0x100000>; 437 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 438 dma-coherent; 439 440 sec_jr0: jr@10000 { 441 compatible = "fsl,sec-v5.0-job-ring", 442 "fsl,sec-v4.0-job-ring"; 443 reg = <0x10000 0x10000>; 444 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 445 }; 446 447 sec_jr1: jr@20000 { 448 compatible = "fsl,sec-v5.0-job-ring", 449 "fsl,sec-v4.0-job-ring"; 450 reg = <0x20000 0x10000>; 451 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 452 }; 453 454 sec_jr2: jr@30000 { 455 compatible = "fsl,sec-v5.0-job-ring", 456 "fsl,sec-v4.0-job-ring"; 457 reg = <0x30000 0x10000>; 458 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 459 }; 460 461 sec_jr3: jr@40000 { 462 compatible = "fsl,sec-v5.0-job-ring", 463 "fsl,sec-v4.0-job-ring"; 464 reg = <0x40000 0x10000>; 465 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 466 }; 467 }; 468 469 qdma: dma-controller@8380000 { 470 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 471 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 472 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 473 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 474 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "qdma-error", "qdma-queue0", 480 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 481 dma-channels = <8>; 482 block-number = <1>; 483 block-offset = <0x10000>; 484 fsl,dma-queues = <2>; 485 status-sizes = <64>; 486 queue-sizes = <64 64>; 487 }; 488 489 cluster1_core0_watchdog: watchdog@c000000 { 490 compatible = "arm,sp805", "arm,primecell"; 491 reg = <0x0 0xc000000 0x0 0x1000>; 492 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 493 clock-names = "apb_pclk", "wdog_clk"; 494 }; 495 496 cluster1_core1_watchdog: watchdog@c010000 { 497 compatible = "arm,sp805", "arm,primecell"; 498 reg = <0x0 0xc010000 0x0 0x1000>; 499 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 500 clock-names = "apb_pclk", "wdog_clk"; 501 }; 502 503 sai1: audio-controller@f100000 { 504 #sound-dai-cells = <0>; 505 compatible = "fsl,vf610-sai"; 506 reg = <0x0 0xf100000 0x0 0x10000>; 507 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 509 <&clockgen 4 1>, <&clockgen 4 1>; 510 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 511 dma-names = "tx", "rx"; 512 dmas = <&edma0 1 4>, 513 <&edma0 1 3>; 514 status = "disabled"; 515 }; 516 517 sai2: audio-controller@f110000 { 518 #sound-dai-cells = <0>; 519 compatible = "fsl,vf610-sai"; 520 reg = <0x0 0xf110000 0x0 0x10000>; 521 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 523 <&clockgen 4 1>, <&clockgen 4 1>; 524 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 525 dma-names = "tx", "rx"; 526 dmas = <&edma0 1 6>, 527 <&edma0 1 5>; 528 status = "disabled"; 529 }; 530 531 sai4: audio-controller@f130000 { 532 #sound-dai-cells = <0>; 533 compatible = "fsl,vf610-sai"; 534 reg = <0x0 0xf130000 0x0 0x10000>; 535 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 537 <&clockgen 4 1>, <&clockgen 4 1>; 538 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 539 dma-names = "tx", "rx"; 540 dmas = <&edma0 1 10>, 541 <&edma0 1 9>; 542 status = "disabled"; 543 }; 544 545 tmu: tmu@1f00000 { 546 compatible = "fsl,qoriq-tmu"; 547 reg = <0x0 0x1f80000 0x0 0x10000>; 548 interrupts = <0 23 0x4>; 549 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 550 fsl,tmu-calibration = <0x00000000 0x00000024 551 0x00000001 0x0000002b 552 0x00000002 0x00000031 553 0x00000003 0x00000038 554 0x00000004 0x0000003f 555 0x00000005 0x00000045 556 0x00000006 0x0000004c 557 0x00000007 0x00000053 558 0x00000008 0x00000059 559 0x00000009 0x00000060 560 0x0000000a 0x00000066 561 0x0000000b 0x0000006d 562 563 0x00010000 0x0000001c 564 0x00010001 0x00000024 565 0x00010002 0x0000002c 566 0x00010003 0x00000035 567 0x00010004 0x0000003d 568 0x00010005 0x00000045 569 0x00010006 0x0000004d 570 0x00010007 0x00000045 571 0x00010008 0x0000005e 572 0x00010009 0x00000066 573 0x0001000a 0x0000006e 574 575 0x00020000 0x00000018 576 0x00020001 0x00000022 577 0x00020002 0x0000002d 578 0x00020003 0x00000038 579 0x00020004 0x00000043 580 0x00020005 0x0000004d 581 0x00020006 0x00000058 582 0x00020007 0x00000063 583 0x00020008 0x0000006e 584 585 0x00030000 0x00000010 586 0x00030001 0x0000001c 587 0x00030002 0x00000029 588 0x00030003 0x00000036 589 0x00030004 0x00000042 590 0x00030005 0x0000004f 591 0x00030006 0x0000005b 592 0x00030007 0x00000068>; 593 little-endian; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 thermal-zones { 598 core-cluster { 599 polling-delay-passive = <1000>; 600 polling-delay = <5000>; 601 thermal-sensors = <&tmu 0>; 602 603 trips { 604 core_cluster_alert: core-cluster-alert { 605 temperature = <85000>; 606 hysteresis = <2000>; 607 type = "passive"; 608 }; 609 610 core_cluster_crit: core-cluster-crit { 611 temperature = <95000>; 612 hysteresis = <2000>; 613 type = "critical"; 614 }; 615 }; 616 617 cooling-maps { 618 map0 { 619 trip = <&core_cluster_alert>; 620 cooling-device = 621 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 622 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 623 }; 624 }; 625 }; 626 }; 627 628 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 629 compatible = "pci-host-ecam-generic"; 630 reg = <0x01 0xf0000000 0x0 0x100000>; 631 #address-cells = <3>; 632 #size-cells = <2>; 633 #interrupt-cells = <1>; 634 msi-parent = <&its>; 635 device_type = "pci"; 636 bus-range = <0x0 0x0>; 637 dma-coherent; 638 msi-map = <0 &its 0x17 0xe>; 639 iommu-map = <0 &smmu 0x17 0xe>; 640 /* PF0-6 BAR0 - non-prefetchable memory */ 641 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 642 /* PF0-6 BAR2 - prefetchable memory */ 643 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 644 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 645 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 646 /* PF0: VF0-1 BAR2 - prefetchable memory */ 647 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 648 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 649 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 650 /* PF1: VF0-1 BAR2 - prefetchable memory */ 651 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 652 653 enetc_port0: ethernet@0,0 { 654 compatible = "fsl,enetc"; 655 reg = <0x000000 0 0 0 0>; 656 }; 657 enetc_port1: ethernet@0,1 { 658 compatible = "fsl,enetc"; 659 reg = <0x000100 0 0 0 0>; 660 }; 661 enetc_mdio_pf3: mdio@0,3 { 662 compatible = "fsl,enetc-mdio"; 663 reg = <0x000300 0 0 0 0>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 }; 667 ethernet@0,4 { 668 compatible = "fsl,enetc-ptp"; 669 reg = <0x000400 0 0 0 0>; 670 clocks = <&clockgen 4 0>; 671 little-endian; 672 }; 673 }; 674 }; 675 676 malidp0: display@f080000 { 677 compatible = "arm,mali-dp500"; 678 reg = <0x0 0xf080000 0x0 0x10000>; 679 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 680 <0 223 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-names = "DE", "SE"; 682 clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>; 683 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 684 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 685 arm,malidp-arqos-value = <0xd000d000>; 686 687 port { 688 dp0_out: endpoint { 689 690 }; 691 }; 692 }; 693}; 694