1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 next-level-cache = <&l2>; 32 cpu-idle-states = <&CPU_PW20>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a72"; 39 reg = <0x1>; 40 enable-method = "psci"; 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PW20>; 44 #cooling-cells = <2>; 45 }; 46 47 l2: l2-cache { 48 compatible = "cache"; 49 }; 50 }; 51 52 idle-states { 53 /* 54 * PSCI node is not added default, U-boot will add missing 55 * parts if it determines to use PSCI. 56 */ 57 entry-method = "psci"; 58 59 CPU_PW20: cpu-pw20 { 60 compatible = "arm,idle-state"; 61 idle-state-name = "PW20"; 62 arm,psci-suspend-param = <0x0>; 63 entry-latency-us = <2000>; 64 exit-latency-us = <2000>; 65 min-residency-us = <6000>; 66 }; 67 }; 68 69 rtc_clk: rtc-clk { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <32768>; 73 clock-output-names = "rtc_clk"; 74 }; 75 76 sysclk: sysclk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <100000000>; 80 clock-output-names = "sysclk"; 81 }; 82 83 osc_27m: clock-osc-27m { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <27000000>; 87 clock-output-names = "phy_27m"; 88 }; 89 90 firmware { 91 optee: optee { 92 compatible = "linaro,optee-tz"; 93 method = "smc"; 94 status = "disabled"; 95 }; 96 }; 97 98 reboot { 99 compatible ="syscon-reboot"; 100 regmap = <&rst>; 101 offset = <0>; 102 mask = <0x02>; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 108 IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 110 IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 112 IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 114 IRQ_TYPE_LEVEL_LOW)>; 115 }; 116 117 pmu { 118 compatible = "arm,cortex-a72-pmu"; 119 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 gic: interrupt-controller@6000000 { 123 compatible= "arm,gic-v3"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 129 #interrupt-cells= <3>; 130 interrupt-controller; 131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 132 IRQ_TYPE_LEVEL_LOW)>; 133 its: gic-its@6020000 { 134 compatible = "arm,gic-v3-its"; 135 msi-controller; 136 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 137 }; 138 }; 139 140 thermal-zones { 141 ddr-controller { 142 polling-delay-passive = <1000>; 143 polling-delay = <5000>; 144 thermal-sensors = <&tmu 0>; 145 146 trips { 147 ddr-ctrler-alert { 148 temperature = <85000>; 149 hysteresis = <2000>; 150 type = "passive"; 151 }; 152 153 ddr-ctrler-crit { 154 temperature = <95000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 }; 160 161 core-cluster { 162 polling-delay-passive = <1000>; 163 polling-delay = <5000>; 164 thermal-sensors = <&tmu 1>; 165 166 trips { 167 core_cluster_alert: core-cluster-alert { 168 temperature = <85000>; 169 hysteresis = <2000>; 170 type = "passive"; 171 }; 172 173 core_cluster_crit: core-cluster-crit { 174 temperature = <95000>; 175 hysteresis = <2000>; 176 type = "critical"; 177 }; 178 }; 179 180 cooling-maps { 181 map0 { 182 trip = <&core_cluster_alert>; 183 cooling-device = 184 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 186 }; 187 }; 188 }; 189 }; 190 191 soc: soc { 192 compatible = "simple-bus"; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 197 ddr: memory-controller@1080000 { 198 compatible = "fsl,qoriq-memory-controller"; 199 reg = <0x0 0x1080000 0x0 0x1000>; 200 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 201 little-endian; 202 }; 203 204 dcfg: syscon@1e00000 { 205 #address-cells = <1>; 206 #size-cells = <1>; 207 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 208 reg = <0x0 0x1e00000 0x0 0x10000>; 209 ranges = <0x0 0x0 0x1e00000 0x10000>; 210 little-endian; 211 212 fspi_clk: clock-controller@900 { 213 compatible = "fsl,ls1028a-flexspi-clk"; 214 reg = <0x900 0x4>; 215 #clock-cells = <0>; 216 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 217 clock-output-names = "fspi_clk"; 218 }; 219 }; 220 221 rst: syscon@1e60000 { 222 compatible = "syscon"; 223 reg = <0x0 0x1e60000 0x0 0x10000>; 224 little-endian; 225 }; 226 227 scfg: syscon@1fc0000 { 228 compatible = "fsl,ls1028a-scfg", "syscon"; 229 reg = <0x0 0x1fc0000 0x0 0x10000>; 230 big-endian; 231 }; 232 233 clockgen: clock-controller@1300000 { 234 compatible = "fsl,ls1028a-clockgen"; 235 reg = <0x0 0x1300000 0x0 0xa0000>; 236 #clock-cells = <2>; 237 clocks = <&sysclk>; 238 }; 239 240 i2c0: i2c@2000000 { 241 compatible = "fsl,vf610-i2c"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0x0 0x2000000 0x0 0x10000>; 245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 247 QORIQ_CLK_PLL_DIV(4)>; 248 status = "disabled"; 249 }; 250 251 i2c1: i2c@2010000 { 252 compatible = "fsl,vf610-i2c"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 reg = <0x0 0x2010000 0x0 0x10000>; 256 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 258 QORIQ_CLK_PLL_DIV(4)>; 259 status = "disabled"; 260 }; 261 262 i2c2: i2c@2020000 { 263 compatible = "fsl,vf610-i2c"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 reg = <0x0 0x2020000 0x0 0x10000>; 267 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 269 QORIQ_CLK_PLL_DIV(4)>; 270 status = "disabled"; 271 }; 272 273 i2c3: i2c@2030000 { 274 compatible = "fsl,vf610-i2c"; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 reg = <0x0 0x2030000 0x0 0x10000>; 278 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 280 QORIQ_CLK_PLL_DIV(4)>; 281 status = "disabled"; 282 }; 283 284 i2c4: i2c@2040000 { 285 compatible = "fsl,vf610-i2c"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0x0 0x2040000 0x0 0x10000>; 289 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 291 QORIQ_CLK_PLL_DIV(4)>; 292 status = "disabled"; 293 }; 294 295 i2c5: i2c@2050000 { 296 compatible = "fsl,vf610-i2c"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x2050000 0x0 0x10000>; 300 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 302 QORIQ_CLK_PLL_DIV(4)>; 303 status = "disabled"; 304 }; 305 306 i2c6: i2c@2060000 { 307 compatible = "fsl,vf610-i2c"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 reg = <0x0 0x2060000 0x0 0x10000>; 311 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 313 QORIQ_CLK_PLL_DIV(4)>; 314 status = "disabled"; 315 }; 316 317 i2c7: i2c@2070000 { 318 compatible = "fsl,vf610-i2c"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 reg = <0x0 0x2070000 0x0 0x10000>; 322 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 324 QORIQ_CLK_PLL_DIV(4)>; 325 status = "disabled"; 326 }; 327 328 fspi: spi@20c0000 { 329 compatible = "nxp,lx2160a-fspi"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 reg = <0x0 0x20c0000 0x0 0x10000>, 333 <0x0 0x20000000 0x0 0x10000000>; 334 reg-names = "fspi_base", "fspi_mmap"; 335 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&fspi_clk>, <&fspi_clk>; 337 clock-names = "fspi_en", "fspi"; 338 status = "disabled"; 339 }; 340 341 dspi0: spi@2100000 { 342 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 reg = <0x0 0x2100000 0x0 0x10000>; 346 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 347 clock-names = "dspi"; 348 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 349 QORIQ_CLK_PLL_DIV(2)>; 350 dmas = <&edma0 0 62>, <&edma0 0 60>; 351 dma-names = "tx", "rx"; 352 spi-num-chipselects = <4>; 353 little-endian; 354 status = "disabled"; 355 }; 356 357 dspi1: spi@2110000 { 358 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 reg = <0x0 0x2110000 0x0 0x10000>; 362 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 363 clock-names = "dspi"; 364 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 365 QORIQ_CLK_PLL_DIV(2)>; 366 dmas = <&edma0 0 58>, <&edma0 0 56>; 367 dma-names = "tx", "rx"; 368 spi-num-chipselects = <4>; 369 little-endian; 370 status = "disabled"; 371 }; 372 373 dspi2: spi@2120000 { 374 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <0x0 0x2120000 0x0 0x10000>; 378 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 379 clock-names = "dspi"; 380 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 381 QORIQ_CLK_PLL_DIV(2)>; 382 dmas = <&edma0 0 54>, <&edma0 0 2>; 383 dma-names = "tx", "rx"; 384 spi-num-chipselects = <3>; 385 little-endian; 386 status = "disabled"; 387 }; 388 389 esdhc: mmc@2140000 { 390 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 391 reg = <0x0 0x2140000 0x0 0x10000>; 392 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 393 clock-frequency = <0>; /* fixed up by bootloader */ 394 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 395 voltage-ranges = <1800 1800 3300 3300>; 396 sdhci,auto-cmd12; 397 little-endian; 398 bus-width = <4>; 399 status = "disabled"; 400 }; 401 402 esdhc1: mmc@2150000 { 403 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 404 reg = <0x0 0x2150000 0x0 0x10000>; 405 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 406 clock-frequency = <0>; /* fixed up by bootloader */ 407 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 408 voltage-ranges = <1800 1800>; 409 sdhci,auto-cmd12; 410 non-removable; 411 little-endian; 412 bus-width = <4>; 413 status = "disabled"; 414 }; 415 416 can0: can@2180000 { 417 compatible = "fsl,lx2160ar1-flexcan"; 418 reg = <0x0 0x2180000 0x0 0x10000>; 419 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 421 QORIQ_CLK_PLL_DIV(2)>, 422 <&clockgen QORIQ_CLK_PLATFORM_PLL 423 QORIQ_CLK_PLL_DIV(2)>; 424 clock-names = "ipg", "per"; 425 status = "disabled"; 426 }; 427 428 can1: can@2190000 { 429 compatible = "fsl,lx2160ar1-flexcan"; 430 reg = <0x0 0x2190000 0x0 0x10000>; 431 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 433 QORIQ_CLK_PLL_DIV(2)>, 434 <&clockgen QORIQ_CLK_PLATFORM_PLL 435 QORIQ_CLK_PLL_DIV(2)>; 436 clock-names = "ipg", "per"; 437 status = "disabled"; 438 }; 439 440 duart0: serial@21c0500 { 441 compatible = "fsl,ns16550", "ns16550a"; 442 reg = <0x00 0x21c0500 0x0 0x100>; 443 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 445 QORIQ_CLK_PLL_DIV(2)>; 446 status = "disabled"; 447 }; 448 449 duart1: serial@21c0600 { 450 compatible = "fsl,ns16550", "ns16550a"; 451 reg = <0x00 0x21c0600 0x0 0x100>; 452 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 454 QORIQ_CLK_PLL_DIV(2)>; 455 status = "disabled"; 456 }; 457 458 459 lpuart0: serial@2260000 { 460 compatible = "fsl,ls1028a-lpuart"; 461 reg = <0x0 0x2260000 0x0 0x1000>; 462 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 464 QORIQ_CLK_PLL_DIV(2)>; 465 clock-names = "ipg"; 466 dma-names = "rx","tx"; 467 dmas = <&edma0 1 32>, 468 <&edma0 1 33>; 469 status = "disabled"; 470 }; 471 472 lpuart1: serial@2270000 { 473 compatible = "fsl,ls1028a-lpuart"; 474 reg = <0x0 0x2270000 0x0 0x1000>; 475 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 477 QORIQ_CLK_PLL_DIV(2)>; 478 clock-names = "ipg"; 479 dma-names = "rx","tx"; 480 dmas = <&edma0 1 30>, 481 <&edma0 1 31>; 482 status = "disabled"; 483 }; 484 485 lpuart2: serial@2280000 { 486 compatible = "fsl,ls1028a-lpuart"; 487 reg = <0x0 0x2280000 0x0 0x1000>; 488 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 490 QORIQ_CLK_PLL_DIV(2)>; 491 clock-names = "ipg"; 492 dma-names = "rx","tx"; 493 dmas = <&edma0 1 28>, 494 <&edma0 1 29>; 495 status = "disabled"; 496 }; 497 498 lpuart3: serial@2290000 { 499 compatible = "fsl,ls1028a-lpuart"; 500 reg = <0x0 0x2290000 0x0 0x1000>; 501 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 503 QORIQ_CLK_PLL_DIV(2)>; 504 clock-names = "ipg"; 505 dma-names = "rx","tx"; 506 dmas = <&edma0 1 26>, 507 <&edma0 1 27>; 508 status = "disabled"; 509 }; 510 511 lpuart4: serial@22a0000 { 512 compatible = "fsl,ls1028a-lpuart"; 513 reg = <0x0 0x22a0000 0x0 0x1000>; 514 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 516 QORIQ_CLK_PLL_DIV(2)>; 517 clock-names = "ipg"; 518 dma-names = "rx","tx"; 519 dmas = <&edma0 1 24>, 520 <&edma0 1 25>; 521 status = "disabled"; 522 }; 523 524 lpuart5: serial@22b0000 { 525 compatible = "fsl,ls1028a-lpuart"; 526 reg = <0x0 0x22b0000 0x0 0x1000>; 527 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 529 QORIQ_CLK_PLL_DIV(2)>; 530 clock-names = "ipg"; 531 dma-names = "rx","tx"; 532 dmas = <&edma0 1 22>, 533 <&edma0 1 23>; 534 status = "disabled"; 535 }; 536 537 edma0: dma-controller@22c0000 { 538 #dma-cells = <2>; 539 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 540 reg = <0x0 0x22c0000 0x0 0x10000>, 541 <0x0 0x22d0000 0x0 0x10000>, 542 <0x0 0x22e0000 0x0 0x10000>; 543 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "edma-tx", "edma-err"; 546 dma-channels = <32>; 547 clock-names = "dmamux0", "dmamux1"; 548 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 549 QORIQ_CLK_PLL_DIV(2)>, 550 <&clockgen QORIQ_CLK_PLATFORM_PLL 551 QORIQ_CLK_PLL_DIV(2)>; 552 }; 553 554 gpio1: gpio@2300000 { 555 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 556 reg = <0x0 0x2300000 0x0 0x10000>; 557 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 little-endian; 563 }; 564 565 gpio2: gpio@2310000 { 566 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 567 reg = <0x0 0x2310000 0x0 0x10000>; 568 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 569 gpio-controller; 570 #gpio-cells = <2>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 little-endian; 574 }; 575 576 gpio3: gpio@2320000 { 577 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 578 reg = <0x0 0x2320000 0x0 0x10000>; 579 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 580 gpio-controller; 581 #gpio-cells = <2>; 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 little-endian; 585 }; 586 587 usb0: usb@3100000 { 588 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 589 reg = <0x0 0x3100000 0x0 0x10000>; 590 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 591 dr_mode = "host"; 592 snps,dis_rxdet_inp3_quirk; 593 snps,quirk-frame-length-adjustment = <0x20>; 594 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 595 status = "disabled"; 596 }; 597 598 usb1: usb@3110000 { 599 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 600 reg = <0x0 0x3110000 0x0 0x10000>; 601 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 602 dr_mode = "host"; 603 snps,dis_rxdet_inp3_quirk; 604 snps,quirk-frame-length-adjustment = <0x20>; 605 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 606 status = "disabled"; 607 }; 608 609 sata: sata@3200000 { 610 compatible = "fsl,ls1028a-ahci"; 611 reg = <0x0 0x3200000 0x0 0x10000>, 612 <0x7 0x100520 0x0 0x4>; 613 reg-names = "ahci", "sata-ecc"; 614 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 616 QORIQ_CLK_PLL_DIV(2)>; 617 status = "disabled"; 618 }; 619 620 pcie1: pcie@3400000 { 621 compatible = "fsl,ls1028a-pcie"; 622 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 623 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 624 reg-names = "regs", "config"; 625 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 626 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 627 interrupt-names = "pme", "aer"; 628 #address-cells = <3>; 629 #size-cells = <2>; 630 device_type = "pci"; 631 dma-coherent; 632 num-viewport = <8>; 633 bus-range = <0x0 0xff>; 634 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 635 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 636 msi-parent = <&its>; 637 #interrupt-cells = <1>; 638 interrupt-map-mask = <0 0 0 7>; 639 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 640 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 641 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 642 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 643 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 644 status = "disabled"; 645 }; 646 647 pcie_ep1: pcie-ep@3400000 { 648 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 649 reg = <0x00 0x03400000 0x0 0x00100000 650 0x80 0x00000000 0x8 0x00000000>; 651 reg-names = "regs", "addr_space"; 652 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 653 interrupt-names = "pme"; 654 num-ib-windows = <6>; 655 num-ob-windows = <8>; 656 status = "disabled"; 657 }; 658 659 pcie2: pcie@3500000 { 660 compatible = "fsl,ls1028a-pcie"; 661 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 662 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 663 reg-names = "regs", "config"; 664 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 666 interrupt-names = "pme", "aer"; 667 #address-cells = <3>; 668 #size-cells = <2>; 669 device_type = "pci"; 670 dma-coherent; 671 num-viewport = <8>; 672 bus-range = <0x0 0xff>; 673 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 674 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 675 msi-parent = <&its>; 676 #interrupt-cells = <1>; 677 interrupt-map-mask = <0 0 0 7>; 678 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 679 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 680 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 681 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 682 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 683 status = "disabled"; 684 }; 685 686 pcie_ep2: pcie-ep@3500000 { 687 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 688 reg = <0x00 0x03500000 0x0 0x00100000 689 0x88 0x00000000 0x8 0x00000000>; 690 reg-names = "regs", "addr_space"; 691 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 692 interrupt-names = "pme"; 693 num-ib-windows = <6>; 694 num-ob-windows = <8>; 695 status = "disabled"; 696 }; 697 698 smmu: iommu@5000000 { 699 compatible = "arm,mmu-500"; 700 reg = <0 0x5000000 0 0x800000>; 701 #global-interrupts = <8>; 702 #iommu-cells = <1>; 703 stream-match-mask = <0x7c00>; 704 /* global secure fault */ 705 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 706 /* combined secure interrupt */ 707 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 708 /* global non-secure fault */ 709 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 710 /* combined non-secure interrupt */ 711 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 712 /* performance counter interrupts 0-7 */ 713 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 715 /* per context interrupt, 64 interrupts */ 716 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 750 crypto: crypto@8000000 { 751 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 752 fsl,sec-era = <10>; 753 #address-cells = <1>; 754 #size-cells = <1>; 755 ranges = <0x0 0x00 0x8000000 0x100000>; 756 reg = <0x00 0x8000000 0x0 0x100000>; 757 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 758 dma-coherent; 759 760 sec_jr0: jr@10000 { 761 compatible = "fsl,sec-v5.0-job-ring", 762 "fsl,sec-v4.0-job-ring"; 763 reg = <0x10000 0x10000>; 764 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 765 }; 766 767 sec_jr1: jr@20000 { 768 compatible = "fsl,sec-v5.0-job-ring", 769 "fsl,sec-v4.0-job-ring"; 770 reg = <0x20000 0x10000>; 771 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 772 }; 773 774 sec_jr2: jr@30000 { 775 compatible = "fsl,sec-v5.0-job-ring", 776 "fsl,sec-v4.0-job-ring"; 777 reg = <0x30000 0x10000>; 778 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 779 }; 780 781 sec_jr3: jr@40000 { 782 compatible = "fsl,sec-v5.0-job-ring", 783 "fsl,sec-v4.0-job-ring"; 784 reg = <0x40000 0x10000>; 785 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 786 }; 787 }; 788 789 qdma: dma-controller@8380000 { 790 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 791 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 792 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 793 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 794 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-names = "qdma-error", "qdma-queue0", 800 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 801 dma-channels = <8>; 802 block-number = <1>; 803 block-offset = <0x10000>; 804 fsl,dma-queues = <2>; 805 status-sizes = <64>; 806 queue-sizes = <64 64>; 807 }; 808 809 cluster1_core0_watchdog: watchdog@c000000 { 810 compatible = "arm,sp805", "arm,primecell"; 811 reg = <0x0 0xc000000 0x0 0x1000>; 812 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 813 QORIQ_CLK_PLL_DIV(16)>, 814 <&clockgen QORIQ_CLK_PLATFORM_PLL 815 QORIQ_CLK_PLL_DIV(16)>; 816 clock-names = "wdog_clk", "apb_pclk"; 817 }; 818 819 cluster1_core1_watchdog: watchdog@c010000 { 820 compatible = "arm,sp805", "arm,primecell"; 821 reg = <0x0 0xc010000 0x0 0x1000>; 822 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 823 QORIQ_CLK_PLL_DIV(16)>, 824 <&clockgen QORIQ_CLK_PLATFORM_PLL 825 QORIQ_CLK_PLL_DIV(16)>; 826 clock-names = "wdog_clk", "apb_pclk"; 827 }; 828 829 malidp0: display@f080000 { 830 compatible = "arm,mali-dp500"; 831 reg = <0x0 0xf080000 0x0 0x10000>; 832 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 833 <0 223 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "DE", "SE"; 835 clocks = <&dpclk>, 836 <&clockgen QORIQ_CLK_HWACCEL 2>, 837 <&clockgen QORIQ_CLK_HWACCEL 2>, 838 <&clockgen QORIQ_CLK_HWACCEL 2>; 839 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 840 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 841 arm,malidp-arqos-value = <0xd000d000>; 842 843 port { 844 dpi0_out: endpoint { 845 846 }; 847 }; 848 }; 849 850 gpu: gpu@f0c0000 { 851 compatible = "vivante,gc"; 852 reg = <0x0 0xf0c0000 0x0 0x10000>; 853 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 855 <&clockgen QORIQ_CLK_HWACCEL 2>, 856 <&clockgen QORIQ_CLK_HWACCEL 2>; 857 clock-names = "core", "shader", "bus"; 858 #cooling-cells = <2>; 859 }; 860 861 sai1: audio-controller@f100000 { 862 #sound-dai-cells = <0>; 863 compatible = "fsl,vf610-sai"; 864 reg = <0x0 0xf100000 0x0 0x10000>; 865 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 867 QORIQ_CLK_PLL_DIV(2)>, 868 <&clockgen QORIQ_CLK_PLATFORM_PLL 869 QORIQ_CLK_PLL_DIV(2)>, 870 <&clockgen QORIQ_CLK_PLATFORM_PLL 871 QORIQ_CLK_PLL_DIV(2)>, 872 <&clockgen QORIQ_CLK_PLATFORM_PLL 873 QORIQ_CLK_PLL_DIV(2)>; 874 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 875 dma-names = "tx", "rx"; 876 dmas = <&edma0 1 4>, 877 <&edma0 1 3>; 878 fsl,sai-asynchronous; 879 status = "disabled"; 880 }; 881 882 sai2: audio-controller@f110000 { 883 #sound-dai-cells = <0>; 884 compatible = "fsl,vf610-sai"; 885 reg = <0x0 0xf110000 0x0 0x10000>; 886 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 888 QORIQ_CLK_PLL_DIV(2)>, 889 <&clockgen QORIQ_CLK_PLATFORM_PLL 890 QORIQ_CLK_PLL_DIV(2)>, 891 <&clockgen QORIQ_CLK_PLATFORM_PLL 892 QORIQ_CLK_PLL_DIV(2)>, 893 <&clockgen QORIQ_CLK_PLATFORM_PLL 894 QORIQ_CLK_PLL_DIV(2)>; 895 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 896 dma-names = "tx", "rx"; 897 dmas = <&edma0 1 6>, 898 <&edma0 1 5>; 899 fsl,sai-asynchronous; 900 status = "disabled"; 901 }; 902 903 sai3: audio-controller@f120000 { 904 #sound-dai-cells = <0>; 905 compatible = "fsl,vf610-sai"; 906 reg = <0x0 0xf120000 0x0 0x10000>; 907 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 909 QORIQ_CLK_PLL_DIV(2)>, 910 <&clockgen QORIQ_CLK_PLATFORM_PLL 911 QORIQ_CLK_PLL_DIV(2)>, 912 <&clockgen QORIQ_CLK_PLATFORM_PLL 913 QORIQ_CLK_PLL_DIV(2)>, 914 <&clockgen QORIQ_CLK_PLATFORM_PLL 915 QORIQ_CLK_PLL_DIV(2)>; 916 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 917 dma-names = "tx", "rx"; 918 dmas = <&edma0 1 8>, 919 <&edma0 1 7>; 920 fsl,sai-asynchronous; 921 status = "disabled"; 922 }; 923 924 sai4: audio-controller@f130000 { 925 #sound-dai-cells = <0>; 926 compatible = "fsl,vf610-sai"; 927 reg = <0x0 0xf130000 0x0 0x10000>; 928 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 930 QORIQ_CLK_PLL_DIV(2)>, 931 <&clockgen QORIQ_CLK_PLATFORM_PLL 932 QORIQ_CLK_PLL_DIV(2)>, 933 <&clockgen QORIQ_CLK_PLATFORM_PLL 934 QORIQ_CLK_PLL_DIV(2)>, 935 <&clockgen QORIQ_CLK_PLATFORM_PLL 936 QORIQ_CLK_PLL_DIV(2)>; 937 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 938 dma-names = "tx", "rx"; 939 dmas = <&edma0 1 10>, 940 <&edma0 1 9>; 941 fsl,sai-asynchronous; 942 status = "disabled"; 943 }; 944 945 sai5: audio-controller@f140000 { 946 #sound-dai-cells = <0>; 947 compatible = "fsl,vf610-sai"; 948 reg = <0x0 0xf140000 0x0 0x10000>; 949 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 951 QORIQ_CLK_PLL_DIV(2)>, 952 <&clockgen QORIQ_CLK_PLATFORM_PLL 953 QORIQ_CLK_PLL_DIV(2)>, 954 <&clockgen QORIQ_CLK_PLATFORM_PLL 955 QORIQ_CLK_PLL_DIV(2)>, 956 <&clockgen QORIQ_CLK_PLATFORM_PLL 957 QORIQ_CLK_PLL_DIV(2)>; 958 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 959 dma-names = "tx", "rx"; 960 dmas = <&edma0 1 12>, 961 <&edma0 1 11>; 962 fsl,sai-asynchronous; 963 status = "disabled"; 964 }; 965 966 sai6: audio-controller@f150000 { 967 #sound-dai-cells = <0>; 968 compatible = "fsl,vf610-sai"; 969 reg = <0x0 0xf150000 0x0 0x10000>; 970 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 972 QORIQ_CLK_PLL_DIV(2)>, 973 <&clockgen QORIQ_CLK_PLATFORM_PLL 974 QORIQ_CLK_PLL_DIV(2)>, 975 <&clockgen QORIQ_CLK_PLATFORM_PLL 976 QORIQ_CLK_PLL_DIV(2)>, 977 <&clockgen QORIQ_CLK_PLATFORM_PLL 978 QORIQ_CLK_PLL_DIV(2)>; 979 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 980 dma-names = "tx", "rx"; 981 dmas = <&edma0 1 14>, 982 <&edma0 1 13>; 983 fsl,sai-asynchronous; 984 status = "disabled"; 985 }; 986 987 dpclk: clock-controller@f1f0000 { 988 compatible = "fsl,ls1028a-plldig"; 989 reg = <0x0 0xf1f0000 0x0 0x10000>; 990 #clock-cells = <0>; 991 clocks = <&osc_27m>; 992 }; 993 994 tmu: tmu@1f80000 { 995 compatible = "fsl,qoriq-tmu"; 996 reg = <0x0 0x1f80000 0x0 0x10000>; 997 interrupts = <0 23 0x4>; 998 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 999 fsl,tmu-calibration = <0x00000000 0x00000024 1000 0x00000001 0x0000002b 1001 0x00000002 0x00000031 1002 0x00000003 0x00000038 1003 0x00000004 0x0000003f 1004 0x00000005 0x00000045 1005 0x00000006 0x0000004c 1006 0x00000007 0x00000053 1007 0x00000008 0x00000059 1008 0x00000009 0x00000060 1009 0x0000000a 0x00000066 1010 0x0000000b 0x0000006d 1011 1012 0x00010000 0x0000001c 1013 0x00010001 0x00000024 1014 0x00010002 0x0000002c 1015 0x00010003 0x00000035 1016 0x00010004 0x0000003d 1017 0x00010005 0x00000045 1018 0x00010006 0x0000004d 1019 0x00010007 0x00000055 1020 0x00010008 0x0000005e 1021 0x00010009 0x00000066 1022 0x0001000a 0x0000006e 1023 1024 0x00020000 0x00000018 1025 0x00020001 0x00000022 1026 0x00020002 0x0000002d 1027 0x00020003 0x00000038 1028 0x00020004 0x00000043 1029 0x00020005 0x0000004d 1030 0x00020006 0x00000058 1031 0x00020007 0x00000063 1032 0x00020008 0x0000006e 1033 1034 0x00030000 0x00000010 1035 0x00030001 0x0000001c 1036 0x00030002 0x00000029 1037 0x00030003 0x00000036 1038 0x00030004 0x00000042 1039 0x00030005 0x0000004f 1040 0x00030006 0x0000005b 1041 0x00030007 0x00000068>; 1042 little-endian; 1043 #thermal-sensor-cells = <1>; 1044 }; 1045 1046 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1047 compatible = "pci-host-ecam-generic"; 1048 reg = <0x01 0xf0000000 0x0 0x100000>; 1049 #address-cells = <3>; 1050 #size-cells = <2>; 1051 msi-parent = <&its>; 1052 device_type = "pci"; 1053 bus-range = <0x0 0x0>; 1054 dma-coherent; 1055 msi-map = <0 &its 0x17 0xe>; 1056 iommu-map = <0 &smmu 0x17 0xe>; 1057 /* PF0-6 BAR0 - non-prefetchable memory */ 1058 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1059 /* PF0-6 BAR2 - prefetchable memory */ 1060 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1061 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1062 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1063 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1064 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1065 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1066 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1067 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1068 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1069 /* BAR4 (PF5) - non-prefetchable memory */ 1070 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1071 1072 enetc_port0: ethernet@0,0 { 1073 compatible = "fsl,enetc"; 1074 reg = <0x000000 0 0 0 0>; 1075 status = "disabled"; 1076 }; 1077 1078 enetc_port1: ethernet@0,1 { 1079 compatible = "fsl,enetc"; 1080 reg = <0x000100 0 0 0 0>; 1081 status = "disabled"; 1082 }; 1083 1084 enetc_port2: ethernet@0,2 { 1085 compatible = "fsl,enetc"; 1086 reg = <0x000200 0 0 0 0>; 1087 phy-mode = "internal"; 1088 status = "disabled"; 1089 1090 fixed-link { 1091 speed = <2500>; 1092 full-duplex; 1093 pause; 1094 }; 1095 }; 1096 1097 enetc_mdio_pf3: mdio@0,3 { 1098 compatible = "fsl,enetc-mdio"; 1099 reg = <0x000300 0 0 0 0>; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 }; 1103 1104 ethernet@0,4 { 1105 compatible = "fsl,enetc-ptp"; 1106 reg = <0x000400 0 0 0 0>; 1107 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1108 little-endian; 1109 fsl,extts-fifo; 1110 }; 1111 1112 mscc_felix: ethernet-switch@0,5 { 1113 reg = <0x000500 0 0 0 0>; 1114 /* IEP INT_B */ 1115 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1116 status = "disabled"; 1117 1118 mscc_felix_ports: ports { 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 1122 /* External ports */ 1123 mscc_felix_port0: port@0 { 1124 reg = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 mscc_felix_port1: port@1 { 1129 reg = <1>; 1130 status = "disabled"; 1131 }; 1132 1133 mscc_felix_port2: port@2 { 1134 reg = <2>; 1135 status = "disabled"; 1136 }; 1137 1138 mscc_felix_port3: port@3 { 1139 reg = <3>; 1140 status = "disabled"; 1141 }; 1142 1143 /* Internal ports */ 1144 mscc_felix_port4: port@4 { 1145 reg = <4>; 1146 phy-mode = "internal"; 1147 status = "disabled"; 1148 1149 fixed-link { 1150 speed = <2500>; 1151 full-duplex; 1152 pause; 1153 }; 1154 }; 1155 1156 mscc_felix_port5: port@5 { 1157 reg = <5>; 1158 phy-mode = "internal"; 1159 status = "disabled"; 1160 1161 fixed-link { 1162 speed = <1000>; 1163 full-duplex; 1164 pause; 1165 }; 1166 }; 1167 }; 1168 }; 1169 1170 enetc_port3: ethernet@0,6 { 1171 compatible = "fsl,enetc"; 1172 reg = <0x000600 0 0 0 0>; 1173 phy-mode = "internal"; 1174 status = "disabled"; 1175 1176 fixed-link { 1177 speed = <1000>; 1178 full-duplex; 1179 pause; 1180 }; 1181 }; 1182 1183 rcec@1f,0 { 1184 reg = <0x00f800 0 0 0 0>; 1185 /* IEP INT_A */ 1186 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1187 }; 1188 }; 1189 1190 /* Integrated Endpoint Register Block */ 1191 ierb@1f0800000 { 1192 compatible = "fsl,ls1028a-enetc-ierb"; 1193 reg = <0x01 0xf0800000 0x0 0x10000>; 1194 }; 1195 1196 pwm0: pwm@2800000 { 1197 compatible = "fsl,vf610-ftm-pwm"; 1198 #pwm-cells = <3>; 1199 reg = <0x0 0x2800000 0x0 0x10000>; 1200 clock-names = "ftm_sys", "ftm_ext", 1201 "ftm_fix", "ftm_cnt_clk_en"; 1202 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1203 <&rtc_clk>, <&clockgen 4 1>; 1204 status = "disabled"; 1205 }; 1206 1207 pwm1: pwm@2810000 { 1208 compatible = "fsl,vf610-ftm-pwm"; 1209 #pwm-cells = <3>; 1210 reg = <0x0 0x2810000 0x0 0x10000>; 1211 clock-names = "ftm_sys", "ftm_ext", 1212 "ftm_fix", "ftm_cnt_clk_en"; 1213 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1214 <&rtc_clk>, <&clockgen 4 1>; 1215 status = "disabled"; 1216 }; 1217 1218 pwm2: pwm@2820000 { 1219 compatible = "fsl,vf610-ftm-pwm"; 1220 #pwm-cells = <3>; 1221 reg = <0x0 0x2820000 0x0 0x10000>; 1222 clock-names = "ftm_sys", "ftm_ext", 1223 "ftm_fix", "ftm_cnt_clk_en"; 1224 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1225 <&rtc_clk>, <&clockgen 4 1>; 1226 status = "disabled"; 1227 }; 1228 1229 pwm3: pwm@2830000 { 1230 compatible = "fsl,vf610-ftm-pwm"; 1231 #pwm-cells = <3>; 1232 reg = <0x0 0x2830000 0x0 0x10000>; 1233 clock-names = "ftm_sys", "ftm_ext", 1234 "ftm_fix", "ftm_cnt_clk_en"; 1235 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1236 <&rtc_clk>, <&clockgen 4 1>; 1237 status = "disabled"; 1238 }; 1239 1240 pwm4: pwm@2840000 { 1241 compatible = "fsl,vf610-ftm-pwm"; 1242 #pwm-cells = <3>; 1243 reg = <0x0 0x2840000 0x0 0x10000>; 1244 clock-names = "ftm_sys", "ftm_ext", 1245 "ftm_fix", "ftm_cnt_clk_en"; 1246 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1247 <&rtc_clk>, <&clockgen 4 1>; 1248 status = "disabled"; 1249 }; 1250 1251 pwm5: pwm@2850000 { 1252 compatible = "fsl,vf610-ftm-pwm"; 1253 #pwm-cells = <3>; 1254 reg = <0x0 0x2850000 0x0 0x10000>; 1255 clock-names = "ftm_sys", "ftm_ext", 1256 "ftm_fix", "ftm_cnt_clk_en"; 1257 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1258 <&rtc_clk>, <&clockgen 4 1>; 1259 status = "disabled"; 1260 }; 1261 1262 pwm6: pwm@2860000 { 1263 compatible = "fsl,vf610-ftm-pwm"; 1264 #pwm-cells = <3>; 1265 reg = <0x0 0x2860000 0x0 0x10000>; 1266 clock-names = "ftm_sys", "ftm_ext", 1267 "ftm_fix", "ftm_cnt_clk_en"; 1268 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1269 <&rtc_clk>, <&clockgen 4 1>; 1270 status = "disabled"; 1271 }; 1272 1273 pwm7: pwm@2870000 { 1274 compatible = "fsl,vf610-ftm-pwm"; 1275 #pwm-cells = <3>; 1276 reg = <0x0 0x2870000 0x0 0x10000>; 1277 clock-names = "ftm_sys", "ftm_ext", 1278 "ftm_fix", "ftm_cnt_clk_en"; 1279 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1280 <&rtc_clk>, <&clockgen 4 1>; 1281 status = "disabled"; 1282 }; 1283 1284 rcpm: power-controller@1e34040 { 1285 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1286 reg = <0x0 0x1e34040 0x0 0x1c>; 1287 #fsl,rcpm-wakeup-cells = <7>; 1288 little-endian; 1289 }; 1290 1291 ftm_alarm0: timer@2800000 { 1292 compatible = "fsl,ls1028a-ftm-alarm"; 1293 reg = <0x0 0x2800000 0x0 0x10000>; 1294 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1295 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1296 status = "disabled"; 1297 }; 1298 1299 ftm_alarm1: timer@2810000 { 1300 compatible = "fsl,ls1028a-ftm-alarm"; 1301 reg = <0x0 0x2810000 0x0 0x10000>; 1302 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1303 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1304 status = "disabled"; 1305 }; 1306 }; 1307 1308}; 1309