1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 next-level-cache = <&l2>; 32 cpu-idle-states = <&CPU_PW20>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a72"; 39 reg = <0x1>; 40 enable-method = "psci"; 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PW20>; 44 #cooling-cells = <2>; 45 }; 46 47 l2: l2-cache { 48 compatible = "cache"; 49 }; 50 }; 51 52 idle-states { 53 /* 54 * PSCI node is not added default, U-boot will add missing 55 * parts if it determines to use PSCI. 56 */ 57 entry-method = "psci"; 58 59 CPU_PW20: cpu-pw20 { 60 compatible = "arm,idle-state"; 61 idle-state-name = "PW20"; 62 arm,psci-suspend-param = <0x0>; 63 entry-latency-us = <2000>; 64 exit-latency-us = <2000>; 65 min-residency-us = <6000>; 66 }; 67 }; 68 69 rtc_clk: rtc-clk { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <32768>; 73 clock-output-names = "rtc_clk"; 74 }; 75 76 sysclk: sysclk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <100000000>; 80 clock-output-names = "sysclk"; 81 }; 82 83 osc_27m: clock-osc-27m { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <27000000>; 87 clock-output-names = "phy_27m"; 88 }; 89 90 firmware { 91 optee: optee { 92 compatible = "linaro,optee-tz"; 93 method = "smc"; 94 status = "disabled"; 95 }; 96 }; 97 98 reboot { 99 compatible ="syscon-reboot"; 100 regmap = <&rst>; 101 offset = <0>; 102 mask = <0x02>; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 108 IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 110 IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 112 IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 114 IRQ_TYPE_LEVEL_LOW)>; 115 }; 116 117 pmu { 118 compatible = "arm,cortex-a72-pmu"; 119 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 gic: interrupt-controller@6000000 { 123 compatible= "arm,gic-v3"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 129 #interrupt-cells= <3>; 130 interrupt-controller; 131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 132 IRQ_TYPE_LEVEL_LOW)>; 133 its: gic-its@6020000 { 134 compatible = "arm,gic-v3-its"; 135 msi-controller; 136 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 137 }; 138 }; 139 140 thermal-zones { 141 ddr-controller { 142 polling-delay-passive = <1000>; 143 polling-delay = <5000>; 144 thermal-sensors = <&tmu 0>; 145 146 trips { 147 ddr-ctrler-alert { 148 temperature = <85000>; 149 hysteresis = <2000>; 150 type = "passive"; 151 }; 152 153 ddr-ctrler-crit { 154 temperature = <95000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 }; 160 161 core-cluster { 162 polling-delay-passive = <1000>; 163 polling-delay = <5000>; 164 thermal-sensors = <&tmu 1>; 165 166 trips { 167 core_cluster_alert: core-cluster-alert { 168 temperature = <85000>; 169 hysteresis = <2000>; 170 type = "passive"; 171 }; 172 173 core_cluster_crit: core-cluster-crit { 174 temperature = <95000>; 175 hysteresis = <2000>; 176 type = "critical"; 177 }; 178 }; 179 180 cooling-maps { 181 map0 { 182 trip = <&core_cluster_alert>; 183 cooling-device = 184 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 186 }; 187 }; 188 }; 189 }; 190 191 soc: soc { 192 compatible = "simple-bus"; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 197 ddr: memory-controller@1080000 { 198 compatible = "fsl,qoriq-memory-controller"; 199 reg = <0x0 0x1080000 0x0 0x1000>; 200 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 201 little-endian; 202 }; 203 204 dcfg: syscon@1e00000 { 205 #address-cells = <1>; 206 #size-cells = <1>; 207 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 208 reg = <0x0 0x1e00000 0x0 0x10000>; 209 ranges = <0x0 0x0 0x1e00000 0x10000>; 210 little-endian; 211 212 fspi_clk: clock-controller@900 { 213 compatible = "fsl,ls1028a-flexspi-clk"; 214 reg = <0x900 0x4>; 215 #clock-cells = <0>; 216 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 217 clock-output-names = "fspi_clk"; 218 }; 219 }; 220 221 rst: syscon@1e60000 { 222 compatible = "syscon"; 223 reg = <0x0 0x1e60000 0x0 0x10000>; 224 little-endian; 225 }; 226 227 efuse@1e80000 { 228 compatible = "fsl,ls1028a-sfp"; 229 reg = <0x0 0x1e80000 0x0 0x10000>; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 233 ls1028a_uid: unique-id@1c { 234 reg = <0x1c 0x8>; 235 }; 236 }; 237 238 scfg: syscon@1fc0000 { 239 compatible = "fsl,ls1028a-scfg", "syscon"; 240 reg = <0x0 0x1fc0000 0x0 0x10000>; 241 big-endian; 242 }; 243 244 clockgen: clock-controller@1300000 { 245 compatible = "fsl,ls1028a-clockgen"; 246 reg = <0x0 0x1300000 0x0 0xa0000>; 247 #clock-cells = <2>; 248 clocks = <&sysclk>; 249 }; 250 251 i2c0: i2c@2000000 { 252 compatible = "fsl,vf610-i2c"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 reg = <0x0 0x2000000 0x0 0x10000>; 256 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 258 QORIQ_CLK_PLL_DIV(4)>; 259 status = "disabled"; 260 }; 261 262 i2c1: i2c@2010000 { 263 compatible = "fsl,vf610-i2c"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 reg = <0x0 0x2010000 0x0 0x10000>; 267 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 269 QORIQ_CLK_PLL_DIV(4)>; 270 status = "disabled"; 271 }; 272 273 i2c2: i2c@2020000 { 274 compatible = "fsl,vf610-i2c"; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 reg = <0x0 0x2020000 0x0 0x10000>; 278 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 280 QORIQ_CLK_PLL_DIV(4)>; 281 status = "disabled"; 282 }; 283 284 i2c3: i2c@2030000 { 285 compatible = "fsl,vf610-i2c"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0x0 0x2030000 0x0 0x10000>; 289 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 291 QORIQ_CLK_PLL_DIV(4)>; 292 status = "disabled"; 293 }; 294 295 i2c4: i2c@2040000 { 296 compatible = "fsl,vf610-i2c"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x2040000 0x0 0x10000>; 300 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 302 QORIQ_CLK_PLL_DIV(4)>; 303 status = "disabled"; 304 }; 305 306 i2c5: i2c@2050000 { 307 compatible = "fsl,vf610-i2c"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 reg = <0x0 0x2050000 0x0 0x10000>; 311 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 313 QORIQ_CLK_PLL_DIV(4)>; 314 status = "disabled"; 315 }; 316 317 i2c6: i2c@2060000 { 318 compatible = "fsl,vf610-i2c"; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 reg = <0x0 0x2060000 0x0 0x10000>; 322 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 324 QORIQ_CLK_PLL_DIV(4)>; 325 status = "disabled"; 326 }; 327 328 i2c7: i2c@2070000 { 329 compatible = "fsl,vf610-i2c"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 reg = <0x0 0x2070000 0x0 0x10000>; 333 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 335 QORIQ_CLK_PLL_DIV(4)>; 336 status = "disabled"; 337 }; 338 339 fspi: spi@20c0000 { 340 compatible = "nxp,lx2160a-fspi"; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 reg = <0x0 0x20c0000 0x0 0x10000>, 344 <0x0 0x20000000 0x0 0x10000000>; 345 reg-names = "fspi_base", "fspi_mmap"; 346 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&fspi_clk>, <&fspi_clk>; 348 clock-names = "fspi_en", "fspi"; 349 status = "disabled"; 350 }; 351 352 dspi0: spi@2100000 { 353 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 reg = <0x0 0x2100000 0x0 0x10000>; 357 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 358 clock-names = "dspi"; 359 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 360 QORIQ_CLK_PLL_DIV(2)>; 361 dmas = <&edma0 0 62>, <&edma0 0 60>; 362 dma-names = "tx", "rx"; 363 spi-num-chipselects = <4>; 364 little-endian; 365 status = "disabled"; 366 }; 367 368 dspi1: spi@2110000 { 369 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 reg = <0x0 0x2110000 0x0 0x10000>; 373 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 374 clock-names = "dspi"; 375 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 376 QORIQ_CLK_PLL_DIV(2)>; 377 dmas = <&edma0 0 58>, <&edma0 0 56>; 378 dma-names = "tx", "rx"; 379 spi-num-chipselects = <4>; 380 little-endian; 381 status = "disabled"; 382 }; 383 384 dspi2: spi@2120000 { 385 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <0x0 0x2120000 0x0 0x10000>; 389 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 390 clock-names = "dspi"; 391 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 392 QORIQ_CLK_PLL_DIV(2)>; 393 dmas = <&edma0 0 54>, <&edma0 0 2>; 394 dma-names = "tx", "rx"; 395 spi-num-chipselects = <3>; 396 little-endian; 397 status = "disabled"; 398 }; 399 400 esdhc: mmc@2140000 { 401 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 402 reg = <0x0 0x2140000 0x0 0x10000>; 403 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 404 clock-frequency = <0>; /* fixed up by bootloader */ 405 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 406 voltage-ranges = <1800 1800 3300 3300>; 407 sdhci,auto-cmd12; 408 little-endian; 409 bus-width = <4>; 410 status = "disabled"; 411 }; 412 413 esdhc1: mmc@2150000 { 414 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 415 reg = <0x0 0x2150000 0x0 0x10000>; 416 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 417 clock-frequency = <0>; /* fixed up by bootloader */ 418 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 419 voltage-ranges = <1800 1800>; 420 sdhci,auto-cmd12; 421 non-removable; 422 little-endian; 423 bus-width = <4>; 424 status = "disabled"; 425 }; 426 427 can0: can@2180000 { 428 compatible = "fsl,lx2160ar1-flexcan"; 429 reg = <0x0 0x2180000 0x0 0x10000>; 430 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 432 QORIQ_CLK_PLL_DIV(2)>, 433 <&clockgen QORIQ_CLK_PLATFORM_PLL 434 QORIQ_CLK_PLL_DIV(2)>; 435 clock-names = "ipg", "per"; 436 status = "disabled"; 437 }; 438 439 can1: can@2190000 { 440 compatible = "fsl,lx2160ar1-flexcan"; 441 reg = <0x0 0x2190000 0x0 0x10000>; 442 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 444 QORIQ_CLK_PLL_DIV(2)>, 445 <&clockgen QORIQ_CLK_PLATFORM_PLL 446 QORIQ_CLK_PLL_DIV(2)>; 447 clock-names = "ipg", "per"; 448 status = "disabled"; 449 }; 450 451 duart0: serial@21c0500 { 452 compatible = "fsl,ns16550", "ns16550a"; 453 reg = <0x00 0x21c0500 0x0 0x100>; 454 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 456 QORIQ_CLK_PLL_DIV(2)>; 457 status = "disabled"; 458 }; 459 460 duart1: serial@21c0600 { 461 compatible = "fsl,ns16550", "ns16550a"; 462 reg = <0x00 0x21c0600 0x0 0x100>; 463 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 465 QORIQ_CLK_PLL_DIV(2)>; 466 status = "disabled"; 467 }; 468 469 470 lpuart0: serial@2260000 { 471 compatible = "fsl,ls1028a-lpuart"; 472 reg = <0x0 0x2260000 0x0 0x1000>; 473 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 475 QORIQ_CLK_PLL_DIV(2)>; 476 clock-names = "ipg"; 477 dma-names = "rx","tx"; 478 dmas = <&edma0 1 32>, 479 <&edma0 1 33>; 480 status = "disabled"; 481 }; 482 483 lpuart1: serial@2270000 { 484 compatible = "fsl,ls1028a-lpuart"; 485 reg = <0x0 0x2270000 0x0 0x1000>; 486 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 488 QORIQ_CLK_PLL_DIV(2)>; 489 clock-names = "ipg"; 490 dma-names = "rx","tx"; 491 dmas = <&edma0 1 30>, 492 <&edma0 1 31>; 493 status = "disabled"; 494 }; 495 496 lpuart2: serial@2280000 { 497 compatible = "fsl,ls1028a-lpuart"; 498 reg = <0x0 0x2280000 0x0 0x1000>; 499 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 501 QORIQ_CLK_PLL_DIV(2)>; 502 clock-names = "ipg"; 503 dma-names = "rx","tx"; 504 dmas = <&edma0 1 28>, 505 <&edma0 1 29>; 506 status = "disabled"; 507 }; 508 509 lpuart3: serial@2290000 { 510 compatible = "fsl,ls1028a-lpuart"; 511 reg = <0x0 0x2290000 0x0 0x1000>; 512 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 514 QORIQ_CLK_PLL_DIV(2)>; 515 clock-names = "ipg"; 516 dma-names = "rx","tx"; 517 dmas = <&edma0 1 26>, 518 <&edma0 1 27>; 519 status = "disabled"; 520 }; 521 522 lpuart4: serial@22a0000 { 523 compatible = "fsl,ls1028a-lpuart"; 524 reg = <0x0 0x22a0000 0x0 0x1000>; 525 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 527 QORIQ_CLK_PLL_DIV(2)>; 528 clock-names = "ipg"; 529 dma-names = "rx","tx"; 530 dmas = <&edma0 1 24>, 531 <&edma0 1 25>; 532 status = "disabled"; 533 }; 534 535 lpuart5: serial@22b0000 { 536 compatible = "fsl,ls1028a-lpuart"; 537 reg = <0x0 0x22b0000 0x0 0x1000>; 538 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 540 QORIQ_CLK_PLL_DIV(2)>; 541 clock-names = "ipg"; 542 dma-names = "rx","tx"; 543 dmas = <&edma0 1 22>, 544 <&edma0 1 23>; 545 status = "disabled"; 546 }; 547 548 edma0: dma-controller@22c0000 { 549 #dma-cells = <2>; 550 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 551 reg = <0x0 0x22c0000 0x0 0x10000>, 552 <0x0 0x22d0000 0x0 0x10000>, 553 <0x0 0x22e0000 0x0 0x10000>; 554 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 556 interrupt-names = "edma-tx", "edma-err"; 557 dma-channels = <32>; 558 clock-names = "dmamux0", "dmamux1"; 559 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 560 QORIQ_CLK_PLL_DIV(2)>, 561 <&clockgen QORIQ_CLK_PLATFORM_PLL 562 QORIQ_CLK_PLL_DIV(2)>; 563 }; 564 565 gpio1: gpio@2300000 { 566 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 567 reg = <0x0 0x2300000 0x0 0x10000>; 568 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 569 gpio-controller; 570 #gpio-cells = <2>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 little-endian; 574 }; 575 576 gpio2: gpio@2310000 { 577 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 578 reg = <0x0 0x2310000 0x0 0x10000>; 579 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 580 gpio-controller; 581 #gpio-cells = <2>; 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 little-endian; 585 }; 586 587 gpio3: gpio@2320000 { 588 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 589 reg = <0x0 0x2320000 0x0 0x10000>; 590 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 little-endian; 596 }; 597 598 usb0: usb@3100000 { 599 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 600 reg = <0x0 0x3100000 0x0 0x10000>; 601 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 602 dr_mode = "host"; 603 snps,dis_rxdet_inp3_quirk; 604 snps,quirk-frame-length-adjustment = <0x20>; 605 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 606 status = "disabled"; 607 }; 608 609 usb1: usb@3110000 { 610 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 611 reg = <0x0 0x3110000 0x0 0x10000>; 612 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 613 dr_mode = "host"; 614 snps,dis_rxdet_inp3_quirk; 615 snps,quirk-frame-length-adjustment = <0x20>; 616 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 617 status = "disabled"; 618 }; 619 620 sata: sata@3200000 { 621 compatible = "fsl,ls1028a-ahci"; 622 reg = <0x0 0x3200000 0x0 0x10000>, 623 <0x7 0x100520 0x0 0x4>; 624 reg-names = "ahci", "sata-ecc"; 625 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 627 QORIQ_CLK_PLL_DIV(2)>; 628 status = "disabled"; 629 }; 630 631 pcie1: pcie@3400000 { 632 compatible = "fsl,ls1028a-pcie"; 633 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 634 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 635 reg-names = "regs", "config"; 636 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 637 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 638 interrupt-names = "pme", "aer"; 639 #address-cells = <3>; 640 #size-cells = <2>; 641 device_type = "pci"; 642 dma-coherent; 643 num-viewport = <8>; 644 bus-range = <0x0 0xff>; 645 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 646 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 647 msi-parent = <&its>; 648 #interrupt-cells = <1>; 649 interrupt-map-mask = <0 0 0 7>; 650 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 651 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 652 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 653 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 654 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 655 status = "disabled"; 656 }; 657 658 pcie_ep1: pcie-ep@3400000 { 659 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 660 reg = <0x00 0x03400000 0x0 0x00100000 661 0x80 0x00000000 0x8 0x00000000>; 662 reg-names = "regs", "addr_space"; 663 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 664 interrupt-names = "pme"; 665 num-ib-windows = <6>; 666 num-ob-windows = <8>; 667 status = "disabled"; 668 }; 669 670 pcie2: pcie@3500000 { 671 compatible = "fsl,ls1028a-pcie"; 672 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 673 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 674 reg-names = "regs", "config"; 675 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 677 interrupt-names = "pme", "aer"; 678 #address-cells = <3>; 679 #size-cells = <2>; 680 device_type = "pci"; 681 dma-coherent; 682 num-viewport = <8>; 683 bus-range = <0x0 0xff>; 684 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 685 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 686 msi-parent = <&its>; 687 #interrupt-cells = <1>; 688 interrupt-map-mask = <0 0 0 7>; 689 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 690 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 691 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 692 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 693 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 694 status = "disabled"; 695 }; 696 697 pcie_ep2: pcie-ep@3500000 { 698 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 699 reg = <0x00 0x03500000 0x0 0x00100000 700 0x88 0x00000000 0x8 0x00000000>; 701 reg-names = "regs", "addr_space"; 702 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 703 interrupt-names = "pme"; 704 num-ib-windows = <6>; 705 num-ob-windows = <8>; 706 status = "disabled"; 707 }; 708 709 smmu: iommu@5000000 { 710 compatible = "arm,mmu-500"; 711 reg = <0 0x5000000 0 0x800000>; 712 #global-interrupts = <8>; 713 #iommu-cells = <1>; 714 stream-match-mask = <0x7c00>; 715 /* global secure fault */ 716 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 717 /* combined secure interrupt */ 718 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 719 /* global non-secure fault */ 720 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 721 /* combined non-secure interrupt */ 722 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 723 /* performance counter interrupts 0-7 */ 724 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 726 /* per context interrupt, 64 interrupts */ 727 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 759 }; 760 761 crypto: crypto@8000000 { 762 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 763 fsl,sec-era = <10>; 764 #address-cells = <1>; 765 #size-cells = <1>; 766 ranges = <0x0 0x00 0x8000000 0x100000>; 767 reg = <0x00 0x8000000 0x0 0x100000>; 768 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 769 dma-coherent; 770 771 sec_jr0: jr@10000 { 772 compatible = "fsl,sec-v5.0-job-ring", 773 "fsl,sec-v4.0-job-ring"; 774 reg = <0x10000 0x10000>; 775 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 776 }; 777 778 sec_jr1: jr@20000 { 779 compatible = "fsl,sec-v5.0-job-ring", 780 "fsl,sec-v4.0-job-ring"; 781 reg = <0x20000 0x10000>; 782 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 783 }; 784 785 sec_jr2: jr@30000 { 786 compatible = "fsl,sec-v5.0-job-ring", 787 "fsl,sec-v4.0-job-ring"; 788 reg = <0x30000 0x10000>; 789 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 790 }; 791 792 sec_jr3: jr@40000 { 793 compatible = "fsl,sec-v5.0-job-ring", 794 "fsl,sec-v4.0-job-ring"; 795 reg = <0x40000 0x10000>; 796 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 797 }; 798 }; 799 800 qdma: dma-controller@8380000 { 801 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 802 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 803 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 804 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 805 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "qdma-error", "qdma-queue0", 811 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 812 dma-channels = <8>; 813 block-number = <1>; 814 block-offset = <0x10000>; 815 fsl,dma-queues = <2>; 816 status-sizes = <64>; 817 queue-sizes = <64 64>; 818 }; 819 820 cluster1_core0_watchdog: watchdog@c000000 { 821 compatible = "arm,sp805", "arm,primecell"; 822 reg = <0x0 0xc000000 0x0 0x1000>; 823 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 824 QORIQ_CLK_PLL_DIV(16)>, 825 <&clockgen QORIQ_CLK_PLATFORM_PLL 826 QORIQ_CLK_PLL_DIV(16)>; 827 clock-names = "wdog_clk", "apb_pclk"; 828 }; 829 830 cluster1_core1_watchdog: watchdog@c010000 { 831 compatible = "arm,sp805", "arm,primecell"; 832 reg = <0x0 0xc010000 0x0 0x1000>; 833 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 834 QORIQ_CLK_PLL_DIV(16)>, 835 <&clockgen QORIQ_CLK_PLATFORM_PLL 836 QORIQ_CLK_PLL_DIV(16)>; 837 clock-names = "wdog_clk", "apb_pclk"; 838 }; 839 840 malidp0: display@f080000 { 841 compatible = "arm,mali-dp500"; 842 reg = <0x0 0xf080000 0x0 0x10000>; 843 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 844 <0 223 IRQ_TYPE_LEVEL_HIGH>; 845 interrupt-names = "DE", "SE"; 846 clocks = <&dpclk>, 847 <&clockgen QORIQ_CLK_HWACCEL 2>, 848 <&clockgen QORIQ_CLK_HWACCEL 2>, 849 <&clockgen QORIQ_CLK_HWACCEL 2>; 850 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 851 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 852 arm,malidp-arqos-value = <0xd000d000>; 853 854 port { 855 dpi0_out: endpoint { 856 857 }; 858 }; 859 }; 860 861 gpu: gpu@f0c0000 { 862 compatible = "vivante,gc"; 863 reg = <0x0 0xf0c0000 0x0 0x10000>; 864 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 866 <&clockgen QORIQ_CLK_HWACCEL 2>, 867 <&clockgen QORIQ_CLK_HWACCEL 2>; 868 clock-names = "core", "shader", "bus"; 869 #cooling-cells = <2>; 870 }; 871 872 sai1: audio-controller@f100000 { 873 #sound-dai-cells = <0>; 874 compatible = "fsl,vf610-sai"; 875 reg = <0x0 0xf100000 0x0 0x10000>; 876 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 878 QORIQ_CLK_PLL_DIV(2)>, 879 <&clockgen QORIQ_CLK_PLATFORM_PLL 880 QORIQ_CLK_PLL_DIV(2)>, 881 <&clockgen QORIQ_CLK_PLATFORM_PLL 882 QORIQ_CLK_PLL_DIV(2)>, 883 <&clockgen QORIQ_CLK_PLATFORM_PLL 884 QORIQ_CLK_PLL_DIV(2)>; 885 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 886 dma-names = "tx", "rx"; 887 dmas = <&edma0 1 4>, 888 <&edma0 1 3>; 889 fsl,sai-asynchronous; 890 status = "disabled"; 891 }; 892 893 sai2: audio-controller@f110000 { 894 #sound-dai-cells = <0>; 895 compatible = "fsl,vf610-sai"; 896 reg = <0x0 0xf110000 0x0 0x10000>; 897 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 899 QORIQ_CLK_PLL_DIV(2)>, 900 <&clockgen QORIQ_CLK_PLATFORM_PLL 901 QORIQ_CLK_PLL_DIV(2)>, 902 <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>, 904 <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(2)>; 906 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 907 dma-names = "tx", "rx"; 908 dmas = <&edma0 1 6>, 909 <&edma0 1 5>; 910 fsl,sai-asynchronous; 911 status = "disabled"; 912 }; 913 914 sai3: audio-controller@f120000 { 915 #sound-dai-cells = <0>; 916 compatible = "fsl,vf610-sai"; 917 reg = <0x0 0xf120000 0x0 0x10000>; 918 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 920 QORIQ_CLK_PLL_DIV(2)>, 921 <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(2)>, 923 <&clockgen QORIQ_CLK_PLATFORM_PLL 924 QORIQ_CLK_PLL_DIV(2)>, 925 <&clockgen QORIQ_CLK_PLATFORM_PLL 926 QORIQ_CLK_PLL_DIV(2)>; 927 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 928 dma-names = "tx", "rx"; 929 dmas = <&edma0 1 8>, 930 <&edma0 1 7>; 931 fsl,sai-asynchronous; 932 status = "disabled"; 933 }; 934 935 sai4: audio-controller@f130000 { 936 #sound-dai-cells = <0>; 937 compatible = "fsl,vf610-sai"; 938 reg = <0x0 0xf130000 0x0 0x10000>; 939 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 941 QORIQ_CLK_PLL_DIV(2)>, 942 <&clockgen QORIQ_CLK_PLATFORM_PLL 943 QORIQ_CLK_PLL_DIV(2)>, 944 <&clockgen QORIQ_CLK_PLATFORM_PLL 945 QORIQ_CLK_PLL_DIV(2)>, 946 <&clockgen QORIQ_CLK_PLATFORM_PLL 947 QORIQ_CLK_PLL_DIV(2)>; 948 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 949 dma-names = "tx", "rx"; 950 dmas = <&edma0 1 10>, 951 <&edma0 1 9>; 952 fsl,sai-asynchronous; 953 status = "disabled"; 954 }; 955 956 sai5: audio-controller@f140000 { 957 #sound-dai-cells = <0>; 958 compatible = "fsl,vf610-sai"; 959 reg = <0x0 0xf140000 0x0 0x10000>; 960 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 962 QORIQ_CLK_PLL_DIV(2)>, 963 <&clockgen QORIQ_CLK_PLATFORM_PLL 964 QORIQ_CLK_PLL_DIV(2)>, 965 <&clockgen QORIQ_CLK_PLATFORM_PLL 966 QORIQ_CLK_PLL_DIV(2)>, 967 <&clockgen QORIQ_CLK_PLATFORM_PLL 968 QORIQ_CLK_PLL_DIV(2)>; 969 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 970 dma-names = "tx", "rx"; 971 dmas = <&edma0 1 12>, 972 <&edma0 1 11>; 973 fsl,sai-asynchronous; 974 status = "disabled"; 975 }; 976 977 sai6: audio-controller@f150000 { 978 #sound-dai-cells = <0>; 979 compatible = "fsl,vf610-sai"; 980 reg = <0x0 0xf150000 0x0 0x10000>; 981 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 983 QORIQ_CLK_PLL_DIV(2)>, 984 <&clockgen QORIQ_CLK_PLATFORM_PLL 985 QORIQ_CLK_PLL_DIV(2)>, 986 <&clockgen QORIQ_CLK_PLATFORM_PLL 987 QORIQ_CLK_PLL_DIV(2)>, 988 <&clockgen QORIQ_CLK_PLATFORM_PLL 989 QORIQ_CLK_PLL_DIV(2)>; 990 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 991 dma-names = "tx", "rx"; 992 dmas = <&edma0 1 14>, 993 <&edma0 1 13>; 994 fsl,sai-asynchronous; 995 status = "disabled"; 996 }; 997 998 dpclk: clock-controller@f1f0000 { 999 compatible = "fsl,ls1028a-plldig"; 1000 reg = <0x0 0xf1f0000 0x0 0x10000>; 1001 #clock-cells = <0>; 1002 clocks = <&osc_27m>; 1003 }; 1004 1005 tmu: tmu@1f80000 { 1006 compatible = "fsl,qoriq-tmu"; 1007 reg = <0x0 0x1f80000 0x0 0x10000>; 1008 interrupts = <0 23 0x4>; 1009 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1010 fsl,tmu-calibration = <0x00000000 0x00000024 1011 0x00000001 0x0000002b 1012 0x00000002 0x00000031 1013 0x00000003 0x00000038 1014 0x00000004 0x0000003f 1015 0x00000005 0x00000045 1016 0x00000006 0x0000004c 1017 0x00000007 0x00000053 1018 0x00000008 0x00000059 1019 0x00000009 0x00000060 1020 0x0000000a 0x00000066 1021 0x0000000b 0x0000006d 1022 1023 0x00010000 0x0000001c 1024 0x00010001 0x00000024 1025 0x00010002 0x0000002c 1026 0x00010003 0x00000035 1027 0x00010004 0x0000003d 1028 0x00010005 0x00000045 1029 0x00010006 0x0000004d 1030 0x00010007 0x00000055 1031 0x00010008 0x0000005e 1032 0x00010009 0x00000066 1033 0x0001000a 0x0000006e 1034 1035 0x00020000 0x00000018 1036 0x00020001 0x00000022 1037 0x00020002 0x0000002d 1038 0x00020003 0x00000038 1039 0x00020004 0x00000043 1040 0x00020005 0x0000004d 1041 0x00020006 0x00000058 1042 0x00020007 0x00000063 1043 0x00020008 0x0000006e 1044 1045 0x00030000 0x00000010 1046 0x00030001 0x0000001c 1047 0x00030002 0x00000029 1048 0x00030003 0x00000036 1049 0x00030004 0x00000042 1050 0x00030005 0x0000004f 1051 0x00030006 0x0000005b 1052 0x00030007 0x00000068>; 1053 little-endian; 1054 #thermal-sensor-cells = <1>; 1055 }; 1056 1057 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1058 compatible = "pci-host-ecam-generic"; 1059 reg = <0x01 0xf0000000 0x0 0x100000>; 1060 #address-cells = <3>; 1061 #size-cells = <2>; 1062 msi-parent = <&its>; 1063 device_type = "pci"; 1064 bus-range = <0x0 0x0>; 1065 dma-coherent; 1066 msi-map = <0 &its 0x17 0xe>; 1067 iommu-map = <0 &smmu 0x17 0xe>; 1068 /* PF0-6 BAR0 - non-prefetchable memory */ 1069 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1070 /* PF0-6 BAR2 - prefetchable memory */ 1071 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1072 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1073 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1074 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1075 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1076 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1077 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1078 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1079 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1080 /* BAR4 (PF5) - non-prefetchable memory */ 1081 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1082 1083 enetc_port0: ethernet@0,0 { 1084 compatible = "fsl,enetc"; 1085 reg = <0x000000 0 0 0 0>; 1086 status = "disabled"; 1087 }; 1088 1089 enetc_port1: ethernet@0,1 { 1090 compatible = "fsl,enetc"; 1091 reg = <0x000100 0 0 0 0>; 1092 status = "disabled"; 1093 }; 1094 1095 enetc_port2: ethernet@0,2 { 1096 compatible = "fsl,enetc"; 1097 reg = <0x000200 0 0 0 0>; 1098 phy-mode = "internal"; 1099 status = "disabled"; 1100 1101 fixed-link { 1102 speed = <2500>; 1103 full-duplex; 1104 pause; 1105 }; 1106 }; 1107 1108 enetc_mdio_pf3: mdio@0,3 { 1109 compatible = "fsl,enetc-mdio"; 1110 reg = <0x000300 0 0 0 0>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 }; 1114 1115 ethernet@0,4 { 1116 compatible = "fsl,enetc-ptp"; 1117 reg = <0x000400 0 0 0 0>; 1118 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1119 little-endian; 1120 fsl,extts-fifo; 1121 }; 1122 1123 mscc_felix: ethernet-switch@0,5 { 1124 reg = <0x000500 0 0 0 0>; 1125 /* IEP INT_B */ 1126 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1127 status = "disabled"; 1128 1129 mscc_felix_ports: ports { 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 1133 /* External ports */ 1134 mscc_felix_port0: port@0 { 1135 reg = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 mscc_felix_port1: port@1 { 1140 reg = <1>; 1141 status = "disabled"; 1142 }; 1143 1144 mscc_felix_port2: port@2 { 1145 reg = <2>; 1146 status = "disabled"; 1147 }; 1148 1149 mscc_felix_port3: port@3 { 1150 reg = <3>; 1151 status = "disabled"; 1152 }; 1153 1154 /* Internal ports */ 1155 mscc_felix_port4: port@4 { 1156 reg = <4>; 1157 phy-mode = "internal"; 1158 status = "disabled"; 1159 1160 fixed-link { 1161 speed = <2500>; 1162 full-duplex; 1163 pause; 1164 }; 1165 }; 1166 1167 mscc_felix_port5: port@5 { 1168 reg = <5>; 1169 phy-mode = "internal"; 1170 status = "disabled"; 1171 1172 fixed-link { 1173 speed = <1000>; 1174 full-duplex; 1175 pause; 1176 }; 1177 }; 1178 }; 1179 }; 1180 1181 enetc_port3: ethernet@0,6 { 1182 compatible = "fsl,enetc"; 1183 reg = <0x000600 0 0 0 0>; 1184 phy-mode = "internal"; 1185 status = "disabled"; 1186 1187 fixed-link { 1188 speed = <1000>; 1189 full-duplex; 1190 pause; 1191 }; 1192 }; 1193 1194 rcec@1f,0 { 1195 reg = <0x00f800 0 0 0 0>; 1196 /* IEP INT_A */ 1197 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1198 }; 1199 }; 1200 1201 /* Integrated Endpoint Register Block */ 1202 ierb@1f0800000 { 1203 compatible = "fsl,ls1028a-enetc-ierb"; 1204 reg = <0x01 0xf0800000 0x0 0x10000>; 1205 }; 1206 1207 pwm0: pwm@2800000 { 1208 compatible = "fsl,vf610-ftm-pwm"; 1209 #pwm-cells = <3>; 1210 reg = <0x0 0x2800000 0x0 0x10000>; 1211 clock-names = "ftm_sys", "ftm_ext", 1212 "ftm_fix", "ftm_cnt_clk_en"; 1213 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1214 <&rtc_clk>, <&clockgen 4 1>; 1215 status = "disabled"; 1216 }; 1217 1218 pwm1: pwm@2810000 { 1219 compatible = "fsl,vf610-ftm-pwm"; 1220 #pwm-cells = <3>; 1221 reg = <0x0 0x2810000 0x0 0x10000>; 1222 clock-names = "ftm_sys", "ftm_ext", 1223 "ftm_fix", "ftm_cnt_clk_en"; 1224 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1225 <&rtc_clk>, <&clockgen 4 1>; 1226 status = "disabled"; 1227 }; 1228 1229 pwm2: pwm@2820000 { 1230 compatible = "fsl,vf610-ftm-pwm"; 1231 #pwm-cells = <3>; 1232 reg = <0x0 0x2820000 0x0 0x10000>; 1233 clock-names = "ftm_sys", "ftm_ext", 1234 "ftm_fix", "ftm_cnt_clk_en"; 1235 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1236 <&rtc_clk>, <&clockgen 4 1>; 1237 status = "disabled"; 1238 }; 1239 1240 pwm3: pwm@2830000 { 1241 compatible = "fsl,vf610-ftm-pwm"; 1242 #pwm-cells = <3>; 1243 reg = <0x0 0x2830000 0x0 0x10000>; 1244 clock-names = "ftm_sys", "ftm_ext", 1245 "ftm_fix", "ftm_cnt_clk_en"; 1246 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1247 <&rtc_clk>, <&clockgen 4 1>; 1248 status = "disabled"; 1249 }; 1250 1251 pwm4: pwm@2840000 { 1252 compatible = "fsl,vf610-ftm-pwm"; 1253 #pwm-cells = <3>; 1254 reg = <0x0 0x2840000 0x0 0x10000>; 1255 clock-names = "ftm_sys", "ftm_ext", 1256 "ftm_fix", "ftm_cnt_clk_en"; 1257 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1258 <&rtc_clk>, <&clockgen 4 1>; 1259 status = "disabled"; 1260 }; 1261 1262 pwm5: pwm@2850000 { 1263 compatible = "fsl,vf610-ftm-pwm"; 1264 #pwm-cells = <3>; 1265 reg = <0x0 0x2850000 0x0 0x10000>; 1266 clock-names = "ftm_sys", "ftm_ext", 1267 "ftm_fix", "ftm_cnt_clk_en"; 1268 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1269 <&rtc_clk>, <&clockgen 4 1>; 1270 status = "disabled"; 1271 }; 1272 1273 pwm6: pwm@2860000 { 1274 compatible = "fsl,vf610-ftm-pwm"; 1275 #pwm-cells = <3>; 1276 reg = <0x0 0x2860000 0x0 0x10000>; 1277 clock-names = "ftm_sys", "ftm_ext", 1278 "ftm_fix", "ftm_cnt_clk_en"; 1279 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1280 <&rtc_clk>, <&clockgen 4 1>; 1281 status = "disabled"; 1282 }; 1283 1284 pwm7: pwm@2870000 { 1285 compatible = "fsl,vf610-ftm-pwm"; 1286 #pwm-cells = <3>; 1287 reg = <0x0 0x2870000 0x0 0x10000>; 1288 clock-names = "ftm_sys", "ftm_ext", 1289 "ftm_fix", "ftm_cnt_clk_en"; 1290 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1291 <&rtc_clk>, <&clockgen 4 1>; 1292 status = "disabled"; 1293 }; 1294 1295 rcpm: power-controller@1e34040 { 1296 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1297 reg = <0x0 0x1e34040 0x0 0x1c>; 1298 #fsl,rcpm-wakeup-cells = <7>; 1299 little-endian; 1300 }; 1301 1302 ftm_alarm0: timer@2800000 { 1303 compatible = "fsl,ls1028a-ftm-alarm"; 1304 reg = <0x0 0x2800000 0x0 0x10000>; 1305 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1306 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1307 status = "disabled"; 1308 }; 1309 1310 ftm_alarm1: timer@2810000 { 1311 compatible = "fsl,ls1028a-ftm-alarm"; 1312 reg = <0x0 0x2810000 0x0 0x10000>; 1313 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1314 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1315 status = "disabled"; 1316 }; 1317 }; 1318 1319}; 1320