1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a72"; 38 reg = <0x1>; 39 enable-method = "psci"; 40 clocks = <&clockgen 1 0>; 41 next-level-cache = <&l2>; 42 cpu-idle-states = <&CPU_PW20>; 43 #cooling-cells = <2>; 44 }; 45 46 l2: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 idle-states { 52 /* 53 * PSCI node is not added default, U-boot will add missing 54 * parts if it determines to use PSCI. 55 */ 56 entry-method = "arm,psci"; 57 58 CPU_PW20: cpu-pw20 { 59 compatible = "arm,idle-state"; 60 idle-state-name = "PW20"; 61 arm,psci-suspend-param = <0x0>; 62 entry-latency-us = <2000>; 63 exit-latency-us = <2000>; 64 min-residency-us = <6000>; 65 }; 66 }; 67 68 sysclk: clock-sysclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "sysclk"; 73 }; 74 75 osc_27m: clock-osc-27m { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <27000000>; 79 clock-output-names = "phy_27m"; 80 }; 81 82 dpclk: clock-controller@f1f0000 { 83 compatible = "fsl,ls1028a-plldig"; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; 85 #clock-cells = <0>; 86 clocks = <&osc_27m>; 87 }; 88 89 reboot { 90 compatible ="syscon-reboot"; 91 regmap = <&dcfg>; 92 offset = <0xb0>; 93 mask = <0x02>; 94 }; 95 96 timer { 97 compatible = "arm,armv8-timer"; 98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 99 IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 101 IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a72-pmu"; 110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 gic: interrupt-controller@6000000 { 114 compatible= "arm,gic-v3"; 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 119 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 120 #interrupt-cells= <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 123 IRQ_TYPE_LEVEL_LOW)>; 124 its: gic-its@6020000 { 125 compatible = "arm,gic-v3-its"; 126 msi-controller; 127 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 128 }; 129 }; 130 131 thermal-zones { 132 core-cluster { 133 polling-delay-passive = <1000>; 134 polling-delay = <5000>; 135 thermal-sensors = <&tmu 0>; 136 137 trips { 138 core_cluster_alert: core-cluster-alert { 139 temperature = <85000>; 140 hysteresis = <2000>; 141 type = "passive"; 142 }; 143 144 core_cluster_crit: core-cluster-crit { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "critical"; 148 }; 149 }; 150 151 cooling-maps { 152 map0 { 153 trip = <&core_cluster_alert>; 154 cooling-device = 155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 157 }; 158 }; 159 }; 160 }; 161 162 soc: soc { 163 compatible = "simple-bus"; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges; 167 168 ddr: memory-controller@1080000 { 169 compatible = "fsl,qoriq-memory-controller"; 170 reg = <0x0 0x1080000 0x0 0x1000>; 171 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 172 big-endian; 173 }; 174 175 dcfg: syscon@1e00000 { 176 compatible = "fsl,ls1028a-dcfg", "syscon"; 177 reg = <0x0 0x1e00000 0x0 0x10000>; 178 big-endian; 179 }; 180 181 scfg: syscon@1fc0000 { 182 compatible = "fsl,ls1028a-scfg", "syscon"; 183 reg = <0x0 0x1fc0000 0x0 0x10000>; 184 big-endian; 185 }; 186 187 clockgen: clock-controller@1300000 { 188 compatible = "fsl,ls1028a-clockgen"; 189 reg = <0x0 0x1300000 0x0 0xa0000>; 190 #clock-cells = <2>; 191 clocks = <&sysclk>; 192 }; 193 194 i2c0: i2c@2000000 { 195 compatible = "fsl,vf610-i2c"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 reg = <0x0 0x2000000 0x0 0x10000>; 199 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&clockgen 4 3>; 201 status = "disabled"; 202 }; 203 204 i2c1: i2c@2010000 { 205 compatible = "fsl,vf610-i2c"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 reg = <0x0 0x2010000 0x0 0x10000>; 209 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&clockgen 4 3>; 211 status = "disabled"; 212 }; 213 214 i2c2: i2c@2020000 { 215 compatible = "fsl,vf610-i2c"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 reg = <0x0 0x2020000 0x0 0x10000>; 219 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&clockgen 4 3>; 221 status = "disabled"; 222 }; 223 224 i2c3: i2c@2030000 { 225 compatible = "fsl,vf610-i2c"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 reg = <0x0 0x2030000 0x0 0x10000>; 229 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clockgen 4 3>; 231 status = "disabled"; 232 }; 233 234 i2c4: i2c@2040000 { 235 compatible = "fsl,vf610-i2c"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 reg = <0x0 0x2040000 0x0 0x10000>; 239 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&clockgen 4 3>; 241 status = "disabled"; 242 }; 243 244 i2c5: i2c@2050000 { 245 compatible = "fsl,vf610-i2c"; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 reg = <0x0 0x2050000 0x0 0x10000>; 249 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clockgen 4 3>; 251 status = "disabled"; 252 }; 253 254 i2c6: i2c@2060000 { 255 compatible = "fsl,vf610-i2c"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x0 0x2060000 0x0 0x10000>; 259 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&clockgen 4 3>; 261 status = "disabled"; 262 }; 263 264 i2c7: i2c@2070000 { 265 compatible = "fsl,vf610-i2c"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 reg = <0x0 0x2070000 0x0 0x10000>; 269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clockgen 4 3>; 271 status = "disabled"; 272 }; 273 274 fspi: spi@20c0000 { 275 compatible = "nxp,lx2160a-fspi"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 reg = <0x0 0x20c0000 0x0 0x10000>, 279 <0x0 0x20000000 0x0 0x10000000>; 280 reg-names = "fspi_base", "fspi_mmap"; 281 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 283 clock-names = "fspi_en", "fspi"; 284 status = "disabled"; 285 }; 286 287 esdhc: mmc@2140000 { 288 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 289 reg = <0x0 0x2140000 0x0 0x10000>; 290 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 291 clock-frequency = <0>; /* fixed up by bootloader */ 292 clocks = <&clockgen 2 1>; 293 voltage-ranges = <1800 1800 3300 3300>; 294 sdhci,auto-cmd12; 295 little-endian; 296 bus-width = <4>; 297 status = "disabled"; 298 }; 299 300 esdhc1: mmc@2150000 { 301 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 302 reg = <0x0 0x2150000 0x0 0x10000>; 303 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 304 clock-frequency = <0>; /* fixed up by bootloader */ 305 clocks = <&clockgen 2 1>; 306 voltage-ranges = <1800 1800 3300 3300>; 307 sdhci,auto-cmd12; 308 broken-cd; 309 little-endian; 310 bus-width = <4>; 311 status = "disabled"; 312 }; 313 314 duart0: serial@21c0500 { 315 compatible = "fsl,ns16550", "ns16550a"; 316 reg = <0x00 0x21c0500 0x0 0x100>; 317 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clockgen 4 1>; 319 status = "disabled"; 320 }; 321 322 duart1: serial@21c0600 { 323 compatible = "fsl,ns16550", "ns16550a"; 324 reg = <0x00 0x21c0600 0x0 0x100>; 325 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&clockgen 4 1>; 327 status = "disabled"; 328 }; 329 330 edma0: dma-controller@22c0000 { 331 #dma-cells = <2>; 332 compatible = "fsl,ls1028a-edma"; 333 reg = <0x0 0x22c0000 0x0 0x10000>, 334 <0x0 0x22d0000 0x0 0x10000>, 335 <0x0 0x22e0000 0x0 0x10000>; 336 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-names = "edma-tx", "edma-err"; 339 dma-channels = <32>; 340 clock-names = "dmamux0", "dmamux1"; 341 clocks = <&clockgen 4 1>, 342 <&clockgen 4 1>; 343 }; 344 345 gpio1: gpio@2300000 { 346 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 347 reg = <0x0 0x2300000 0x0 0x10000>; 348 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 little-endian; 354 }; 355 356 gpio2: gpio@2310000 { 357 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 358 reg = <0x0 0x2310000 0x0 0x10000>; 359 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 little-endian; 365 }; 366 367 gpio3: gpio@2320000 { 368 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 369 reg = <0x0 0x2320000 0x0 0x10000>; 370 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 little-endian; 376 }; 377 378 usb0: usb@3100000 { 379 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 380 reg = <0x0 0x3100000 0x0 0x10000>; 381 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 382 dr_mode = "host"; 383 snps,dis_rxdet_inp3_quirk; 384 snps,quirk-frame-length-adjustment = <0x20>; 385 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 386 }; 387 388 usb1: usb@3110000 { 389 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 390 reg = <0x0 0x3110000 0x0 0x10000>; 391 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 392 dr_mode = "host"; 393 snps,dis_rxdet_inp3_quirk; 394 snps,quirk-frame-length-adjustment = <0x20>; 395 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 396 }; 397 398 sata: sata@3200000 { 399 compatible = "fsl,ls1028a-ahci"; 400 reg = <0x0 0x3200000 0x0 0x10000>, 401 <0x7 0x100520 0x0 0x4>; 402 reg-names = "ahci", "sata-ecc"; 403 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&clockgen 4 1>; 405 status = "disabled"; 406 }; 407 408 smmu: iommu@5000000 { 409 compatible = "arm,mmu-500"; 410 reg = <0 0x5000000 0 0x800000>; 411 #global-interrupts = <8>; 412 #iommu-cells = <1>; 413 stream-match-mask = <0x7c00>; 414 /* global secure fault */ 415 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 416 /* combined secure interrupt */ 417 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 418 /* global non-secure fault */ 419 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 420 /* combined non-secure interrupt */ 421 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 422 /* performance counter interrupts 0-7 */ 423 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 425 /* per context interrupt, 64 interrupts */ 426 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 458 }; 459 460 crypto: crypto@8000000 { 461 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 462 fsl,sec-era = <10>; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 ranges = <0x0 0x00 0x8000000 0x100000>; 466 reg = <0x00 0x8000000 0x0 0x100000>; 467 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 468 dma-coherent; 469 470 sec_jr0: jr@10000 { 471 compatible = "fsl,sec-v5.0-job-ring", 472 "fsl,sec-v4.0-job-ring"; 473 reg = <0x10000 0x10000>; 474 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 475 }; 476 477 sec_jr1: jr@20000 { 478 compatible = "fsl,sec-v5.0-job-ring", 479 "fsl,sec-v4.0-job-ring"; 480 reg = <0x20000 0x10000>; 481 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 482 }; 483 484 sec_jr2: jr@30000 { 485 compatible = "fsl,sec-v5.0-job-ring", 486 "fsl,sec-v4.0-job-ring"; 487 reg = <0x30000 0x10000>; 488 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 489 }; 490 491 sec_jr3: jr@40000 { 492 compatible = "fsl,sec-v5.0-job-ring", 493 "fsl,sec-v4.0-job-ring"; 494 reg = <0x40000 0x10000>; 495 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 496 }; 497 }; 498 499 qdma: dma-controller@8380000 { 500 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 501 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 502 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 503 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 504 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 509 interrupt-names = "qdma-error", "qdma-queue0", 510 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 511 dma-channels = <8>; 512 block-number = <1>; 513 block-offset = <0x10000>; 514 fsl,dma-queues = <2>; 515 status-sizes = <64>; 516 queue-sizes = <64 64>; 517 }; 518 519 cluster1_core0_watchdog: watchdog@c000000 { 520 compatible = "arm,sp805", "arm,primecell"; 521 reg = <0x0 0xc000000 0x0 0x1000>; 522 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 523 clock-names = "apb_pclk", "wdog_clk"; 524 }; 525 526 cluster1_core1_watchdog: watchdog@c010000 { 527 compatible = "arm,sp805", "arm,primecell"; 528 reg = <0x0 0xc010000 0x0 0x1000>; 529 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 530 clock-names = "apb_pclk", "wdog_clk"; 531 }; 532 533 sai1: audio-controller@f100000 { 534 #sound-dai-cells = <0>; 535 compatible = "fsl,vf610-sai"; 536 reg = <0x0 0xf100000 0x0 0x10000>; 537 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 539 <&clockgen 4 1>, <&clockgen 4 1>; 540 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 541 dma-names = "tx", "rx"; 542 dmas = <&edma0 1 4>, 543 <&edma0 1 3>; 544 fsl,sai-asynchronous; 545 status = "disabled"; 546 }; 547 548 sai2: audio-controller@f110000 { 549 #sound-dai-cells = <0>; 550 compatible = "fsl,vf610-sai"; 551 reg = <0x0 0xf110000 0x0 0x10000>; 552 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 554 <&clockgen 4 1>, <&clockgen 4 1>; 555 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 556 dma-names = "tx", "rx"; 557 dmas = <&edma0 1 6>, 558 <&edma0 1 5>; 559 fsl,sai-asynchronous; 560 status = "disabled"; 561 }; 562 563 sai3: audio-controller@f120000 { 564 #sound-dai-cells = <0>; 565 compatible = "fsl,vf610-sai"; 566 reg = <0x0 0xf120000 0x0 0x10000>; 567 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 569 <&clockgen 4 1>, <&clockgen 4 1>; 570 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 571 dma-names = "tx", "rx"; 572 dmas = <&edma0 1 8>, 573 <&edma0 1 7>; 574 fsl,sai-asynchronous; 575 status = "disabled"; 576 }; 577 578 sai4: audio-controller@f130000 { 579 #sound-dai-cells = <0>; 580 compatible = "fsl,vf610-sai"; 581 reg = <0x0 0xf130000 0x0 0x10000>; 582 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 584 <&clockgen 4 1>, <&clockgen 4 1>; 585 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 586 dma-names = "tx", "rx"; 587 dmas = <&edma0 1 10>, 588 <&edma0 1 9>; 589 fsl,sai-asynchronous; 590 status = "disabled"; 591 }; 592 593 sai5: audio-controller@f140000 { 594 #sound-dai-cells = <0>; 595 compatible = "fsl,vf610-sai"; 596 reg = <0x0 0xf140000 0x0 0x10000>; 597 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 599 <&clockgen 4 1>, <&clockgen 4 1>; 600 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 601 dma-names = "tx", "rx"; 602 dmas = <&edma0 1 12>, 603 <&edma0 1 11>; 604 fsl,sai-asynchronous; 605 status = "disabled"; 606 }; 607 608 sai6: audio-controller@f150000 { 609 #sound-dai-cells = <0>; 610 compatible = "fsl,vf610-sai"; 611 reg = <0x0 0xf150000 0x0 0x10000>; 612 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 614 <&clockgen 4 1>, <&clockgen 4 1>; 615 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 616 dma-names = "tx", "rx"; 617 dmas = <&edma0 1 14>, 618 <&edma0 1 13>; 619 fsl,sai-asynchronous; 620 status = "disabled"; 621 }; 622 623 tmu: tmu@1f80000 { 624 compatible = "fsl,qoriq-tmu"; 625 reg = <0x0 0x1f80000 0x0 0x10000>; 626 interrupts = <0 23 0x4>; 627 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 628 fsl,tmu-calibration = <0x00000000 0x00000024 629 0x00000001 0x0000002b 630 0x00000002 0x00000031 631 0x00000003 0x00000038 632 0x00000004 0x0000003f 633 0x00000005 0x00000045 634 0x00000006 0x0000004c 635 0x00000007 0x00000053 636 0x00000008 0x00000059 637 0x00000009 0x00000060 638 0x0000000a 0x00000066 639 0x0000000b 0x0000006d 640 641 0x00010000 0x0000001c 642 0x00010001 0x00000024 643 0x00010002 0x0000002c 644 0x00010003 0x00000035 645 0x00010004 0x0000003d 646 0x00010005 0x00000045 647 0x00010006 0x0000004d 648 0x00010007 0x00000045 649 0x00010008 0x0000005e 650 0x00010009 0x00000066 651 0x0001000a 0x0000006e 652 653 0x00020000 0x00000018 654 0x00020001 0x00000022 655 0x00020002 0x0000002d 656 0x00020003 0x00000038 657 0x00020004 0x00000043 658 0x00020005 0x0000004d 659 0x00020006 0x00000058 660 0x00020007 0x00000063 661 0x00020008 0x0000006e 662 663 0x00030000 0x00000010 664 0x00030001 0x0000001c 665 0x00030002 0x00000029 666 0x00030003 0x00000036 667 0x00030004 0x00000042 668 0x00030005 0x0000004f 669 0x00030006 0x0000005b 670 0x00030007 0x00000068>; 671 little-endian; 672 #thermal-sensor-cells = <1>; 673 }; 674 675 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 676 compatible = "pci-host-ecam-generic"; 677 reg = <0x01 0xf0000000 0x0 0x100000>; 678 #address-cells = <3>; 679 #size-cells = <2>; 680 #interrupt-cells = <1>; 681 msi-parent = <&its>; 682 device_type = "pci"; 683 bus-range = <0x0 0x0>; 684 dma-coherent; 685 msi-map = <0 &its 0x17 0xe>; 686 iommu-map = <0 &smmu 0x17 0xe>; 687 /* PF0-6 BAR0 - non-prefetchable memory */ 688 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 689 /* PF0-6 BAR2 - prefetchable memory */ 690 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 691 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 692 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 693 /* PF0: VF0-1 BAR2 - prefetchable memory */ 694 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 695 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 696 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 697 /* PF1: VF0-1 BAR2 - prefetchable memory */ 698 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 699 700 enetc_port0: ethernet@0,0 { 701 compatible = "fsl,enetc"; 702 reg = <0x000000 0 0 0 0>; 703 }; 704 enetc_port1: ethernet@0,1 { 705 compatible = "fsl,enetc"; 706 reg = <0x000100 0 0 0 0>; 707 }; 708 enetc_mdio_pf3: mdio@0,3 { 709 compatible = "fsl,enetc-mdio"; 710 reg = <0x000300 0 0 0 0>; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 }; 714 ethernet@0,4 { 715 compatible = "fsl,enetc-ptp"; 716 reg = <0x000400 0 0 0 0>; 717 clocks = <&clockgen 4 0>; 718 little-endian; 719 }; 720 }; 721 }; 722 723 malidp0: display@f080000 { 724 compatible = "arm,mali-dp500"; 725 reg = <0x0 0xf080000 0x0 0x10000>; 726 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 727 <0 223 IRQ_TYPE_LEVEL_HIGH>; 728 interrupt-names = "DE", "SE"; 729 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 730 <&clockgen 2 2>; 731 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 732 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 733 arm,malidp-arqos-value = <0xd000d000>; 734 735 port { 736 dp0_out: endpoint { 737 738 }; 739 }; 740 }; 741}; 742