1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a72"; 38 reg = <0x1>; 39 enable-method = "psci"; 40 clocks = <&clockgen 1 0>; 41 next-level-cache = <&l2>; 42 cpu-idle-states = <&CPU_PW20>; 43 #cooling-cells = <2>; 44 }; 45 46 l2: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 idle-states { 52 /* 53 * PSCI node is not added default, U-boot will add missing 54 * parts if it determines to use PSCI. 55 */ 56 entry-method = "psci"; 57 58 CPU_PW20: cpu-pw20 { 59 compatible = "arm,idle-state"; 60 idle-state-name = "PW20"; 61 arm,psci-suspend-param = <0x0>; 62 entry-latency-us = <2000>; 63 exit-latency-us = <2000>; 64 min-residency-us = <6000>; 65 }; 66 }; 67 68 sysclk: clock-sysclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "sysclk"; 73 }; 74 75 osc_27m: clock-osc-27m { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <27000000>; 79 clock-output-names = "phy_27m"; 80 }; 81 82 dpclk: clock-controller@f1f0000 { 83 compatible = "fsl,ls1028a-plldig"; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; 85 #clock-cells = <0>; 86 clocks = <&osc_27m>; 87 }; 88 89 reboot { 90 compatible ="syscon-reboot"; 91 regmap = <&rst>; 92 offset = <0xb0>; 93 mask = <0x02>; 94 }; 95 96 timer { 97 compatible = "arm,armv8-timer"; 98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 99 IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 101 IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a72-pmu"; 110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 gic: interrupt-controller@6000000 { 114 compatible= "arm,gic-v3"; 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 119 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 120 #interrupt-cells= <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 123 IRQ_TYPE_LEVEL_LOW)>; 124 its: gic-its@6020000 { 125 compatible = "arm,gic-v3-its"; 126 msi-controller; 127 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 128 }; 129 }; 130 131 thermal-zones { 132 core-cluster { 133 polling-delay-passive = <1000>; 134 polling-delay = <5000>; 135 thermal-sensors = <&tmu 0>; 136 137 trips { 138 core_cluster_alert: core-cluster-alert { 139 temperature = <85000>; 140 hysteresis = <2000>; 141 type = "passive"; 142 }; 143 144 core_cluster_crit: core-cluster-crit { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "critical"; 148 }; 149 }; 150 151 cooling-maps { 152 map0 { 153 trip = <&core_cluster_alert>; 154 cooling-device = 155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 157 }; 158 }; 159 }; 160 }; 161 162 soc: soc { 163 compatible = "simple-bus"; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges; 167 168 ddr: memory-controller@1080000 { 169 compatible = "fsl,qoriq-memory-controller"; 170 reg = <0x0 0x1080000 0x0 0x1000>; 171 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 172 big-endian; 173 }; 174 175 dcfg: syscon@1e00000 { 176 compatible = "fsl,ls1028a-dcfg", "syscon"; 177 reg = <0x0 0x1e00000 0x0 0x10000>; 178 little-endian; 179 }; 180 181 rst: syscon@1e60000 { 182 compatible = "syscon"; 183 reg = <0x0 0x1e60000 0x0 0x10000>; 184 little-endian; 185 }; 186 187 scfg: syscon@1fc0000 { 188 compatible = "fsl,ls1028a-scfg", "syscon"; 189 reg = <0x0 0x1fc0000 0x0 0x10000>; 190 big-endian; 191 }; 192 193 clockgen: clock-controller@1300000 { 194 compatible = "fsl,ls1028a-clockgen"; 195 reg = <0x0 0x1300000 0x0 0xa0000>; 196 #clock-cells = <2>; 197 clocks = <&sysclk>; 198 }; 199 200 i2c0: i2c@2000000 { 201 compatible = "fsl,vf610-i2c"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <0x0 0x2000000 0x0 0x10000>; 205 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&clockgen 4 3>; 207 status = "disabled"; 208 }; 209 210 i2c1: i2c@2010000 { 211 compatible = "fsl,vf610-i2c"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 reg = <0x0 0x2010000 0x0 0x10000>; 215 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clockgen 4 3>; 217 status = "disabled"; 218 }; 219 220 i2c2: i2c@2020000 { 221 compatible = "fsl,vf610-i2c"; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 reg = <0x0 0x2020000 0x0 0x10000>; 225 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&clockgen 4 3>; 227 status = "disabled"; 228 }; 229 230 i2c3: i2c@2030000 { 231 compatible = "fsl,vf610-i2c"; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0x0 0x2030000 0x0 0x10000>; 235 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&clockgen 4 3>; 237 status = "disabled"; 238 }; 239 240 i2c4: i2c@2040000 { 241 compatible = "fsl,vf610-i2c"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0x0 0x2040000 0x0 0x10000>; 245 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&clockgen 4 3>; 247 status = "disabled"; 248 }; 249 250 i2c5: i2c@2050000 { 251 compatible = "fsl,vf610-i2c"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0x0 0x2050000 0x0 0x10000>; 255 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&clockgen 4 3>; 257 status = "disabled"; 258 }; 259 260 i2c6: i2c@2060000 { 261 compatible = "fsl,vf610-i2c"; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 reg = <0x0 0x2060000 0x0 0x10000>; 265 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&clockgen 4 3>; 267 status = "disabled"; 268 }; 269 270 i2c7: i2c@2070000 { 271 compatible = "fsl,vf610-i2c"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0x0 0x2070000 0x0 0x10000>; 275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&clockgen 4 3>; 277 status = "disabled"; 278 }; 279 280 fspi: spi@20c0000 { 281 compatible = "nxp,lx2160a-fspi"; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 reg = <0x0 0x20c0000 0x0 0x10000>, 285 <0x0 0x20000000 0x0 0x10000000>; 286 reg-names = "fspi_base", "fspi_mmap"; 287 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 289 clock-names = "fspi_en", "fspi"; 290 status = "disabled"; 291 }; 292 293 esdhc: mmc@2140000 { 294 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 295 reg = <0x0 0x2140000 0x0 0x10000>; 296 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 297 clock-frequency = <0>; /* fixed up by bootloader */ 298 clocks = <&clockgen 2 1>; 299 voltage-ranges = <1800 1800 3300 3300>; 300 sdhci,auto-cmd12; 301 little-endian; 302 bus-width = <4>; 303 status = "disabled"; 304 }; 305 306 esdhc1: mmc@2150000 { 307 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 308 reg = <0x0 0x2150000 0x0 0x10000>; 309 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 310 clock-frequency = <0>; /* fixed up by bootloader */ 311 clocks = <&clockgen 2 1>; 312 voltage-ranges = <1800 1800 3300 3300>; 313 sdhci,auto-cmd12; 314 broken-cd; 315 little-endian; 316 bus-width = <4>; 317 status = "disabled"; 318 }; 319 320 duart0: serial@21c0500 { 321 compatible = "fsl,ns16550", "ns16550a"; 322 reg = <0x00 0x21c0500 0x0 0x100>; 323 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&clockgen 4 1>; 325 status = "disabled"; 326 }; 327 328 duart1: serial@21c0600 { 329 compatible = "fsl,ns16550", "ns16550a"; 330 reg = <0x00 0x21c0600 0x0 0x100>; 331 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clockgen 4 1>; 333 status = "disabled"; 334 }; 335 336 337 lpuart0: serial@2260000 { 338 compatible = "fsl,ls1028a-lpuart"; 339 reg = <0x0 0x2260000 0x0 0x1000>; 340 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clockgen 4 1>; 342 clock-names = "ipg"; 343 dma-names = "rx","tx"; 344 dmas = <&edma0 1 32>, 345 <&edma0 1 33>; 346 status = "disabled"; 347 }; 348 349 lpuart1: serial@2270000 { 350 compatible = "fsl,ls1028a-lpuart"; 351 reg = <0x0 0x2270000 0x0 0x1000>; 352 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clockgen 4 1>; 354 clock-names = "ipg"; 355 dma-names = "rx","tx"; 356 dmas = <&edma0 1 30>, 357 <&edma0 1 31>; 358 status = "disabled"; 359 }; 360 361 lpuart2: serial@2280000 { 362 compatible = "fsl,ls1028a-lpuart"; 363 reg = <0x0 0x2280000 0x0 0x1000>; 364 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clockgen 4 1>; 366 clock-names = "ipg"; 367 dma-names = "rx","tx"; 368 dmas = <&edma0 1 28>, 369 <&edma0 1 29>; 370 status = "disabled"; 371 }; 372 373 lpuart3: serial@2290000 { 374 compatible = "fsl,ls1028a-lpuart"; 375 reg = <0x0 0x2290000 0x0 0x1000>; 376 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clockgen 4 1>; 378 clock-names = "ipg"; 379 dma-names = "rx","tx"; 380 dmas = <&edma0 1 26>, 381 <&edma0 1 27>; 382 status = "disabled"; 383 }; 384 385 lpuart4: serial@22a0000 { 386 compatible = "fsl,ls1028a-lpuart"; 387 reg = <0x0 0x22a0000 0x0 0x1000>; 388 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clockgen 4 1>; 390 clock-names = "ipg"; 391 dma-names = "rx","tx"; 392 dmas = <&edma0 1 24>, 393 <&edma0 1 25>; 394 status = "disabled"; 395 }; 396 397 lpuart5: serial@22b0000 { 398 compatible = "fsl,ls1028a-lpuart"; 399 reg = <0x0 0x22b0000 0x0 0x1000>; 400 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clockgen 4 1>; 402 clock-names = "ipg"; 403 dma-names = "rx","tx"; 404 dmas = <&edma0 1 22>, 405 <&edma0 1 23>; 406 status = "disabled"; 407 }; 408 409 edma0: dma-controller@22c0000 { 410 #dma-cells = <2>; 411 compatible = "fsl,ls1028a-edma"; 412 reg = <0x0 0x22c0000 0x0 0x10000>, 413 <0x0 0x22d0000 0x0 0x10000>, 414 <0x0 0x22e0000 0x0 0x10000>; 415 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "edma-tx", "edma-err"; 418 dma-channels = <32>; 419 clock-names = "dmamux0", "dmamux1"; 420 clocks = <&clockgen 4 1>, 421 <&clockgen 4 1>; 422 }; 423 424 gpio1: gpio@2300000 { 425 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 426 reg = <0x0 0x2300000 0x0 0x10000>; 427 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 little-endian; 433 }; 434 435 gpio2: gpio@2310000 { 436 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 437 reg = <0x0 0x2310000 0x0 0x10000>; 438 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 little-endian; 444 }; 445 446 gpio3: gpio@2320000 { 447 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 448 reg = <0x0 0x2320000 0x0 0x10000>; 449 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 little-endian; 455 }; 456 457 usb0: usb@3100000 { 458 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 459 reg = <0x0 0x3100000 0x0 0x10000>; 460 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 461 dr_mode = "host"; 462 snps,dis_rxdet_inp3_quirk; 463 snps,quirk-frame-length-adjustment = <0x20>; 464 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 465 }; 466 467 usb1: usb@3110000 { 468 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 469 reg = <0x0 0x3110000 0x0 0x10000>; 470 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 471 dr_mode = "host"; 472 snps,dis_rxdet_inp3_quirk; 473 snps,quirk-frame-length-adjustment = <0x20>; 474 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 475 }; 476 477 sata: sata@3200000 { 478 compatible = "fsl,ls1028a-ahci"; 479 reg = <0x0 0x3200000 0x0 0x10000>, 480 <0x7 0x100520 0x0 0x4>; 481 reg-names = "ahci", "sata-ecc"; 482 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clockgen 4 1>; 484 status = "disabled"; 485 }; 486 487 smmu: iommu@5000000 { 488 compatible = "arm,mmu-500"; 489 reg = <0 0x5000000 0 0x800000>; 490 #global-interrupts = <8>; 491 #iommu-cells = <1>; 492 stream-match-mask = <0x7c00>; 493 /* global secure fault */ 494 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 495 /* combined secure interrupt */ 496 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 497 /* global non-secure fault */ 498 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 499 /* combined non-secure interrupt */ 500 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 501 /* performance counter interrupts 0-7 */ 502 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 504 /* per context interrupt, 64 interrupts */ 505 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 537 }; 538 539 crypto: crypto@8000000 { 540 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 541 fsl,sec-era = <10>; 542 #address-cells = <1>; 543 #size-cells = <1>; 544 ranges = <0x0 0x00 0x8000000 0x100000>; 545 reg = <0x00 0x8000000 0x0 0x100000>; 546 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 547 dma-coherent; 548 549 sec_jr0: jr@10000 { 550 compatible = "fsl,sec-v5.0-job-ring", 551 "fsl,sec-v4.0-job-ring"; 552 reg = <0x10000 0x10000>; 553 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 554 }; 555 556 sec_jr1: jr@20000 { 557 compatible = "fsl,sec-v5.0-job-ring", 558 "fsl,sec-v4.0-job-ring"; 559 reg = <0x20000 0x10000>; 560 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 561 }; 562 563 sec_jr2: jr@30000 { 564 compatible = "fsl,sec-v5.0-job-ring", 565 "fsl,sec-v4.0-job-ring"; 566 reg = <0x30000 0x10000>; 567 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 568 }; 569 570 sec_jr3: jr@40000 { 571 compatible = "fsl,sec-v5.0-job-ring", 572 "fsl,sec-v4.0-job-ring"; 573 reg = <0x40000 0x10000>; 574 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 575 }; 576 }; 577 578 qdma: dma-controller@8380000 { 579 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 580 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 581 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 582 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 583 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 588 interrupt-names = "qdma-error", "qdma-queue0", 589 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 590 dma-channels = <8>; 591 block-number = <1>; 592 block-offset = <0x10000>; 593 fsl,dma-queues = <2>; 594 status-sizes = <64>; 595 queue-sizes = <64 64>; 596 }; 597 598 cluster1_core0_watchdog: watchdog@c000000 { 599 compatible = "arm,sp805", "arm,primecell"; 600 reg = <0x0 0xc000000 0x0 0x1000>; 601 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 602 clock-names = "apb_pclk", "wdog_clk"; 603 }; 604 605 cluster1_core1_watchdog: watchdog@c010000 { 606 compatible = "arm,sp805", "arm,primecell"; 607 reg = <0x0 0xc010000 0x0 0x1000>; 608 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 609 clock-names = "apb_pclk", "wdog_clk"; 610 }; 611 612 sai1: audio-controller@f100000 { 613 #sound-dai-cells = <0>; 614 compatible = "fsl,vf610-sai"; 615 reg = <0x0 0xf100000 0x0 0x10000>; 616 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 618 <&clockgen 4 1>, <&clockgen 4 1>; 619 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 620 dma-names = "tx", "rx"; 621 dmas = <&edma0 1 4>, 622 <&edma0 1 3>; 623 fsl,sai-asynchronous; 624 status = "disabled"; 625 }; 626 627 sai2: audio-controller@f110000 { 628 #sound-dai-cells = <0>; 629 compatible = "fsl,vf610-sai"; 630 reg = <0x0 0xf110000 0x0 0x10000>; 631 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 633 <&clockgen 4 1>, <&clockgen 4 1>; 634 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 635 dma-names = "tx", "rx"; 636 dmas = <&edma0 1 6>, 637 <&edma0 1 5>; 638 fsl,sai-asynchronous; 639 status = "disabled"; 640 }; 641 642 sai3: audio-controller@f120000 { 643 #sound-dai-cells = <0>; 644 compatible = "fsl,vf610-sai"; 645 reg = <0x0 0xf120000 0x0 0x10000>; 646 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 648 <&clockgen 4 1>, <&clockgen 4 1>; 649 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 650 dma-names = "tx", "rx"; 651 dmas = <&edma0 1 8>, 652 <&edma0 1 7>; 653 fsl,sai-asynchronous; 654 status = "disabled"; 655 }; 656 657 sai4: audio-controller@f130000 { 658 #sound-dai-cells = <0>; 659 compatible = "fsl,vf610-sai"; 660 reg = <0x0 0xf130000 0x0 0x10000>; 661 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 663 <&clockgen 4 1>, <&clockgen 4 1>; 664 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 665 dma-names = "tx", "rx"; 666 dmas = <&edma0 1 10>, 667 <&edma0 1 9>; 668 fsl,sai-asynchronous; 669 status = "disabled"; 670 }; 671 672 sai5: audio-controller@f140000 { 673 #sound-dai-cells = <0>; 674 compatible = "fsl,vf610-sai"; 675 reg = <0x0 0xf140000 0x0 0x10000>; 676 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 678 <&clockgen 4 1>, <&clockgen 4 1>; 679 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 680 dma-names = "tx", "rx"; 681 dmas = <&edma0 1 12>, 682 <&edma0 1 11>; 683 fsl,sai-asynchronous; 684 status = "disabled"; 685 }; 686 687 sai6: audio-controller@f150000 { 688 #sound-dai-cells = <0>; 689 compatible = "fsl,vf610-sai"; 690 reg = <0x0 0xf150000 0x0 0x10000>; 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 693 <&clockgen 4 1>, <&clockgen 4 1>; 694 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 695 dma-names = "tx", "rx"; 696 dmas = <&edma0 1 14>, 697 <&edma0 1 13>; 698 fsl,sai-asynchronous; 699 status = "disabled"; 700 }; 701 702 tmu: tmu@1f80000 { 703 compatible = "fsl,qoriq-tmu"; 704 reg = <0x0 0x1f80000 0x0 0x10000>; 705 interrupts = <0 23 0x4>; 706 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 707 fsl,tmu-calibration = <0x00000000 0x00000024 708 0x00000001 0x0000002b 709 0x00000002 0x00000031 710 0x00000003 0x00000038 711 0x00000004 0x0000003f 712 0x00000005 0x00000045 713 0x00000006 0x0000004c 714 0x00000007 0x00000053 715 0x00000008 0x00000059 716 0x00000009 0x00000060 717 0x0000000a 0x00000066 718 0x0000000b 0x0000006d 719 720 0x00010000 0x0000001c 721 0x00010001 0x00000024 722 0x00010002 0x0000002c 723 0x00010003 0x00000035 724 0x00010004 0x0000003d 725 0x00010005 0x00000045 726 0x00010006 0x0000004d 727 0x00010007 0x00000055 728 0x00010008 0x0000005e 729 0x00010009 0x00000066 730 0x0001000a 0x0000006e 731 732 0x00020000 0x00000018 733 0x00020001 0x00000022 734 0x00020002 0x0000002d 735 0x00020003 0x00000038 736 0x00020004 0x00000043 737 0x00020005 0x0000004d 738 0x00020006 0x00000058 739 0x00020007 0x00000063 740 0x00020008 0x0000006e 741 742 0x00030000 0x00000010 743 0x00030001 0x0000001c 744 0x00030002 0x00000029 745 0x00030003 0x00000036 746 0x00030004 0x00000042 747 0x00030005 0x0000004f 748 0x00030006 0x0000005b 749 0x00030007 0x00000068>; 750 little-endian; 751 #thermal-sensor-cells = <1>; 752 }; 753 754 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 755 compatible = "pci-host-ecam-generic"; 756 reg = <0x01 0xf0000000 0x0 0x100000>; 757 #address-cells = <3>; 758 #size-cells = <2>; 759 #interrupt-cells = <1>; 760 msi-parent = <&its>; 761 device_type = "pci"; 762 bus-range = <0x0 0x0>; 763 dma-coherent; 764 msi-map = <0 &its 0x17 0xe>; 765 iommu-map = <0 &smmu 0x17 0xe>; 766 /* PF0-6 BAR0 - non-prefetchable memory */ 767 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 768 /* PF0-6 BAR2 - prefetchable memory */ 769 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 770 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 771 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 772 /* PF0: VF0-1 BAR2 - prefetchable memory */ 773 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 774 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 775 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 776 /* PF1: VF0-1 BAR2 - prefetchable memory */ 777 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 778 779 enetc_port0: ethernet@0,0 { 780 compatible = "fsl,enetc"; 781 reg = <0x000000 0 0 0 0>; 782 }; 783 enetc_port1: ethernet@0,1 { 784 compatible = "fsl,enetc"; 785 reg = <0x000100 0 0 0 0>; 786 }; 787 enetc_mdio_pf3: mdio@0,3 { 788 compatible = "fsl,enetc-mdio"; 789 reg = <0x000300 0 0 0 0>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 }; 793 ethernet@0,4 { 794 compatible = "fsl,enetc-ptp"; 795 reg = <0x000400 0 0 0 0>; 796 clocks = <&clockgen 4 0>; 797 little-endian; 798 }; 799 }; 800 }; 801 802 malidp0: display@f080000 { 803 compatible = "arm,mali-dp500"; 804 reg = <0x0 0xf080000 0x0 0x10000>; 805 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 806 <0 223 IRQ_TYPE_LEVEL_HIGH>; 807 interrupt-names = "DE", "SE"; 808 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 809 <&clockgen 2 2>; 810 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 811 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 812 arm,malidp-arqos-value = <0xd000d000>; 813 814 port { 815 dp0_out: endpoint { 816 817 }; 818 }; 819 }; 820}; 821