1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 next-level-cache = <&l2>; 32 cpu-idle-states = <&CPU_PW20>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a72"; 39 reg = <0x1>; 40 enable-method = "psci"; 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PW20>; 44 #cooling-cells = <2>; 45 }; 46 47 l2: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 idle-states { 54 /* 55 * PSCI node is not added default, U-boot will add missing 56 * parts if it determines to use PSCI. 57 */ 58 entry-method = "psci"; 59 60 CPU_PW20: cpu-pw20 { 61 compatible = "arm,idle-state"; 62 idle-state-name = "PW20"; 63 arm,psci-suspend-param = <0x0>; 64 entry-latency-us = <2000>; 65 exit-latency-us = <2000>; 66 min-residency-us = <6000>; 67 }; 68 }; 69 70 rtc_clk: rtc-clk { 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <32768>; 74 clock-output-names = "rtc_clk"; 75 }; 76 77 sysclk: sysclk { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <100000000>; 81 clock-output-names = "sysclk"; 82 }; 83 84 osc_27m: clock-osc-27m { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <27000000>; 88 clock-output-names = "phy_27m"; 89 }; 90 91 firmware { 92 optee: optee { 93 compatible = "linaro,optee-tz"; 94 method = "smc"; 95 status = "disabled"; 96 }; 97 }; 98 99 reboot { 100 compatible = "syscon-reboot"; 101 regmap = <&rst>; 102 offset = <0>; 103 mask = <0x02>; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 109 IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 111 IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 113 IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 115 IRQ_TYPE_LEVEL_LOW)>; 116 }; 117 118 pmu { 119 compatible = "arm,cortex-a72-pmu"; 120 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 121 }; 122 123 gic: interrupt-controller@6000000 { 124 compatible = "arm,gic-v3"; 125 #address-cells = <2>; 126 #size-cells = <2>; 127 ranges; 128 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 129 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 133 IRQ_TYPE_LEVEL_LOW)>; 134 its: gic-its@6020000 { 135 compatible = "arm,gic-v3-its"; 136 msi-controller; 137 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 138 }; 139 }; 140 141 thermal-zones { 142 ddr-controller { 143 polling-delay-passive = <1000>; 144 polling-delay = <5000>; 145 thermal-sensors = <&tmu 0>; 146 147 trips { 148 ddr-ctrler-alert { 149 temperature = <85000>; 150 hysteresis = <2000>; 151 type = "passive"; 152 }; 153 154 ddr-ctrler-crit { 155 temperature = <95000>; 156 hysteresis = <2000>; 157 type = "critical"; 158 }; 159 }; 160 }; 161 162 core-cluster { 163 polling-delay-passive = <1000>; 164 polling-delay = <5000>; 165 thermal-sensors = <&tmu 1>; 166 167 trips { 168 core_cluster_alert: core-cluster-alert { 169 temperature = <85000>; 170 hysteresis = <2000>; 171 type = "passive"; 172 }; 173 174 core_cluster_crit: core-cluster-crit { 175 temperature = <95000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 181 cooling-maps { 182 map0 { 183 trip = <&core_cluster_alert>; 184 cooling-device = 185 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 186 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 187 }; 188 }; 189 }; 190 }; 191 192 soc: soc { 193 compatible = "simple-bus"; 194 #address-cells = <2>; 195 #size-cells = <2>; 196 ranges; 197 198 ddr: memory-controller@1080000 { 199 compatible = "fsl,qoriq-memory-controller"; 200 reg = <0x0 0x1080000 0x0 0x1000>; 201 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 202 little-endian; 203 }; 204 205 dcfg: syscon@1e00000 { 206 #address-cells = <1>; 207 #size-cells = <1>; 208 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 209 reg = <0x0 0x1e00000 0x0 0x10000>; 210 ranges = <0x0 0x0 0x1e00000 0x10000>; 211 little-endian; 212 213 fspi_clk: clock-controller@900 { 214 compatible = "fsl,ls1028a-flexspi-clk"; 215 reg = <0x900 0x4>; 216 #clock-cells = <0>; 217 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 218 clock-output-names = "fspi_clk"; 219 }; 220 }; 221 222 rst: syscon@1e60000 { 223 compatible = "syscon"; 224 reg = <0x0 0x1e60000 0x0 0x10000>; 225 little-endian; 226 }; 227 228 sfp: efuse@1e80000 { 229 compatible = "fsl,ls1028a-sfp"; 230 reg = <0x0 0x1e80000 0x0 0x10000>; 231 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 232 QORIQ_CLK_PLL_DIV(4)>; 233 clock-names = "sfp"; 234 #address-cells = <1>; 235 #size-cells = <1>; 236 237 ls1028a_uid: unique-id@1c { 238 reg = <0x1c 0x8>; 239 }; 240 }; 241 242 scfg: syscon@1fc0000 { 243 compatible = "fsl,ls1028a-scfg", "syscon"; 244 reg = <0x0 0x1fc0000 0x0 0x10000>; 245 big-endian; 246 }; 247 248 clockgen: clock-controller@1300000 { 249 compatible = "fsl,ls1028a-clockgen"; 250 reg = <0x0 0x1300000 0x0 0xa0000>; 251 #clock-cells = <2>; 252 clocks = <&sysclk>; 253 }; 254 255 i2c0: i2c@2000000 { 256 compatible = "fsl,vf610-i2c"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 reg = <0x0 0x2000000 0x0 0x10000>; 260 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 262 QORIQ_CLK_PLL_DIV(4)>; 263 status = "disabled"; 264 }; 265 266 i2c1: i2c@2010000 { 267 compatible = "fsl,vf610-i2c"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 reg = <0x0 0x2010000 0x0 0x10000>; 271 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 273 QORIQ_CLK_PLL_DIV(4)>; 274 status = "disabled"; 275 }; 276 277 i2c2: i2c@2020000 { 278 compatible = "fsl,vf610-i2c"; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 reg = <0x0 0x2020000 0x0 0x10000>; 282 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 284 QORIQ_CLK_PLL_DIV(4)>; 285 status = "disabled"; 286 }; 287 288 i2c3: i2c@2030000 { 289 compatible = "fsl,vf610-i2c"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 reg = <0x0 0x2030000 0x0 0x10000>; 293 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 295 QORIQ_CLK_PLL_DIV(4)>; 296 status = "disabled"; 297 }; 298 299 i2c4: i2c@2040000 { 300 compatible = "fsl,vf610-i2c"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <0x0 0x2040000 0x0 0x10000>; 304 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 306 QORIQ_CLK_PLL_DIV(4)>; 307 status = "disabled"; 308 }; 309 310 i2c5: i2c@2050000 { 311 compatible = "fsl,vf610-i2c"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0 0x2050000 0x0 0x10000>; 315 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 317 QORIQ_CLK_PLL_DIV(4)>; 318 status = "disabled"; 319 }; 320 321 i2c6: i2c@2060000 { 322 compatible = "fsl,vf610-i2c"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 reg = <0x0 0x2060000 0x0 0x10000>; 326 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 328 QORIQ_CLK_PLL_DIV(4)>; 329 status = "disabled"; 330 }; 331 332 i2c7: i2c@2070000 { 333 compatible = "fsl,vf610-i2c"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x0 0x2070000 0x0 0x10000>; 337 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 339 QORIQ_CLK_PLL_DIV(4)>; 340 status = "disabled"; 341 }; 342 343 fspi: spi@20c0000 { 344 compatible = "nxp,lx2160a-fspi"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 reg = <0x0 0x20c0000 0x0 0x10000>, 348 <0x0 0x20000000 0x0 0x10000000>; 349 reg-names = "fspi_base", "fspi_mmap"; 350 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&fspi_clk>, <&fspi_clk>; 352 clock-names = "fspi_en", "fspi"; 353 status = "disabled"; 354 }; 355 356 dspi0: spi@2100000 { 357 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 reg = <0x0 0x2100000 0x0 0x10000>; 361 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 362 clock-names = "dspi"; 363 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 364 QORIQ_CLK_PLL_DIV(2)>; 365 dmas = <&edma0 0 62>, <&edma0 0 60>; 366 dma-names = "tx", "rx"; 367 spi-num-chipselects = <4>; 368 little-endian; 369 status = "disabled"; 370 }; 371 372 dspi1: spi@2110000 { 373 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x0 0x2110000 0x0 0x10000>; 377 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 378 clock-names = "dspi"; 379 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 380 QORIQ_CLK_PLL_DIV(2)>; 381 dmas = <&edma0 0 58>, <&edma0 0 56>; 382 dma-names = "tx", "rx"; 383 spi-num-chipselects = <4>; 384 little-endian; 385 status = "disabled"; 386 }; 387 388 dspi2: spi@2120000 { 389 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 reg = <0x0 0x2120000 0x0 0x10000>; 393 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 394 clock-names = "dspi"; 395 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 396 QORIQ_CLK_PLL_DIV(2)>; 397 dmas = <&edma0 0 54>, <&edma0 0 2>; 398 dma-names = "tx", "rx"; 399 spi-num-chipselects = <3>; 400 little-endian; 401 status = "disabled"; 402 }; 403 404 esdhc: mmc@2140000 { 405 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 406 reg = <0x0 0x2140000 0x0 0x10000>; 407 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 408 clock-frequency = <0>; /* fixed up by bootloader */ 409 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 410 voltage-ranges = <1800 1800 3300 3300>; 411 sdhci,auto-cmd12; 412 little-endian; 413 bus-width = <4>; 414 status = "disabled"; 415 }; 416 417 esdhc1: mmc@2150000 { 418 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 419 reg = <0x0 0x2150000 0x0 0x10000>; 420 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <0>; /* fixed up by bootloader */ 422 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 423 voltage-ranges = <1800 1800>; 424 sdhci,auto-cmd12; 425 non-removable; 426 little-endian; 427 bus-width = <4>; 428 status = "disabled"; 429 }; 430 431 can0: can@2180000 { 432 compatible = "fsl,lx2160ar1-flexcan"; 433 reg = <0x0 0x2180000 0x0 0x10000>; 434 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 436 QORIQ_CLK_PLL_DIV(2)>, 437 <&clockgen QORIQ_CLK_PLATFORM_PLL 438 QORIQ_CLK_PLL_DIV(2)>; 439 clock-names = "ipg", "per"; 440 status = "disabled"; 441 }; 442 443 can1: can@2190000 { 444 compatible = "fsl,lx2160ar1-flexcan"; 445 reg = <0x0 0x2190000 0x0 0x10000>; 446 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 448 QORIQ_CLK_PLL_DIV(2)>, 449 <&clockgen QORIQ_CLK_PLATFORM_PLL 450 QORIQ_CLK_PLL_DIV(2)>; 451 clock-names = "ipg", "per"; 452 status = "disabled"; 453 }; 454 455 duart0: serial@21c0500 { 456 compatible = "fsl,ns16550", "ns16550a"; 457 reg = <0x00 0x21c0500 0x0 0x100>; 458 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 460 QORIQ_CLK_PLL_DIV(2)>; 461 status = "disabled"; 462 }; 463 464 duart1: serial@21c0600 { 465 compatible = "fsl,ns16550", "ns16550a"; 466 reg = <0x00 0x21c0600 0x0 0x100>; 467 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 469 QORIQ_CLK_PLL_DIV(2)>; 470 status = "disabled"; 471 }; 472 473 474 lpuart0: serial@2260000 { 475 compatible = "fsl,ls1028a-lpuart"; 476 reg = <0x0 0x2260000 0x0 0x1000>; 477 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 479 QORIQ_CLK_PLL_DIV(2)>; 480 clock-names = "ipg"; 481 dma-names = "rx","tx"; 482 dmas = <&edma0 1 32>, 483 <&edma0 1 33>; 484 status = "disabled"; 485 }; 486 487 lpuart1: serial@2270000 { 488 compatible = "fsl,ls1028a-lpuart"; 489 reg = <0x0 0x2270000 0x0 0x1000>; 490 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 492 QORIQ_CLK_PLL_DIV(2)>; 493 clock-names = "ipg"; 494 dma-names = "rx","tx"; 495 dmas = <&edma0 1 30>, 496 <&edma0 1 31>; 497 status = "disabled"; 498 }; 499 500 lpuart2: serial@2280000 { 501 compatible = "fsl,ls1028a-lpuart"; 502 reg = <0x0 0x2280000 0x0 0x1000>; 503 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 505 QORIQ_CLK_PLL_DIV(2)>; 506 clock-names = "ipg"; 507 dma-names = "rx","tx"; 508 dmas = <&edma0 1 28>, 509 <&edma0 1 29>; 510 status = "disabled"; 511 }; 512 513 lpuart3: serial@2290000 { 514 compatible = "fsl,ls1028a-lpuart"; 515 reg = <0x0 0x2290000 0x0 0x1000>; 516 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 518 QORIQ_CLK_PLL_DIV(2)>; 519 clock-names = "ipg"; 520 dma-names = "rx","tx"; 521 dmas = <&edma0 1 26>, 522 <&edma0 1 27>; 523 status = "disabled"; 524 }; 525 526 lpuart4: serial@22a0000 { 527 compatible = "fsl,ls1028a-lpuart"; 528 reg = <0x0 0x22a0000 0x0 0x1000>; 529 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 531 QORIQ_CLK_PLL_DIV(2)>; 532 clock-names = "ipg"; 533 dma-names = "rx","tx"; 534 dmas = <&edma0 1 24>, 535 <&edma0 1 25>; 536 status = "disabled"; 537 }; 538 539 lpuart5: serial@22b0000 { 540 compatible = "fsl,ls1028a-lpuart"; 541 reg = <0x0 0x22b0000 0x0 0x1000>; 542 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 544 QORIQ_CLK_PLL_DIV(2)>; 545 clock-names = "ipg"; 546 dma-names = "rx","tx"; 547 dmas = <&edma0 1 22>, 548 <&edma0 1 23>; 549 status = "disabled"; 550 }; 551 552 edma0: dma-controller@22c0000 { 553 #dma-cells = <2>; 554 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 555 reg = <0x0 0x22c0000 0x0 0x10000>, 556 <0x0 0x22d0000 0x0 0x10000>, 557 <0x0 0x22e0000 0x0 0x10000>; 558 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "edma-tx", "edma-err"; 561 dma-channels = <32>; 562 clock-names = "dmamux0", "dmamux1"; 563 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 564 QORIQ_CLK_PLL_DIV(2)>, 565 <&clockgen QORIQ_CLK_PLATFORM_PLL 566 QORIQ_CLK_PLL_DIV(2)>; 567 }; 568 569 gpio1: gpio@2300000 { 570 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 571 reg = <0x0 0x2300000 0x0 0x10000>; 572 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 573 gpio-controller; 574 #gpio-cells = <2>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 little-endian; 578 }; 579 580 gpio2: gpio@2310000 { 581 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 582 reg = <0x0 0x2310000 0x0 0x10000>; 583 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 584 gpio-controller; 585 #gpio-cells = <2>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 little-endian; 589 }; 590 591 gpio3: gpio@2320000 { 592 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 593 reg = <0x0 0x2320000 0x0 0x10000>; 594 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 little-endian; 600 }; 601 602 usb0: usb@3100000 { 603 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 604 reg = <0x0 0x3100000 0x0 0x10000>; 605 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 606 snps,dis_rxdet_inp3_quirk; 607 snps,quirk-frame-length-adjustment = <0x20>; 608 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 609 status = "disabled"; 610 }; 611 612 usb1: usb@3110000 { 613 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 614 reg = <0x0 0x3110000 0x0 0x10000>; 615 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 616 snps,dis_rxdet_inp3_quirk; 617 snps,quirk-frame-length-adjustment = <0x20>; 618 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 619 status = "disabled"; 620 }; 621 622 sata: sata@3200000 { 623 compatible = "fsl,ls1028a-ahci"; 624 reg = <0x0 0x3200000 0x0 0x10000>, 625 <0x7 0x100520 0x0 0x4>; 626 reg-names = "ahci", "sata-ecc"; 627 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 629 QORIQ_CLK_PLL_DIV(2)>; 630 status = "disabled"; 631 }; 632 633 pcie1: pcie@3400000 { 634 compatible = "fsl,ls1028a-pcie"; 635 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 636 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 637 reg-names = "regs", "config"; 638 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 639 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 640 interrupt-names = "pme", "aer"; 641 #address-cells = <3>; 642 #size-cells = <2>; 643 device_type = "pci"; 644 dma-coherent; 645 num-viewport = <8>; 646 bus-range = <0x0 0xff>; 647 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 648 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 649 msi-parent = <&its>; 650 #interrupt-cells = <1>; 651 interrupt-map-mask = <0 0 0 7>; 652 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 653 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 654 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 655 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 656 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 657 status = "disabled"; 658 }; 659 660 pcie_ep1: pcie-ep@3400000 { 661 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 662 reg = <0x00 0x03400000 0x0 0x00100000 663 0x80 0x00000000 0x8 0x00000000>; 664 reg-names = "regs", "addr_space"; 665 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 666 interrupt-names = "pme"; 667 num-ib-windows = <6>; 668 num-ob-windows = <8>; 669 status = "disabled"; 670 }; 671 672 pcie2: pcie@3500000 { 673 compatible = "fsl,ls1028a-pcie"; 674 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 675 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 676 reg-names = "regs", "config"; 677 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-names = "pme", "aer"; 680 #address-cells = <3>; 681 #size-cells = <2>; 682 device_type = "pci"; 683 dma-coherent; 684 num-viewport = <8>; 685 bus-range = <0x0 0xff>; 686 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 687 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 688 msi-parent = <&its>; 689 #interrupt-cells = <1>; 690 interrupt-map-mask = <0 0 0 7>; 691 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 692 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 693 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 694 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 695 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 696 status = "disabled"; 697 }; 698 699 pcie_ep2: pcie-ep@3500000 { 700 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 701 reg = <0x00 0x03500000 0x0 0x00100000 702 0x88 0x00000000 0x8 0x00000000>; 703 reg-names = "regs", "addr_space"; 704 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 705 interrupt-names = "pme"; 706 num-ib-windows = <6>; 707 num-ob-windows = <8>; 708 status = "disabled"; 709 }; 710 711 smmu: iommu@5000000 { 712 compatible = "arm,mmu-500"; 713 reg = <0 0x5000000 0 0x800000>; 714 #global-interrupts = <8>; 715 #iommu-cells = <1>; 716 stream-match-mask = <0x7c00>; 717 /* global secure fault */ 718 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 719 /* combined secure interrupt */ 720 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 721 /* global non-secure fault */ 722 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 723 /* combined non-secure interrupt */ 724 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 725 /* performance counter interrupts 0-7 */ 726 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 728 /* per context interrupt, 64 interrupts */ 729 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 crypto: crypto@8000000 { 764 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 765 fsl,sec-era = <10>; 766 #address-cells = <1>; 767 #size-cells = <1>; 768 ranges = <0x0 0x00 0x8000000 0x100000>; 769 reg = <0x00 0x8000000 0x0 0x100000>; 770 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 771 dma-coherent; 772 773 sec_jr0: jr@10000 { 774 compatible = "fsl,sec-v5.0-job-ring", 775 "fsl,sec-v4.0-job-ring"; 776 reg = <0x10000 0x10000>; 777 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 778 }; 779 780 sec_jr1: jr@20000 { 781 compatible = "fsl,sec-v5.0-job-ring", 782 "fsl,sec-v4.0-job-ring"; 783 reg = <0x20000 0x10000>; 784 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 785 }; 786 787 sec_jr2: jr@30000 { 788 compatible = "fsl,sec-v5.0-job-ring", 789 "fsl,sec-v4.0-job-ring"; 790 reg = <0x30000 0x10000>; 791 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 792 }; 793 794 sec_jr3: jr@40000 { 795 compatible = "fsl,sec-v5.0-job-ring", 796 "fsl,sec-v4.0-job-ring"; 797 reg = <0x40000 0x10000>; 798 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 799 }; 800 }; 801 802 qdma: dma-controller@8380000 { 803 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 804 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 805 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 806 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 807 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 812 interrupt-names = "qdma-error", "qdma-queue0", 813 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 814 dma-channels = <8>; 815 block-number = <1>; 816 block-offset = <0x10000>; 817 fsl,dma-queues = <2>; 818 status-sizes = <64>; 819 queue-sizes = <64 64>; 820 }; 821 822 cluster1_core0_watchdog: watchdog@c000000 { 823 compatible = "arm,sp805", "arm,primecell"; 824 reg = <0x0 0xc000000 0x0 0x1000>; 825 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 826 QORIQ_CLK_PLL_DIV(16)>, 827 <&clockgen QORIQ_CLK_PLATFORM_PLL 828 QORIQ_CLK_PLL_DIV(16)>; 829 clock-names = "wdog_clk", "apb_pclk"; 830 }; 831 832 cluster1_core1_watchdog: watchdog@c010000 { 833 compatible = "arm,sp805", "arm,primecell"; 834 reg = <0x0 0xc010000 0x0 0x1000>; 835 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 836 QORIQ_CLK_PLL_DIV(16)>, 837 <&clockgen QORIQ_CLK_PLATFORM_PLL 838 QORIQ_CLK_PLL_DIV(16)>; 839 clock-names = "wdog_clk", "apb_pclk"; 840 }; 841 842 malidp0: display@f080000 { 843 compatible = "arm,mali-dp500"; 844 reg = <0x0 0xf080000 0x0 0x10000>; 845 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 846 <0 223 IRQ_TYPE_LEVEL_HIGH>; 847 interrupt-names = "DE", "SE"; 848 clocks = <&dpclk>, 849 <&clockgen QORIQ_CLK_HWACCEL 2>, 850 <&clockgen QORIQ_CLK_HWACCEL 2>, 851 <&clockgen QORIQ_CLK_HWACCEL 2>; 852 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 853 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 854 arm,malidp-arqos-value = <0xd000d000>; 855 856 port { 857 dpi0_out: endpoint { 858 859 }; 860 }; 861 }; 862 863 gpu: gpu@f0c0000 { 864 compatible = "vivante,gc"; 865 reg = <0x0 0xf0c0000 0x0 0x10000>; 866 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 868 <&clockgen QORIQ_CLK_HWACCEL 2>, 869 <&clockgen QORIQ_CLK_HWACCEL 2>; 870 clock-names = "core", "shader", "bus"; 871 #cooling-cells = <2>; 872 }; 873 874 sai1: audio-controller@f100000 { 875 #sound-dai-cells = <0>; 876 compatible = "fsl,vf610-sai"; 877 reg = <0x0 0xf100000 0x0 0x10000>; 878 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 880 QORIQ_CLK_PLL_DIV(2)>, 881 <&clockgen QORIQ_CLK_PLATFORM_PLL 882 QORIQ_CLK_PLL_DIV(2)>, 883 <&clockgen QORIQ_CLK_PLATFORM_PLL 884 QORIQ_CLK_PLL_DIV(2)>, 885 <&clockgen QORIQ_CLK_PLATFORM_PLL 886 QORIQ_CLK_PLL_DIV(2)>; 887 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 888 dma-names = "tx", "rx"; 889 dmas = <&edma0 1 4>, 890 <&edma0 1 3>; 891 fsl,sai-asynchronous; 892 status = "disabled"; 893 }; 894 895 sai2: audio-controller@f110000 { 896 #sound-dai-cells = <0>; 897 compatible = "fsl,vf610-sai"; 898 reg = <0x0 0xf110000 0x0 0x10000>; 899 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 901 QORIQ_CLK_PLL_DIV(2)>, 902 <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>, 904 <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(2)>, 906 <&clockgen QORIQ_CLK_PLATFORM_PLL 907 QORIQ_CLK_PLL_DIV(2)>; 908 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 909 dma-names = "tx", "rx"; 910 dmas = <&edma0 1 6>, 911 <&edma0 1 5>; 912 fsl,sai-asynchronous; 913 status = "disabled"; 914 }; 915 916 sai3: audio-controller@f120000 { 917 #sound-dai-cells = <0>; 918 compatible = "fsl,vf610-sai"; 919 reg = <0x0 0xf120000 0x0 0x10000>; 920 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 922 QORIQ_CLK_PLL_DIV(2)>, 923 <&clockgen QORIQ_CLK_PLATFORM_PLL 924 QORIQ_CLK_PLL_DIV(2)>, 925 <&clockgen QORIQ_CLK_PLATFORM_PLL 926 QORIQ_CLK_PLL_DIV(2)>, 927 <&clockgen QORIQ_CLK_PLATFORM_PLL 928 QORIQ_CLK_PLL_DIV(2)>; 929 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 930 dma-names = "tx", "rx"; 931 dmas = <&edma0 1 8>, 932 <&edma0 1 7>; 933 fsl,sai-asynchronous; 934 status = "disabled"; 935 }; 936 937 sai4: audio-controller@f130000 { 938 #sound-dai-cells = <0>; 939 compatible = "fsl,vf610-sai"; 940 reg = <0x0 0xf130000 0x0 0x10000>; 941 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 943 QORIQ_CLK_PLL_DIV(2)>, 944 <&clockgen QORIQ_CLK_PLATFORM_PLL 945 QORIQ_CLK_PLL_DIV(2)>, 946 <&clockgen QORIQ_CLK_PLATFORM_PLL 947 QORIQ_CLK_PLL_DIV(2)>, 948 <&clockgen QORIQ_CLK_PLATFORM_PLL 949 QORIQ_CLK_PLL_DIV(2)>; 950 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 951 dma-names = "tx", "rx"; 952 dmas = <&edma0 1 10>, 953 <&edma0 1 9>; 954 fsl,sai-asynchronous; 955 status = "disabled"; 956 }; 957 958 sai5: audio-controller@f140000 { 959 #sound-dai-cells = <0>; 960 compatible = "fsl,vf610-sai"; 961 reg = <0x0 0xf140000 0x0 0x10000>; 962 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 964 QORIQ_CLK_PLL_DIV(2)>, 965 <&clockgen QORIQ_CLK_PLATFORM_PLL 966 QORIQ_CLK_PLL_DIV(2)>, 967 <&clockgen QORIQ_CLK_PLATFORM_PLL 968 QORIQ_CLK_PLL_DIV(2)>, 969 <&clockgen QORIQ_CLK_PLATFORM_PLL 970 QORIQ_CLK_PLL_DIV(2)>; 971 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 972 dma-names = "tx", "rx"; 973 dmas = <&edma0 1 12>, 974 <&edma0 1 11>; 975 fsl,sai-asynchronous; 976 status = "disabled"; 977 }; 978 979 sai6: audio-controller@f150000 { 980 #sound-dai-cells = <0>; 981 compatible = "fsl,vf610-sai"; 982 reg = <0x0 0xf150000 0x0 0x10000>; 983 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 985 QORIQ_CLK_PLL_DIV(2)>, 986 <&clockgen QORIQ_CLK_PLATFORM_PLL 987 QORIQ_CLK_PLL_DIV(2)>, 988 <&clockgen QORIQ_CLK_PLATFORM_PLL 989 QORIQ_CLK_PLL_DIV(2)>, 990 <&clockgen QORIQ_CLK_PLATFORM_PLL 991 QORIQ_CLK_PLL_DIV(2)>; 992 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 993 dma-names = "tx", "rx"; 994 dmas = <&edma0 1 14>, 995 <&edma0 1 13>; 996 fsl,sai-asynchronous; 997 status = "disabled"; 998 }; 999 1000 dpclk: clock-controller@f1f0000 { 1001 compatible = "fsl,ls1028a-plldig"; 1002 reg = <0x0 0xf1f0000 0x0 0x10000>; 1003 #clock-cells = <0>; 1004 clocks = <&osc_27m>; 1005 }; 1006 1007 tmu: tmu@1f80000 { 1008 compatible = "fsl,qoriq-tmu"; 1009 reg = <0x0 0x1f80000 0x0 0x10000>; 1010 interrupts = <0 23 0x4>; 1011 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1012 fsl,tmu-calibration = <0x00000000 0x00000024 1013 0x00000001 0x0000002b 1014 0x00000002 0x00000031 1015 0x00000003 0x00000038 1016 0x00000004 0x0000003f 1017 0x00000005 0x00000045 1018 0x00000006 0x0000004c 1019 0x00000007 0x00000053 1020 0x00000008 0x00000059 1021 0x00000009 0x00000060 1022 0x0000000a 0x00000066 1023 0x0000000b 0x0000006d 1024 1025 0x00010000 0x0000001c 1026 0x00010001 0x00000024 1027 0x00010002 0x0000002c 1028 0x00010003 0x00000035 1029 0x00010004 0x0000003d 1030 0x00010005 0x00000045 1031 0x00010006 0x0000004d 1032 0x00010007 0x00000055 1033 0x00010008 0x0000005e 1034 0x00010009 0x00000066 1035 0x0001000a 0x0000006e 1036 1037 0x00020000 0x00000018 1038 0x00020001 0x00000022 1039 0x00020002 0x0000002d 1040 0x00020003 0x00000038 1041 0x00020004 0x00000043 1042 0x00020005 0x0000004d 1043 0x00020006 0x00000058 1044 0x00020007 0x00000063 1045 0x00020008 0x0000006e 1046 1047 0x00030000 0x00000010 1048 0x00030001 0x0000001c 1049 0x00030002 0x00000029 1050 0x00030003 0x00000036 1051 0x00030004 0x00000042 1052 0x00030005 0x0000004f 1053 0x00030006 0x0000005b 1054 0x00030007 0x00000068>; 1055 little-endian; 1056 #thermal-sensor-cells = <1>; 1057 }; 1058 1059 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1060 compatible = "pci-host-ecam-generic"; 1061 reg = <0x01 0xf0000000 0x0 0x100000>; 1062 #address-cells = <3>; 1063 #size-cells = <2>; 1064 msi-parent = <&its>; 1065 device_type = "pci"; 1066 bus-range = <0x0 0x0>; 1067 dma-coherent; 1068 msi-map = <0 &its 0x17 0xe>; 1069 iommu-map = <0 &smmu 0x17 0xe>; 1070 /* PF0-6 BAR0 - non-prefetchable memory */ 1071 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1072 /* PF0-6 BAR2 - prefetchable memory */ 1073 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1074 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1075 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1076 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1077 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1078 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1079 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1080 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1081 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1082 /* BAR4 (PF5) - non-prefetchable memory */ 1083 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1084 1085 enetc_port0: ethernet@0,0 { 1086 compatible = "fsl,enetc"; 1087 reg = <0x000000 0 0 0 0>; 1088 status = "disabled"; 1089 }; 1090 1091 enetc_port1: ethernet@0,1 { 1092 compatible = "fsl,enetc"; 1093 reg = <0x000100 0 0 0 0>; 1094 status = "disabled"; 1095 }; 1096 1097 enetc_port2: ethernet@0,2 { 1098 compatible = "fsl,enetc"; 1099 reg = <0x000200 0 0 0 0>; 1100 phy-mode = "internal"; 1101 status = "disabled"; 1102 1103 fixed-link { 1104 speed = <2500>; 1105 full-duplex; 1106 pause; 1107 }; 1108 }; 1109 1110 enetc_mdio_pf3: mdio@0,3 { 1111 compatible = "fsl,enetc-mdio"; 1112 reg = <0x000300 0 0 0 0>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 }; 1116 1117 ethernet@0,4 { 1118 compatible = "fsl,enetc-ptp"; 1119 reg = <0x000400 0 0 0 0>; 1120 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1121 little-endian; 1122 fsl,extts-fifo; 1123 }; 1124 1125 mscc_felix: ethernet-switch@0,5 { 1126 reg = <0x000500 0 0 0 0>; 1127 /* IEP INT_B */ 1128 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1129 status = "disabled"; 1130 1131 mscc_felix_ports: ports { 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 1135 /* External ports */ 1136 mscc_felix_port0: port@0 { 1137 reg = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 mscc_felix_port1: port@1 { 1142 reg = <1>; 1143 status = "disabled"; 1144 }; 1145 1146 mscc_felix_port2: port@2 { 1147 reg = <2>; 1148 status = "disabled"; 1149 }; 1150 1151 mscc_felix_port3: port@3 { 1152 reg = <3>; 1153 status = "disabled"; 1154 }; 1155 1156 /* Internal ports */ 1157 mscc_felix_port4: port@4 { 1158 reg = <4>; 1159 phy-mode = "internal"; 1160 ethernet = <&enetc_port2>; 1161 status = "disabled"; 1162 1163 fixed-link { 1164 speed = <2500>; 1165 full-duplex; 1166 pause; 1167 }; 1168 }; 1169 1170 mscc_felix_port5: port@5 { 1171 reg = <5>; 1172 phy-mode = "internal"; 1173 ethernet = <&enetc_port3>; 1174 status = "disabled"; 1175 1176 fixed-link { 1177 speed = <1000>; 1178 full-duplex; 1179 pause; 1180 }; 1181 }; 1182 }; 1183 }; 1184 1185 enetc_port3: ethernet@0,6 { 1186 compatible = "fsl,enetc"; 1187 reg = <0x000600 0 0 0 0>; 1188 phy-mode = "internal"; 1189 status = "disabled"; 1190 1191 fixed-link { 1192 speed = <1000>; 1193 full-duplex; 1194 pause; 1195 }; 1196 }; 1197 1198 rcec@1f,0 { 1199 reg = <0x00f800 0 0 0 0>; 1200 /* IEP INT_A */ 1201 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1202 }; 1203 }; 1204 1205 /* Integrated Endpoint Register Block */ 1206 ierb@1f0800000 { 1207 compatible = "fsl,ls1028a-enetc-ierb"; 1208 reg = <0x01 0xf0800000 0x0 0x10000>; 1209 }; 1210 1211 pwm0: pwm@2800000 { 1212 compatible = "fsl,vf610-ftm-pwm"; 1213 #pwm-cells = <3>; 1214 reg = <0x0 0x2800000 0x0 0x10000>; 1215 clock-names = "ftm_sys", "ftm_ext", 1216 "ftm_fix", "ftm_cnt_clk_en"; 1217 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1218 <&rtc_clk>, <&clockgen 4 1>; 1219 status = "disabled"; 1220 }; 1221 1222 pwm1: pwm@2810000 { 1223 compatible = "fsl,vf610-ftm-pwm"; 1224 #pwm-cells = <3>; 1225 reg = <0x0 0x2810000 0x0 0x10000>; 1226 clock-names = "ftm_sys", "ftm_ext", 1227 "ftm_fix", "ftm_cnt_clk_en"; 1228 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1229 <&rtc_clk>, <&clockgen 4 1>; 1230 status = "disabled"; 1231 }; 1232 1233 pwm2: pwm@2820000 { 1234 compatible = "fsl,vf610-ftm-pwm"; 1235 #pwm-cells = <3>; 1236 reg = <0x0 0x2820000 0x0 0x10000>; 1237 clock-names = "ftm_sys", "ftm_ext", 1238 "ftm_fix", "ftm_cnt_clk_en"; 1239 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1240 <&rtc_clk>, <&clockgen 4 1>; 1241 status = "disabled"; 1242 }; 1243 1244 pwm3: pwm@2830000 { 1245 compatible = "fsl,vf610-ftm-pwm"; 1246 #pwm-cells = <3>; 1247 reg = <0x0 0x2830000 0x0 0x10000>; 1248 clock-names = "ftm_sys", "ftm_ext", 1249 "ftm_fix", "ftm_cnt_clk_en"; 1250 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1251 <&rtc_clk>, <&clockgen 4 1>; 1252 status = "disabled"; 1253 }; 1254 1255 pwm4: pwm@2840000 { 1256 compatible = "fsl,vf610-ftm-pwm"; 1257 #pwm-cells = <3>; 1258 reg = <0x0 0x2840000 0x0 0x10000>; 1259 clock-names = "ftm_sys", "ftm_ext", 1260 "ftm_fix", "ftm_cnt_clk_en"; 1261 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1262 <&rtc_clk>, <&clockgen 4 1>; 1263 status = "disabled"; 1264 }; 1265 1266 pwm5: pwm@2850000 { 1267 compatible = "fsl,vf610-ftm-pwm"; 1268 #pwm-cells = <3>; 1269 reg = <0x0 0x2850000 0x0 0x10000>; 1270 clock-names = "ftm_sys", "ftm_ext", 1271 "ftm_fix", "ftm_cnt_clk_en"; 1272 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1273 <&rtc_clk>, <&clockgen 4 1>; 1274 status = "disabled"; 1275 }; 1276 1277 pwm6: pwm@2860000 { 1278 compatible = "fsl,vf610-ftm-pwm"; 1279 #pwm-cells = <3>; 1280 reg = <0x0 0x2860000 0x0 0x10000>; 1281 clock-names = "ftm_sys", "ftm_ext", 1282 "ftm_fix", "ftm_cnt_clk_en"; 1283 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1284 <&rtc_clk>, <&clockgen 4 1>; 1285 status = "disabled"; 1286 }; 1287 1288 pwm7: pwm@2870000 { 1289 compatible = "fsl,vf610-ftm-pwm"; 1290 #pwm-cells = <3>; 1291 reg = <0x0 0x2870000 0x0 0x10000>; 1292 clock-names = "ftm_sys", "ftm_ext", 1293 "ftm_fix", "ftm_cnt_clk_en"; 1294 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1295 <&rtc_clk>, <&clockgen 4 1>; 1296 status = "disabled"; 1297 }; 1298 1299 rcpm: power-controller@1e34040 { 1300 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1301 reg = <0x0 0x1e34040 0x0 0x1c>; 1302 #fsl,rcpm-wakeup-cells = <7>; 1303 little-endian; 1304 }; 1305 1306 ftm_alarm0: timer@2800000 { 1307 compatible = "fsl,ls1028a-ftm-alarm"; 1308 reg = <0x0 0x2800000 0x0 0x10000>; 1309 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1310 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1311 status = "disabled"; 1312 }; 1313 1314 ftm_alarm1: timer@2810000 { 1315 compatible = "fsl,ls1028a-ftm-alarm"; 1316 reg = <0x0 0x2810000 0x0 0x10000>; 1317 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1318 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1319 status = "disabled"; 1320 }; 1321 }; 1322 1323}; 1324