18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 5f7d48ffcSWasim Khan * Copyright 2018-2020 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 20791c88caSBiwen Li aliases { 21791c88caSBiwen Li rtc1 = &ftm_alarm0; 22791c88caSBiwen Li }; 23791c88caSBiwen Li 248897f325SBhaskar Upadhaya cpus { 258897f325SBhaskar Upadhaya #address-cells = <1>; 268897f325SBhaskar Upadhaya #size-cells = <0>; 278897f325SBhaskar Upadhaya 288897f325SBhaskar Upadhaya cpu0: cpu@0 { 298897f325SBhaskar Upadhaya device_type = "cpu"; 308897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 318897f325SBhaskar Upadhaya reg = <0x0>; 328897f325SBhaskar Upadhaya enable-method = "psci"; 338897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 348897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3553f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 36571cebfeSYuantian Tang #cooling-cells = <2>; 378897f325SBhaskar Upadhaya }; 388897f325SBhaskar Upadhaya 398897f325SBhaskar Upadhaya cpu1: cpu@1 { 408897f325SBhaskar Upadhaya device_type = "cpu"; 418897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 428897f325SBhaskar Upadhaya reg = <0x1>; 438897f325SBhaskar Upadhaya enable-method = "psci"; 448897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 458897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4653f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 47571cebfeSYuantian Tang #cooling-cells = <2>; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya 508897f325SBhaskar Upadhaya l2: l2-cache { 518897f325SBhaskar Upadhaya compatible = "cache"; 528897f325SBhaskar Upadhaya }; 538897f325SBhaskar Upadhaya }; 548897f325SBhaskar Upadhaya 558897f325SBhaskar Upadhaya idle-states { 568897f325SBhaskar Upadhaya /* 578897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 588897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 598897f325SBhaskar Upadhaya */ 609b631649SLinus Walleij entry-method = "psci"; 618897f325SBhaskar Upadhaya 6253f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 638897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6453f2ac9dSRan Wang idle-state-name = "PW20"; 6553f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6653f2ac9dSRan Wang entry-latency-us = <2000>; 6753f2ac9dSRan Wang exit-latency-us = <2000>; 6853f2ac9dSRan Wang min-residency-us = <6000>; 698897f325SBhaskar Upadhaya }; 708897f325SBhaskar Upadhaya }; 718897f325SBhaskar Upadhaya 728897f325SBhaskar Upadhaya sysclk: clock-sysclk { 738897f325SBhaskar Upadhaya compatible = "fixed-clock"; 748897f325SBhaskar Upadhaya #clock-cells = <0>; 758897f325SBhaskar Upadhaya clock-frequency = <100000000>; 768897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 778897f325SBhaskar Upadhaya }; 788897f325SBhaskar Upadhaya 7981f36887SWen He osc_27m: clock-osc-27m { 807f538f19SWen He compatible = "fixed-clock"; 817f538f19SWen He #clock-cells = <0>; 827f538f19SWen He clock-frequency = <27000000>; 8381f36887SWen He clock-output-names = "phy_27m"; 8481f36887SWen He }; 8581f36887SWen He 8681f36887SWen He dpclk: clock-controller@f1f0000 { 8781f36887SWen He compatible = "fsl,ls1028a-plldig"; 8881f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8991035cb0SWen He #clock-cells = <0>; 9081f36887SWen He clocks = <&osc_27m>; 917f538f19SWen He }; 927f538f19SWen He 93*f90931aeSMichael Walle firmware { 94*f90931aeSMichael Walle optee { 95*f90931aeSMichael Walle compatible = "linaro,optee-tz"; 96*f90931aeSMichael Walle method = "smc"; 97*f90931aeSMichael Walle status = "disabled"; 98*f90931aeSMichael Walle }; 99*f90931aeSMichael Walle }; 100*f90931aeSMichael Walle 1018897f325SBhaskar Upadhaya reboot { 1028897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 1033f0fb37bSMichael Walle regmap = <&rst>; 1048897f325SBhaskar Upadhaya offset = <0xb0>; 1058897f325SBhaskar Upadhaya mask = <0x02>; 1068897f325SBhaskar Upadhaya }; 1078897f325SBhaskar Upadhaya 1088897f325SBhaskar Upadhaya timer { 1098897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 1108897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 1118897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1128897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1138897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1148897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1158897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1168897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1178897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1188897f325SBhaskar Upadhaya }; 1198897f325SBhaskar Upadhaya 120b9eb314aSAlison Wang pmu { 121b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 122b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 123b9eb314aSAlison Wang }; 124b9eb314aSAlison Wang 1258897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1268897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1278897f325SBhaskar Upadhaya #address-cells = <2>; 1288897f325SBhaskar Upadhaya #size-cells = <2>; 1298897f325SBhaskar Upadhaya ranges; 1308897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1318897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1328897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1338897f325SBhaskar Upadhaya interrupt-controller; 1348897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1358897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1368897f325SBhaskar Upadhaya its: gic-its@6020000 { 1378897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1388897f325SBhaskar Upadhaya msi-controller; 1398897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1408897f325SBhaskar Upadhaya }; 1418897f325SBhaskar Upadhaya }; 1428897f325SBhaskar Upadhaya 14368e36a42SFabio Estevam thermal-zones { 1443269c178SYuantian Tang ddr-controller { 14568e36a42SFabio Estevam polling-delay-passive = <1000>; 14668e36a42SFabio Estevam polling-delay = <5000>; 14768e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 14868e36a42SFabio Estevam 14968e36a42SFabio Estevam trips { 1503269c178SYuantian Tang ddr-ctrler-alert { 1513269c178SYuantian Tang temperature = <85000>; 1523269c178SYuantian Tang hysteresis = <2000>; 1533269c178SYuantian Tang type = "passive"; 1543269c178SYuantian Tang }; 1553269c178SYuantian Tang 1563269c178SYuantian Tang ddr-ctrler-crit { 1573269c178SYuantian Tang temperature = <95000>; 1583269c178SYuantian Tang hysteresis = <2000>; 1593269c178SYuantian Tang type = "critical"; 1603269c178SYuantian Tang }; 1613269c178SYuantian Tang }; 1623269c178SYuantian Tang }; 1633269c178SYuantian Tang 1643269c178SYuantian Tang core-cluster { 1653269c178SYuantian Tang polling-delay-passive = <1000>; 1663269c178SYuantian Tang polling-delay = <5000>; 1673269c178SYuantian Tang thermal-sensors = <&tmu 1>; 1683269c178SYuantian Tang 1693269c178SYuantian Tang trips { 17068e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 17168e36a42SFabio Estevam temperature = <85000>; 17268e36a42SFabio Estevam hysteresis = <2000>; 17368e36a42SFabio Estevam type = "passive"; 17468e36a42SFabio Estevam }; 17568e36a42SFabio Estevam 17668e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 17768e36a42SFabio Estevam temperature = <95000>; 17868e36a42SFabio Estevam hysteresis = <2000>; 17968e36a42SFabio Estevam type = "critical"; 18068e36a42SFabio Estevam }; 18168e36a42SFabio Estevam }; 18268e36a42SFabio Estevam 18368e36a42SFabio Estevam cooling-maps { 18468e36a42SFabio Estevam map0 { 18568e36a42SFabio Estevam trip = <&core_cluster_alert>; 18668e36a42SFabio Estevam cooling-device = 18768e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 18868e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 18968e36a42SFabio Estevam }; 19068e36a42SFabio Estevam }; 19168e36a42SFabio Estevam }; 19268e36a42SFabio Estevam }; 19368e36a42SFabio Estevam 1948897f325SBhaskar Upadhaya soc: soc { 1958897f325SBhaskar Upadhaya compatible = "simple-bus"; 1968897f325SBhaskar Upadhaya #address-cells = <2>; 1978897f325SBhaskar Upadhaya #size-cells = <2>; 1988897f325SBhaskar Upadhaya ranges; 1998897f325SBhaskar Upadhaya 2008897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 2018897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 2028897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 2038897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2048897f325SBhaskar Upadhaya big-endian; 2058897f325SBhaskar Upadhaya }; 2068897f325SBhaskar Upadhaya 2078897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 2088897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 2098897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 21033eae7fbSYinbo Zhu little-endian; 2118897f325SBhaskar Upadhaya }; 2128897f325SBhaskar Upadhaya 2133f0fb37bSMichael Walle rst: syscon@1e60000 { 2143f0fb37bSMichael Walle compatible = "syscon"; 2153f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 2163f0fb37bSMichael Walle little-endian; 2173f0fb37bSMichael Walle }; 2183f0fb37bSMichael Walle 2198897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 2208897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 2218897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 2228897f325SBhaskar Upadhaya big-endian; 2238897f325SBhaskar Upadhaya }; 2248897f325SBhaskar Upadhaya 2258897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 2268897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 2278897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 2288897f325SBhaskar Upadhaya #clock-cells = <2>; 2298897f325SBhaskar Upadhaya clocks = <&sysclk>; 2308897f325SBhaskar Upadhaya }; 2318897f325SBhaskar Upadhaya 2328897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2338897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2348897f325SBhaskar Upadhaya #address-cells = <1>; 2358897f325SBhaskar Upadhaya #size-cells = <0>; 2368897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2378897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 238ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2398897f325SBhaskar Upadhaya status = "disabled"; 2408897f325SBhaskar Upadhaya }; 2418897f325SBhaskar Upadhaya 2428897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2438897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2448897f325SBhaskar Upadhaya #address-cells = <1>; 2458897f325SBhaskar Upadhaya #size-cells = <0>; 2468897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2478897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 248ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2498897f325SBhaskar Upadhaya status = "disabled"; 2508897f325SBhaskar Upadhaya }; 2518897f325SBhaskar Upadhaya 2528897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2538897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2548897f325SBhaskar Upadhaya #address-cells = <1>; 2558897f325SBhaskar Upadhaya #size-cells = <0>; 2568897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2578897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 258ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2598897f325SBhaskar Upadhaya status = "disabled"; 2608897f325SBhaskar Upadhaya }; 2618897f325SBhaskar Upadhaya 2628897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2638897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2648897f325SBhaskar Upadhaya #address-cells = <1>; 2658897f325SBhaskar Upadhaya #size-cells = <0>; 2668897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2678897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 268ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2698897f325SBhaskar Upadhaya status = "disabled"; 2708897f325SBhaskar Upadhaya }; 2718897f325SBhaskar Upadhaya 2728897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2738897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2748897f325SBhaskar Upadhaya #address-cells = <1>; 2758897f325SBhaskar Upadhaya #size-cells = <0>; 2768897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2778897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 278ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2798897f325SBhaskar Upadhaya status = "disabled"; 2808897f325SBhaskar Upadhaya }; 2818897f325SBhaskar Upadhaya 2828897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2838897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2848897f325SBhaskar Upadhaya #address-cells = <1>; 2858897f325SBhaskar Upadhaya #size-cells = <0>; 2868897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2878897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 288ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2898897f325SBhaskar Upadhaya status = "disabled"; 2908897f325SBhaskar Upadhaya }; 2918897f325SBhaskar Upadhaya 2928897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2938897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2948897f325SBhaskar Upadhaya #address-cells = <1>; 2958897f325SBhaskar Upadhaya #size-cells = <0>; 2968897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2978897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 298ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2998897f325SBhaskar Upadhaya status = "disabled"; 3008897f325SBhaskar Upadhaya }; 3018897f325SBhaskar Upadhaya 3028897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 3038897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3048897f325SBhaskar Upadhaya #address-cells = <1>; 3058897f325SBhaskar Upadhaya #size-cells = <0>; 3068897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 3078897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 308ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 3098897f325SBhaskar Upadhaya status = "disabled"; 3108897f325SBhaskar Upadhaya }; 3118897f325SBhaskar Upadhaya 312c77fae5bSAshish Kumar fspi: spi@20c0000 { 313c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 314c77fae5bSAshish Kumar #address-cells = <1>; 315c77fae5bSAshish Kumar #size-cells = <0>; 316c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 317c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 318c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 319c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 320588b17edSMichael Walle clocks = <&clockgen 2 0>, <&clockgen 2 0>; 321c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 322c77fae5bSAshish Kumar status = "disabled"; 323c77fae5bSAshish Kumar }; 324c77fae5bSAshish Kumar 325c2d35adaSMichael Walle dspi0: spi@2100000 { 326c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 327c2d35adaSMichael Walle #address-cells = <1>; 328c2d35adaSMichael Walle #size-cells = <0>; 329c2d35adaSMichael Walle reg = <0x0 0x2100000 0x0 0x10000>; 330c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 331c2d35adaSMichael Walle clock-names = "dspi"; 332c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 333dd12fa69SVladimir Oltean dmas = <&edma0 0 62>, <&edma0 0 60>; 334dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 335c2d35adaSMichael Walle spi-num-chipselects = <4>; 336c2d35adaSMichael Walle little-endian; 337c2d35adaSMichael Walle status = "disabled"; 338c2d35adaSMichael Walle }; 339c2d35adaSMichael Walle 340c2d35adaSMichael Walle dspi1: spi@2110000 { 341c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 342c2d35adaSMichael Walle #address-cells = <1>; 343c2d35adaSMichael Walle #size-cells = <0>; 344c2d35adaSMichael Walle reg = <0x0 0x2110000 0x0 0x10000>; 345c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 346c2d35adaSMichael Walle clock-names = "dspi"; 347c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 348dd12fa69SVladimir Oltean dmas = <&edma0 0 58>, <&edma0 0 56>; 349dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 350c2d35adaSMichael Walle spi-num-chipselects = <4>; 351c2d35adaSMichael Walle little-endian; 352c2d35adaSMichael Walle status = "disabled"; 353c2d35adaSMichael Walle }; 354c2d35adaSMichael Walle 355c2d35adaSMichael Walle dspi2: spi@2120000 { 356c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 357c2d35adaSMichael Walle #address-cells = <1>; 358c2d35adaSMichael Walle #size-cells = <0>; 359c2d35adaSMichael Walle reg = <0x0 0x2120000 0x0 0x10000>; 360c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 361c2d35adaSMichael Walle clock-names = "dspi"; 362c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 363dd12fa69SVladimir Oltean dmas = <&edma0 0 54>, <&edma0 0 2>; 364dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 365c2d35adaSMichael Walle spi-num-chipselects = <3>; 366c2d35adaSMichael Walle little-endian; 367c2d35adaSMichael Walle status = "disabled"; 368c2d35adaSMichael Walle }; 369c2d35adaSMichael Walle 370491d3a3fSAshish Kumar esdhc: mmc@2140000 { 371491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 372491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 373491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 374491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 375491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 376491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 377491d3a3fSAshish Kumar sdhci,auto-cmd12; 378491d3a3fSAshish Kumar little-endian; 379491d3a3fSAshish Kumar bus-width = <4>; 380491d3a3fSAshish Kumar status = "disabled"; 381491d3a3fSAshish Kumar }; 382491d3a3fSAshish Kumar 383491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 384491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 385491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 386491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 387491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 388491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 389491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 390491d3a3fSAshish Kumar sdhci,auto-cmd12; 391491d3a3fSAshish Kumar broken-cd; 392491d3a3fSAshish Kumar little-endian; 393491d3a3fSAshish Kumar bus-width = <4>; 394491d3a3fSAshish Kumar status = "disabled"; 395491d3a3fSAshish Kumar }; 396491d3a3fSAshish Kumar 39704fa4f03SMichael Walle can0: can@2180000 { 39804fa4f03SMichael Walle compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; 39904fa4f03SMichael Walle reg = <0x0 0x2180000 0x0 0x10000>; 40004fa4f03SMichael Walle interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 40104fa4f03SMichael Walle clocks = <&sysclk>, <&clockgen 4 1>; 40204fa4f03SMichael Walle clock-names = "ipg", "per"; 40304fa4f03SMichael Walle status = "disabled"; 40404fa4f03SMichael Walle }; 40504fa4f03SMichael Walle 40604fa4f03SMichael Walle can1: can@2190000 { 40704fa4f03SMichael Walle compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; 40804fa4f03SMichael Walle reg = <0x0 0x2190000 0x0 0x10000>; 40904fa4f03SMichael Walle interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 41004fa4f03SMichael Walle clocks = <&sysclk>, <&clockgen 4 1>; 41104fa4f03SMichael Walle clock-names = "ipg", "per"; 41204fa4f03SMichael Walle status = "disabled"; 41304fa4f03SMichael Walle }; 41404fa4f03SMichael Walle 4158897f325SBhaskar Upadhaya duart0: serial@21c0500 { 4168897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 4178897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 4188897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4198897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 4208897f325SBhaskar Upadhaya status = "disabled"; 4218897f325SBhaskar Upadhaya }; 4228897f325SBhaskar Upadhaya 4238897f325SBhaskar Upadhaya duart1: serial@21c0600 { 4248897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 4258897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 4268897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4278897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 4288897f325SBhaskar Upadhaya status = "disabled"; 4298897f325SBhaskar Upadhaya }; 4308897f325SBhaskar Upadhaya 4312607d724SMichael Walle 4322607d724SMichael Walle lpuart0: serial@2260000 { 4332607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4342607d724SMichael Walle reg = <0x0 0x2260000 0x0 0x1000>; 4352607d724SMichael Walle interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 4362607d724SMichael Walle clocks = <&clockgen 4 1>; 4372607d724SMichael Walle clock-names = "ipg"; 4382607d724SMichael Walle dma-names = "rx","tx"; 4392607d724SMichael Walle dmas = <&edma0 1 32>, 4402607d724SMichael Walle <&edma0 1 33>; 4412607d724SMichael Walle status = "disabled"; 4422607d724SMichael Walle }; 4432607d724SMichael Walle 4442607d724SMichael Walle lpuart1: serial@2270000 { 4452607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4462607d724SMichael Walle reg = <0x0 0x2270000 0x0 0x1000>; 4472607d724SMichael Walle interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 4482607d724SMichael Walle clocks = <&clockgen 4 1>; 4492607d724SMichael Walle clock-names = "ipg"; 4502607d724SMichael Walle dma-names = "rx","tx"; 4512607d724SMichael Walle dmas = <&edma0 1 30>, 4522607d724SMichael Walle <&edma0 1 31>; 4532607d724SMichael Walle status = "disabled"; 4542607d724SMichael Walle }; 4552607d724SMichael Walle 4562607d724SMichael Walle lpuart2: serial@2280000 { 4572607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4582607d724SMichael Walle reg = <0x0 0x2280000 0x0 0x1000>; 4592607d724SMichael Walle interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 4602607d724SMichael Walle clocks = <&clockgen 4 1>; 4612607d724SMichael Walle clock-names = "ipg"; 4622607d724SMichael Walle dma-names = "rx","tx"; 4632607d724SMichael Walle dmas = <&edma0 1 28>, 4642607d724SMichael Walle <&edma0 1 29>; 4652607d724SMichael Walle status = "disabled"; 4662607d724SMichael Walle }; 4672607d724SMichael Walle 4682607d724SMichael Walle lpuart3: serial@2290000 { 4692607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4702607d724SMichael Walle reg = <0x0 0x2290000 0x0 0x1000>; 4712607d724SMichael Walle interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 4722607d724SMichael Walle clocks = <&clockgen 4 1>; 4732607d724SMichael Walle clock-names = "ipg"; 4742607d724SMichael Walle dma-names = "rx","tx"; 4752607d724SMichael Walle dmas = <&edma0 1 26>, 4762607d724SMichael Walle <&edma0 1 27>; 4772607d724SMichael Walle status = "disabled"; 4782607d724SMichael Walle }; 4792607d724SMichael Walle 4802607d724SMichael Walle lpuart4: serial@22a0000 { 4812607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4822607d724SMichael Walle reg = <0x0 0x22a0000 0x0 0x1000>; 4832607d724SMichael Walle interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 4842607d724SMichael Walle clocks = <&clockgen 4 1>; 4852607d724SMichael Walle clock-names = "ipg"; 4862607d724SMichael Walle dma-names = "rx","tx"; 4872607d724SMichael Walle dmas = <&edma0 1 24>, 4882607d724SMichael Walle <&edma0 1 25>; 4892607d724SMichael Walle status = "disabled"; 4902607d724SMichael Walle }; 4912607d724SMichael Walle 4922607d724SMichael Walle lpuart5: serial@22b0000 { 4932607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4942607d724SMichael Walle reg = <0x0 0x22b0000 0x0 0x1000>; 4952607d724SMichael Walle interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 4962607d724SMichael Walle clocks = <&clockgen 4 1>; 4972607d724SMichael Walle clock-names = "ipg"; 4982607d724SMichael Walle dma-names = "rx","tx"; 4992607d724SMichael Walle dmas = <&edma0 1 22>, 5002607d724SMichael Walle <&edma0 1 23>; 5012607d724SMichael Walle status = "disabled"; 5022607d724SMichael Walle }; 5032607d724SMichael Walle 504f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 505f54f7be5SAlison Wang #dma-cells = <2>; 506e0d7856eSMichael Walle compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 507f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 508f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 509f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 510f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 511f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 512f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 513f54f7be5SAlison Wang dma-channels = <32>; 514f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 515f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 516f54f7be5SAlison Wang <&clockgen 4 1>; 517f54f7be5SAlison Wang }; 518f54f7be5SAlison Wang 5198897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 520f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5218897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 5228897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5238897f325SBhaskar Upadhaya gpio-controller; 5248897f325SBhaskar Upadhaya #gpio-cells = <2>; 5258897f325SBhaskar Upadhaya interrupt-controller; 5268897f325SBhaskar Upadhaya #interrupt-cells = <2>; 527f64697bdSSong Hui little-endian; 5288897f325SBhaskar Upadhaya }; 5298897f325SBhaskar Upadhaya 5308897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 531f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5328897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 5338897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5348897f325SBhaskar Upadhaya gpio-controller; 5358897f325SBhaskar Upadhaya #gpio-cells = <2>; 5368897f325SBhaskar Upadhaya interrupt-controller; 5378897f325SBhaskar Upadhaya #interrupt-cells = <2>; 538f64697bdSSong Hui little-endian; 5398897f325SBhaskar Upadhaya }; 5408897f325SBhaskar Upadhaya 5418897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 542f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5438897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 5448897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 5458897f325SBhaskar Upadhaya gpio-controller; 5468897f325SBhaskar Upadhaya #gpio-cells = <2>; 5478897f325SBhaskar Upadhaya interrupt-controller; 5488897f325SBhaskar Upadhaya #interrupt-cells = <2>; 549f64697bdSSong Hui little-endian; 5508897f325SBhaskar Upadhaya }; 5518897f325SBhaskar Upadhaya 552c92f56faSRan Wang usb0: usb@3100000 { 553c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 554c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 555c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 556c92f56faSRan Wang dr_mode = "host"; 557c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 558c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 559c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 560c92f56faSRan Wang }; 561c92f56faSRan Wang 562c92f56faSRan Wang usb1: usb@3110000 { 563c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 564c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 565c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 566c92f56faSRan Wang dr_mode = "host"; 567c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 568c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 569c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 5708897f325SBhaskar Upadhaya }; 5718897f325SBhaskar Upadhaya 5728897f325SBhaskar Upadhaya sata: sata@3200000 { 5738897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 5748897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 5753f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 5768897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 5778897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 5788897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 5798897f325SBhaskar Upadhaya status = "disabled"; 5808897f325SBhaskar Upadhaya }; 5818897f325SBhaskar Upadhaya 582f7d48ffcSWasim Khan pcie1: pcie@3400000 { 583f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 584f6ff3f6dSXiaowei Bao reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 585f6ff3f6dSXiaowei Bao 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 586f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 587f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 588f6ff3f6dSXiaowei Bao <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 589f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 590f6ff3f6dSXiaowei Bao #address-cells = <3>; 591f6ff3f6dSXiaowei Bao #size-cells = <2>; 592f6ff3f6dSXiaowei Bao device_type = "pci"; 593f6ff3f6dSXiaowei Bao dma-coherent; 594f6ff3f6dSXiaowei Bao num-viewport = <8>; 595f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 596f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 597f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 598f6ff3f6dSXiaowei Bao msi-parent = <&its>; 599f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 600f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 601f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 602f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 603f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 604f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 605f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 606f6ff3f6dSXiaowei Bao status = "disabled"; 607f6ff3f6dSXiaowei Bao }; 608f6ff3f6dSXiaowei Bao 609f7d48ffcSWasim Khan pcie2: pcie@3500000 { 610f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 611f6ff3f6dSXiaowei Bao reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 612f6ff3f6dSXiaowei Bao 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 613f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 614f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 615f6ff3f6dSXiaowei Bao <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 616f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 617f6ff3f6dSXiaowei Bao #address-cells = <3>; 618f6ff3f6dSXiaowei Bao #size-cells = <2>; 619f6ff3f6dSXiaowei Bao device_type = "pci"; 620f6ff3f6dSXiaowei Bao dma-coherent; 621f6ff3f6dSXiaowei Bao num-viewport = <8>; 622f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 623f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 624f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 625f6ff3f6dSXiaowei Bao msi-parent = <&its>; 626f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 627f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 628f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 629f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 630f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 631f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 632f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 633f6ff3f6dSXiaowei Bao status = "disabled"; 634f6ff3f6dSXiaowei Bao }; 635f6ff3f6dSXiaowei Bao 6368897f325SBhaskar Upadhaya smmu: iommu@5000000 { 6378897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 6388897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 6398897f325SBhaskar Upadhaya #global-interrupts = <8>; 6408897f325SBhaskar Upadhaya #iommu-cells = <1>; 6418897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 6428897f325SBhaskar Upadhaya /* global secure fault */ 6438897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 6448897f325SBhaskar Upadhaya /* combined secure interrupt */ 6458897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 6468897f325SBhaskar Upadhaya /* global non-secure fault */ 6478897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 6488897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 6498897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 6508897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 6518897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 6528897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 6538897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 6548897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6558897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6568897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 6578897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 6588897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 6598897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 6608897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 6618897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 6628897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 6638897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 6648897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 6658897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 6668897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 6678897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 6688897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 6698897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 6708897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 6718897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6728897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6738897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6748897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6758897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6768897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6778897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 6788897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 6798897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 6808897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 6818897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 6828897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 6838897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 6848897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 6858897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 6868897f325SBhaskar Upadhaya }; 687927d7f85SClaudiu Manoil 6881d0becabSHoria Geantă crypto: crypto@8000000 { 6891d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 6901d0becabSHoria Geantă fsl,sec-era = <10>; 6911d0becabSHoria Geantă #address-cells = <1>; 6921d0becabSHoria Geantă #size-cells = <1>; 6931d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 6941d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 6951d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 6961d0becabSHoria Geantă dma-coherent; 6971d0becabSHoria Geantă 6981d0becabSHoria Geantă sec_jr0: jr@10000 { 6991d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7001d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7011d0becabSHoria Geantă reg = <0x10000 0x10000>; 7021d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 7031d0becabSHoria Geantă }; 7041d0becabSHoria Geantă 7051d0becabSHoria Geantă sec_jr1: jr@20000 { 7061d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7071d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7081d0becabSHoria Geantă reg = <0x20000 0x10000>; 7091d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 7101d0becabSHoria Geantă }; 7111d0becabSHoria Geantă 7121d0becabSHoria Geantă sec_jr2: jr@30000 { 7131d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7141d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7151d0becabSHoria Geantă reg = <0x30000 0x10000>; 7161d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 7171d0becabSHoria Geantă }; 7181d0becabSHoria Geantă 7191d0becabSHoria Geantă sec_jr3: jr@40000 { 7201d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7211d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7221d0becabSHoria Geantă reg = <0x40000 0x10000>; 7231d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 7241d0becabSHoria Geantă }; 7251d0becabSHoria Geantă }; 7261d0becabSHoria Geantă 7277802f88dSPeng Ma qdma: dma-controller@8380000 { 7287802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 7297802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 7307802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 7317802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 7327802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 7337802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 7347802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 7357802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 7367802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 7377802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 7387802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 7397802f88dSPeng Ma dma-channels = <8>; 7407802f88dSPeng Ma block-number = <1>; 7417802f88dSPeng Ma block-offset = <0x10000>; 7427802f88dSPeng Ma fsl,dma-queues = <2>; 7437802f88dSPeng Ma status-sizes = <64>; 7447802f88dSPeng Ma queue-sizes = <64 64>; 7457802f88dSPeng Ma }; 7467802f88dSPeng Ma 74757aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 74857aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 74957aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 75057aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 751f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 75257aa1bc7SChuanhua Han }; 75357aa1bc7SChuanhua Han 75457aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 75557aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 75657aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 75757aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 758f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 75957aa1bc7SChuanhua Han }; 76057aa1bc7SChuanhua Han 761f54f7be5SAlison Wang sai1: audio-controller@f100000 { 762f54f7be5SAlison Wang #sound-dai-cells = <0>; 763f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 764f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 765f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 766f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 767f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 768f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 769f54f7be5SAlison Wang dma-names = "tx", "rx"; 770f54f7be5SAlison Wang dmas = <&edma0 1 4>, 771f54f7be5SAlison Wang <&edma0 1 3>; 7729c015e13SMichael Walle fsl,sai-asynchronous; 773f54f7be5SAlison Wang status = "disabled"; 774f54f7be5SAlison Wang }; 775f54f7be5SAlison Wang 776f54f7be5SAlison Wang sai2: audio-controller@f110000 { 777f54f7be5SAlison Wang #sound-dai-cells = <0>; 778f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 779f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 780f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 781f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 782f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 783f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 784f54f7be5SAlison Wang dma-names = "tx", "rx"; 785f54f7be5SAlison Wang dmas = <&edma0 1 6>, 786f54f7be5SAlison Wang <&edma0 1 5>; 7879c015e13SMichael Walle fsl,sai-asynchronous; 788f54f7be5SAlison Wang status = "disabled"; 789f54f7be5SAlison Wang }; 790f54f7be5SAlison Wang 791434f9cc1SMichael Walle sai3: audio-controller@f120000 { 792434f9cc1SMichael Walle #sound-dai-cells = <0>; 793434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 794434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 795434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 796434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 797434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 798434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 799434f9cc1SMichael Walle dma-names = "tx", "rx"; 800434f9cc1SMichael Walle dmas = <&edma0 1 8>, 801434f9cc1SMichael Walle <&edma0 1 7>; 8029c015e13SMichael Walle fsl,sai-asynchronous; 803f54f7be5SAlison Wang status = "disabled"; 804f54f7be5SAlison Wang }; 805f54f7be5SAlison Wang 806f54f7be5SAlison Wang sai4: audio-controller@f130000 { 807f54f7be5SAlison Wang #sound-dai-cells = <0>; 808f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 809f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 810f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 811f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 812f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 813f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 814f54f7be5SAlison Wang dma-names = "tx", "rx"; 815f54f7be5SAlison Wang dmas = <&edma0 1 10>, 816f54f7be5SAlison Wang <&edma0 1 9>; 8179c015e13SMichael Walle fsl,sai-asynchronous; 818f54f7be5SAlison Wang status = "disabled"; 819f54f7be5SAlison Wang }; 820f54f7be5SAlison Wang 821434f9cc1SMichael Walle sai5: audio-controller@f140000 { 822434f9cc1SMichael Walle #sound-dai-cells = <0>; 823434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 824434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 825434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 826434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 827434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 828434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 829434f9cc1SMichael Walle dma-names = "tx", "rx"; 830434f9cc1SMichael Walle dmas = <&edma0 1 12>, 831434f9cc1SMichael Walle <&edma0 1 11>; 8329c015e13SMichael Walle fsl,sai-asynchronous; 833434f9cc1SMichael Walle status = "disabled"; 834434f9cc1SMichael Walle }; 835434f9cc1SMichael Walle 836434f9cc1SMichael Walle sai6: audio-controller@f150000 { 837434f9cc1SMichael Walle #sound-dai-cells = <0>; 838434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 839434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 840434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 841434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 842434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 843434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 844434f9cc1SMichael Walle dma-names = "tx", "rx"; 845434f9cc1SMichael Walle dmas = <&edma0 1 14>, 846434f9cc1SMichael Walle <&edma0 1 13>; 8479c015e13SMichael Walle fsl,sai-asynchronous; 8488897f325SBhaskar Upadhaya status = "disabled"; 8498897f325SBhaskar Upadhaya }; 8508897f325SBhaskar Upadhaya 8510b680963SFabio Estevam tmu: tmu@1f80000 { 852571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 853571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 854571cebfeSYuantian Tang interrupts = <0 23 0x4>; 855571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 856571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 857571cebfeSYuantian Tang 0x00000001 0x0000002b 858571cebfeSYuantian Tang 0x00000002 0x00000031 859571cebfeSYuantian Tang 0x00000003 0x00000038 860571cebfeSYuantian Tang 0x00000004 0x0000003f 861571cebfeSYuantian Tang 0x00000005 0x00000045 862571cebfeSYuantian Tang 0x00000006 0x0000004c 863571cebfeSYuantian Tang 0x00000007 0x00000053 864571cebfeSYuantian Tang 0x00000008 0x00000059 865571cebfeSYuantian Tang 0x00000009 0x00000060 866571cebfeSYuantian Tang 0x0000000a 0x00000066 867571cebfeSYuantian Tang 0x0000000b 0x0000006d 868571cebfeSYuantian Tang 869571cebfeSYuantian Tang 0x00010000 0x0000001c 870571cebfeSYuantian Tang 0x00010001 0x00000024 871571cebfeSYuantian Tang 0x00010002 0x0000002c 872571cebfeSYuantian Tang 0x00010003 0x00000035 873571cebfeSYuantian Tang 0x00010004 0x0000003d 874571cebfeSYuantian Tang 0x00010005 0x00000045 875571cebfeSYuantian Tang 0x00010006 0x0000004d 876961f8209SMichael Walle 0x00010007 0x00000055 877571cebfeSYuantian Tang 0x00010008 0x0000005e 878571cebfeSYuantian Tang 0x00010009 0x00000066 879571cebfeSYuantian Tang 0x0001000a 0x0000006e 880571cebfeSYuantian Tang 881571cebfeSYuantian Tang 0x00020000 0x00000018 882571cebfeSYuantian Tang 0x00020001 0x00000022 883571cebfeSYuantian Tang 0x00020002 0x0000002d 884571cebfeSYuantian Tang 0x00020003 0x00000038 885571cebfeSYuantian Tang 0x00020004 0x00000043 886571cebfeSYuantian Tang 0x00020005 0x0000004d 887571cebfeSYuantian Tang 0x00020006 0x00000058 888571cebfeSYuantian Tang 0x00020007 0x00000063 889571cebfeSYuantian Tang 0x00020008 0x0000006e 890571cebfeSYuantian Tang 891571cebfeSYuantian Tang 0x00030000 0x00000010 892571cebfeSYuantian Tang 0x00030001 0x0000001c 893571cebfeSYuantian Tang 0x00030002 0x00000029 894571cebfeSYuantian Tang 0x00030003 0x00000036 895571cebfeSYuantian Tang 0x00030004 0x00000042 896571cebfeSYuantian Tang 0x00030005 0x0000004f 897571cebfeSYuantian Tang 0x00030006 0x0000005b 898571cebfeSYuantian Tang 0x00030007 0x00000068>; 899571cebfeSYuantian Tang little-endian; 900571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 901571cebfeSYuantian Tang }; 902571cebfeSYuantian Tang 9038897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 9048897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 9058897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 9068897f325SBhaskar Upadhaya #address-cells = <3>; 9078897f325SBhaskar Upadhaya #size-cells = <2>; 9088897f325SBhaskar Upadhaya msi-parent = <&its>; 9098897f325SBhaskar Upadhaya device_type = "pci"; 9108897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 9118897f325SBhaskar Upadhaya dma-coherent; 9128897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 9138897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 9148897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 9158897f325SBhaskar Upadhaya ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 9168897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 9178897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 9188897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 9198897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 9208897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 9218897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 9228897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 9238897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 9248897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 925b1520d8bSClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 926b1520d8bSClaudiu Manoil /* BAR4 (PF5) - non-prefetchable memory */ 927b1520d8bSClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; 9288897f325SBhaskar Upadhaya 9298897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 9308897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 9318897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 9321a4bfe0fSVladimir Oltean status = "disabled"; 9338897f325SBhaskar Upadhaya }; 9341a4bfe0fSVladimir Oltean 9358897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 9368897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 9378897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 9381a4bfe0fSVladimir Oltean status = "disabled"; 9398897f325SBhaskar Upadhaya }; 9401a4bfe0fSVladimir Oltean 941b1520d8bSClaudiu Manoil enetc_port2: ethernet@0,2 { 942b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 943b1520d8bSClaudiu Manoil reg = <0x000200 0 0 0 0>; 944b1520d8bSClaudiu Manoil phy-mode = "internal"; 945b1520d8bSClaudiu Manoil status = "disabled"; 946b1520d8bSClaudiu Manoil 947b1520d8bSClaudiu Manoil fixed-link { 948b1520d8bSClaudiu Manoil speed = <1000>; 949b1520d8bSClaudiu Manoil full-duplex; 950b1520d8bSClaudiu Manoil }; 951b1520d8bSClaudiu Manoil }; 952b1520d8bSClaudiu Manoil 9538488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 9548488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 9558488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 9568488d8e9SClaudiu Manoil #address-cells = <1>; 9578488d8e9SClaudiu Manoil #size-cells = <0>; 9588488d8e9SClaudiu Manoil }; 9591a4bfe0fSVladimir Oltean 96049401003SY.b. Lu ethernet@0,4 { 96149401003SY.b. Lu compatible = "fsl,enetc-ptp"; 96249401003SY.b. Lu reg = <0x000400 0 0 0 0>; 963d0570a57SMichael Walle clocks = <&clockgen 2 3>; 96449401003SY.b. Lu little-endian; 965ab84bad5SYangbo Lu fsl,extts-fifo; 96649401003SY.b. Lu }; 967b1520d8bSClaudiu Manoil 968630952e1SMichael Walle mscc_felix: ethernet-switch@0,5 { 969b1520d8bSClaudiu Manoil reg = <0x000500 0 0 0 0>; 970b1520d8bSClaudiu Manoil /* IEP INT_B */ 971b1520d8bSClaudiu Manoil interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 972630952e1SMichael Walle status = "disabled"; 973b1520d8bSClaudiu Manoil 974b1520d8bSClaudiu Manoil ports { 975b1520d8bSClaudiu Manoil #address-cells = <1>; 976b1520d8bSClaudiu Manoil #size-cells = <0>; 977b1520d8bSClaudiu Manoil 978b1520d8bSClaudiu Manoil /* External ports */ 979b1520d8bSClaudiu Manoil mscc_felix_port0: port@0 { 980b1520d8bSClaudiu Manoil reg = <0>; 981b1520d8bSClaudiu Manoil status = "disabled"; 982b1520d8bSClaudiu Manoil }; 983b1520d8bSClaudiu Manoil 984b1520d8bSClaudiu Manoil mscc_felix_port1: port@1 { 985b1520d8bSClaudiu Manoil reg = <1>; 986b1520d8bSClaudiu Manoil status = "disabled"; 987b1520d8bSClaudiu Manoil }; 988b1520d8bSClaudiu Manoil 989b1520d8bSClaudiu Manoil mscc_felix_port2: port@2 { 990b1520d8bSClaudiu Manoil reg = <2>; 991b1520d8bSClaudiu Manoil status = "disabled"; 992b1520d8bSClaudiu Manoil }; 993b1520d8bSClaudiu Manoil 994b1520d8bSClaudiu Manoil mscc_felix_port3: port@3 { 995b1520d8bSClaudiu Manoil reg = <3>; 996b1520d8bSClaudiu Manoil status = "disabled"; 997b1520d8bSClaudiu Manoil }; 998b1520d8bSClaudiu Manoil 999b1520d8bSClaudiu Manoil /* Internal ports */ 1000b1520d8bSClaudiu Manoil mscc_felix_port4: port@4 { 1001b1520d8bSClaudiu Manoil reg = <4>; 1002b1520d8bSClaudiu Manoil phy-mode = "internal"; 1003b1520d8bSClaudiu Manoil status = "disabled"; 1004b1520d8bSClaudiu Manoil 1005b1520d8bSClaudiu Manoil fixed-link { 1006b1520d8bSClaudiu Manoil speed = <2500>; 1007b1520d8bSClaudiu Manoil full-duplex; 1008b1520d8bSClaudiu Manoil }; 1009b1520d8bSClaudiu Manoil }; 1010b1520d8bSClaudiu Manoil 1011b1520d8bSClaudiu Manoil mscc_felix_port5: port@5 { 1012b1520d8bSClaudiu Manoil reg = <5>; 1013b1520d8bSClaudiu Manoil phy-mode = "internal"; 1014b1520d8bSClaudiu Manoil status = "disabled"; 1015b1520d8bSClaudiu Manoil 1016b1520d8bSClaudiu Manoil fixed-link { 1017b1520d8bSClaudiu Manoil speed = <1000>; 1018b1520d8bSClaudiu Manoil full-duplex; 1019b1520d8bSClaudiu Manoil }; 1020b1520d8bSClaudiu Manoil }; 1021b1520d8bSClaudiu Manoil }; 1022b1520d8bSClaudiu Manoil }; 1023b1520d8bSClaudiu Manoil 1024b1520d8bSClaudiu Manoil enetc_port3: ethernet@0,6 { 1025b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 1026b1520d8bSClaudiu Manoil reg = <0x000600 0 0 0 0>; 1027b1520d8bSClaudiu Manoil phy-mode = "internal"; 1028b1520d8bSClaudiu Manoil status = "disabled"; 1029b1520d8bSClaudiu Manoil 1030b1520d8bSClaudiu Manoil fixed-link { 1031b1520d8bSClaudiu Manoil speed = <1000>; 1032b1520d8bSClaudiu Manoil full-duplex; 1033b1520d8bSClaudiu Manoil }; 10348897f325SBhaskar Upadhaya }; 10358897f325SBhaskar Upadhaya }; 1036791c88caSBiwen Li 1037791c88caSBiwen Li rcpm: power-controller@1e34040 { 1038791c88caSBiwen Li compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1039791c88caSBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 1040791c88caSBiwen Li #fsl,rcpm-wakeup-cells = <7>; 1041791c88caSBiwen Li }; 1042791c88caSBiwen Li 1043791c88caSBiwen Li ftm_alarm0: timer@2800000 { 1044791c88caSBiwen Li compatible = "fsl,ls1028a-ftm-alarm"; 1045791c88caSBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1046791c88caSBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1047791c88caSBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1048791c88caSBiwen Li }; 10498897f325SBhaskar Upadhaya }; 10507f538f19SWen He 10517f538f19SWen He malidp0: display@f080000 { 10527f538f19SWen He compatible = "arm,mali-dp500"; 10537f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 10547f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 10557f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 10567f538f19SWen He interrupt-names = "DE", "SE"; 105791035cb0SWen He clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 105813782597SWen He <&clockgen 2 2>; 10597f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 10607f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 10613a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 10627f538f19SWen He 10637f538f19SWen He port { 10647f538f19SWen He dp0_out: endpoint { 10657f538f19SWen He 10667f538f19SWen He }; 10677f538f19SWen He }; 10687f538f19SWen He }; 10698897f325SBhaskar Upadhaya}; 1070