18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 5f7d48ffcSWasim Khan * Copyright 2018-2020 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 20791c88caSBiwen Li aliases { 21791c88caSBiwen Li rtc1 = &ftm_alarm0; 22791c88caSBiwen Li }; 23791c88caSBiwen Li 248897f325SBhaskar Upadhaya cpus { 258897f325SBhaskar Upadhaya #address-cells = <1>; 268897f325SBhaskar Upadhaya #size-cells = <0>; 278897f325SBhaskar Upadhaya 288897f325SBhaskar Upadhaya cpu0: cpu@0 { 298897f325SBhaskar Upadhaya device_type = "cpu"; 308897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 318897f325SBhaskar Upadhaya reg = <0x0>; 328897f325SBhaskar Upadhaya enable-method = "psci"; 338897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 348897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3553f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 36571cebfeSYuantian Tang #cooling-cells = <2>; 378897f325SBhaskar Upadhaya }; 388897f325SBhaskar Upadhaya 398897f325SBhaskar Upadhaya cpu1: cpu@1 { 408897f325SBhaskar Upadhaya device_type = "cpu"; 418897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 428897f325SBhaskar Upadhaya reg = <0x1>; 438897f325SBhaskar Upadhaya enable-method = "psci"; 448897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 458897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4653f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 47571cebfeSYuantian Tang #cooling-cells = <2>; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya 508897f325SBhaskar Upadhaya l2: l2-cache { 518897f325SBhaskar Upadhaya compatible = "cache"; 528897f325SBhaskar Upadhaya }; 538897f325SBhaskar Upadhaya }; 548897f325SBhaskar Upadhaya 558897f325SBhaskar Upadhaya idle-states { 568897f325SBhaskar Upadhaya /* 578897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 588897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 598897f325SBhaskar Upadhaya */ 609b631649SLinus Walleij entry-method = "psci"; 618897f325SBhaskar Upadhaya 6253f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 638897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6453f2ac9dSRan Wang idle-state-name = "PW20"; 6553f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6653f2ac9dSRan Wang entry-latency-us = <2000>; 6753f2ac9dSRan Wang exit-latency-us = <2000>; 6853f2ac9dSRan Wang min-residency-us = <6000>; 698897f325SBhaskar Upadhaya }; 708897f325SBhaskar Upadhaya }; 718897f325SBhaskar Upadhaya 728897f325SBhaskar Upadhaya sysclk: clock-sysclk { 738897f325SBhaskar Upadhaya compatible = "fixed-clock"; 748897f325SBhaskar Upadhaya #clock-cells = <0>; 758897f325SBhaskar Upadhaya clock-frequency = <100000000>; 768897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 778897f325SBhaskar Upadhaya }; 788897f325SBhaskar Upadhaya 7981f36887SWen He osc_27m: clock-osc-27m { 807f538f19SWen He compatible = "fixed-clock"; 817f538f19SWen He #clock-cells = <0>; 827f538f19SWen He clock-frequency = <27000000>; 8381f36887SWen He clock-output-names = "phy_27m"; 8481f36887SWen He }; 8581f36887SWen He 8681f36887SWen He dpclk: clock-controller@f1f0000 { 8781f36887SWen He compatible = "fsl,ls1028a-plldig"; 8881f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8991035cb0SWen He #clock-cells = <0>; 9081f36887SWen He clocks = <&osc_27m>; 917f538f19SWen He }; 927f538f19SWen He 938897f325SBhaskar Upadhaya reboot { 948897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 953f0fb37bSMichael Walle regmap = <&rst>; 968897f325SBhaskar Upadhaya offset = <0xb0>; 978897f325SBhaskar Upadhaya mask = <0x02>; 988897f325SBhaskar Upadhaya }; 998897f325SBhaskar Upadhaya 1008897f325SBhaskar Upadhaya timer { 1018897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 1028897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 1038897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1048897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1058897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1068897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1078897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1088897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1098897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1108897f325SBhaskar Upadhaya }; 1118897f325SBhaskar Upadhaya 112b9eb314aSAlison Wang pmu { 113b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 114b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 115b9eb314aSAlison Wang }; 116b9eb314aSAlison Wang 1178897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1188897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1198897f325SBhaskar Upadhaya #address-cells = <2>; 1208897f325SBhaskar Upadhaya #size-cells = <2>; 1218897f325SBhaskar Upadhaya ranges; 1228897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1238897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1248897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1258897f325SBhaskar Upadhaya interrupt-controller; 1268897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1278897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1288897f325SBhaskar Upadhaya its: gic-its@6020000 { 1298897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1308897f325SBhaskar Upadhaya msi-controller; 1318897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1328897f325SBhaskar Upadhaya }; 1338897f325SBhaskar Upadhaya }; 1348897f325SBhaskar Upadhaya 13568e36a42SFabio Estevam thermal-zones { 1363269c178SYuantian Tang ddr-controller { 13768e36a42SFabio Estevam polling-delay-passive = <1000>; 13868e36a42SFabio Estevam polling-delay = <5000>; 13968e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 14068e36a42SFabio Estevam 14168e36a42SFabio Estevam trips { 1423269c178SYuantian Tang ddr-ctrler-alert { 1433269c178SYuantian Tang temperature = <85000>; 1443269c178SYuantian Tang hysteresis = <2000>; 1453269c178SYuantian Tang type = "passive"; 1463269c178SYuantian Tang }; 1473269c178SYuantian Tang 1483269c178SYuantian Tang ddr-ctrler-crit { 1493269c178SYuantian Tang temperature = <95000>; 1503269c178SYuantian Tang hysteresis = <2000>; 1513269c178SYuantian Tang type = "critical"; 1523269c178SYuantian Tang }; 1533269c178SYuantian Tang }; 1543269c178SYuantian Tang }; 1553269c178SYuantian Tang 1563269c178SYuantian Tang core-cluster { 1573269c178SYuantian Tang polling-delay-passive = <1000>; 1583269c178SYuantian Tang polling-delay = <5000>; 1593269c178SYuantian Tang thermal-sensors = <&tmu 1>; 1603269c178SYuantian Tang 1613269c178SYuantian Tang trips { 16268e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 16368e36a42SFabio Estevam temperature = <85000>; 16468e36a42SFabio Estevam hysteresis = <2000>; 16568e36a42SFabio Estevam type = "passive"; 16668e36a42SFabio Estevam }; 16768e36a42SFabio Estevam 16868e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 16968e36a42SFabio Estevam temperature = <95000>; 17068e36a42SFabio Estevam hysteresis = <2000>; 17168e36a42SFabio Estevam type = "critical"; 17268e36a42SFabio Estevam }; 17368e36a42SFabio Estevam }; 17468e36a42SFabio Estevam 17568e36a42SFabio Estevam cooling-maps { 17668e36a42SFabio Estevam map0 { 17768e36a42SFabio Estevam trip = <&core_cluster_alert>; 17868e36a42SFabio Estevam cooling-device = 17968e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 18068e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 18168e36a42SFabio Estevam }; 18268e36a42SFabio Estevam }; 18368e36a42SFabio Estevam }; 18468e36a42SFabio Estevam }; 18568e36a42SFabio Estevam 1868897f325SBhaskar Upadhaya soc: soc { 1878897f325SBhaskar Upadhaya compatible = "simple-bus"; 1888897f325SBhaskar Upadhaya #address-cells = <2>; 1898897f325SBhaskar Upadhaya #size-cells = <2>; 1908897f325SBhaskar Upadhaya ranges; 1918897f325SBhaskar Upadhaya 1928897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1938897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1948897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1958897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1968897f325SBhaskar Upadhaya big-endian; 1978897f325SBhaskar Upadhaya }; 1988897f325SBhaskar Upadhaya 1998897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 2008897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 2018897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 20233eae7fbSYinbo Zhu little-endian; 2038897f325SBhaskar Upadhaya }; 2048897f325SBhaskar Upadhaya 2053f0fb37bSMichael Walle rst: syscon@1e60000 { 2063f0fb37bSMichael Walle compatible = "syscon"; 2073f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 2083f0fb37bSMichael Walle little-endian; 2093f0fb37bSMichael Walle }; 2103f0fb37bSMichael Walle 2118897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 2128897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 2138897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 2148897f325SBhaskar Upadhaya big-endian; 2158897f325SBhaskar Upadhaya }; 2168897f325SBhaskar Upadhaya 2178897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 2188897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 2198897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 2208897f325SBhaskar Upadhaya #clock-cells = <2>; 2218897f325SBhaskar Upadhaya clocks = <&sysclk>; 2228897f325SBhaskar Upadhaya }; 2238897f325SBhaskar Upadhaya 2248897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2258897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2268897f325SBhaskar Upadhaya #address-cells = <1>; 2278897f325SBhaskar Upadhaya #size-cells = <0>; 2288897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2298897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 230ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2318897f325SBhaskar Upadhaya status = "disabled"; 2328897f325SBhaskar Upadhaya }; 2338897f325SBhaskar Upadhaya 2348897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2358897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2368897f325SBhaskar Upadhaya #address-cells = <1>; 2378897f325SBhaskar Upadhaya #size-cells = <0>; 2388897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2398897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 240ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2418897f325SBhaskar Upadhaya status = "disabled"; 2428897f325SBhaskar Upadhaya }; 2438897f325SBhaskar Upadhaya 2448897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2458897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2468897f325SBhaskar Upadhaya #address-cells = <1>; 2478897f325SBhaskar Upadhaya #size-cells = <0>; 2488897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2498897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 250ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2518897f325SBhaskar Upadhaya status = "disabled"; 2528897f325SBhaskar Upadhaya }; 2538897f325SBhaskar Upadhaya 2548897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2558897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2568897f325SBhaskar Upadhaya #address-cells = <1>; 2578897f325SBhaskar Upadhaya #size-cells = <0>; 2588897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2598897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 260ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2618897f325SBhaskar Upadhaya status = "disabled"; 2628897f325SBhaskar Upadhaya }; 2638897f325SBhaskar Upadhaya 2648897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2658897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2668897f325SBhaskar Upadhaya #address-cells = <1>; 2678897f325SBhaskar Upadhaya #size-cells = <0>; 2688897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2698897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 270ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2718897f325SBhaskar Upadhaya status = "disabled"; 2728897f325SBhaskar Upadhaya }; 2738897f325SBhaskar Upadhaya 2748897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2758897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2768897f325SBhaskar Upadhaya #address-cells = <1>; 2778897f325SBhaskar Upadhaya #size-cells = <0>; 2788897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2798897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 280ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2818897f325SBhaskar Upadhaya status = "disabled"; 2828897f325SBhaskar Upadhaya }; 2838897f325SBhaskar Upadhaya 2848897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2858897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2868897f325SBhaskar Upadhaya #address-cells = <1>; 2878897f325SBhaskar Upadhaya #size-cells = <0>; 2888897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2898897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 290ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2918897f325SBhaskar Upadhaya status = "disabled"; 2928897f325SBhaskar Upadhaya }; 2938897f325SBhaskar Upadhaya 2948897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2958897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2968897f325SBhaskar Upadhaya #address-cells = <1>; 2978897f325SBhaskar Upadhaya #size-cells = <0>; 2988897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2998897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 300ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 3018897f325SBhaskar Upadhaya status = "disabled"; 3028897f325SBhaskar Upadhaya }; 3038897f325SBhaskar Upadhaya 304c77fae5bSAshish Kumar fspi: spi@20c0000 { 305c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 306c77fae5bSAshish Kumar #address-cells = <1>; 307c77fae5bSAshish Kumar #size-cells = <0>; 308c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 309c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 310c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 311c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 312c77fae5bSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 313c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 314c77fae5bSAshish Kumar status = "disabled"; 315c77fae5bSAshish Kumar }; 316c77fae5bSAshish Kumar 317c2d35adaSMichael Walle dspi0: spi@2100000 { 318c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 319c2d35adaSMichael Walle #address-cells = <1>; 320c2d35adaSMichael Walle #size-cells = <0>; 321c2d35adaSMichael Walle reg = <0x0 0x2100000 0x0 0x10000>; 322c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 323c2d35adaSMichael Walle clock-names = "dspi"; 324c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 325dd12fa69SVladimir Oltean dmas = <&edma0 0 62>, <&edma0 0 60>; 326dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 327c2d35adaSMichael Walle spi-num-chipselects = <4>; 328c2d35adaSMichael Walle little-endian; 329c2d35adaSMichael Walle status = "disabled"; 330c2d35adaSMichael Walle }; 331c2d35adaSMichael Walle 332c2d35adaSMichael Walle dspi1: spi@2110000 { 333c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 334c2d35adaSMichael Walle #address-cells = <1>; 335c2d35adaSMichael Walle #size-cells = <0>; 336c2d35adaSMichael Walle reg = <0x0 0x2110000 0x0 0x10000>; 337c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 338c2d35adaSMichael Walle clock-names = "dspi"; 339c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 340dd12fa69SVladimir Oltean dmas = <&edma0 0 58>, <&edma0 0 56>; 341dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 342c2d35adaSMichael Walle spi-num-chipselects = <4>; 343c2d35adaSMichael Walle little-endian; 344c2d35adaSMichael Walle status = "disabled"; 345c2d35adaSMichael Walle }; 346c2d35adaSMichael Walle 347c2d35adaSMichael Walle dspi2: spi@2120000 { 348c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 349c2d35adaSMichael Walle #address-cells = <1>; 350c2d35adaSMichael Walle #size-cells = <0>; 351c2d35adaSMichael Walle reg = <0x0 0x2120000 0x0 0x10000>; 352c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353c2d35adaSMichael Walle clock-names = "dspi"; 354c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 355dd12fa69SVladimir Oltean dmas = <&edma0 0 54>, <&edma0 0 2>; 356dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 357c2d35adaSMichael Walle spi-num-chipselects = <3>; 358c2d35adaSMichael Walle little-endian; 359c2d35adaSMichael Walle status = "disabled"; 360c2d35adaSMichael Walle }; 361c2d35adaSMichael Walle 362491d3a3fSAshish Kumar esdhc: mmc@2140000 { 363491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 364491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 365491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 366491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 367491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 368491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 369491d3a3fSAshish Kumar sdhci,auto-cmd12; 370491d3a3fSAshish Kumar little-endian; 371491d3a3fSAshish Kumar bus-width = <4>; 372491d3a3fSAshish Kumar status = "disabled"; 373491d3a3fSAshish Kumar }; 374491d3a3fSAshish Kumar 375491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 376491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 377491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 378491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 379491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 380491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 381491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 382491d3a3fSAshish Kumar sdhci,auto-cmd12; 383491d3a3fSAshish Kumar broken-cd; 384491d3a3fSAshish Kumar little-endian; 385491d3a3fSAshish Kumar bus-width = <4>; 386491d3a3fSAshish Kumar status = "disabled"; 387491d3a3fSAshish Kumar }; 388491d3a3fSAshish Kumar 3898897f325SBhaskar Upadhaya duart0: serial@21c0500 { 3908897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3918897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 3928897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3938897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3948897f325SBhaskar Upadhaya status = "disabled"; 3958897f325SBhaskar Upadhaya }; 3968897f325SBhaskar Upadhaya 3978897f325SBhaskar Upadhaya duart1: serial@21c0600 { 3988897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3998897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 4008897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4018897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 4028897f325SBhaskar Upadhaya status = "disabled"; 4038897f325SBhaskar Upadhaya }; 4048897f325SBhaskar Upadhaya 4052607d724SMichael Walle 4062607d724SMichael Walle lpuart0: serial@2260000 { 4072607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4082607d724SMichael Walle reg = <0x0 0x2260000 0x0 0x1000>; 4092607d724SMichael Walle interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 4102607d724SMichael Walle clocks = <&clockgen 4 1>; 4112607d724SMichael Walle clock-names = "ipg"; 4122607d724SMichael Walle dma-names = "rx","tx"; 4132607d724SMichael Walle dmas = <&edma0 1 32>, 4142607d724SMichael Walle <&edma0 1 33>; 4152607d724SMichael Walle status = "disabled"; 4162607d724SMichael Walle }; 4172607d724SMichael Walle 4182607d724SMichael Walle lpuart1: serial@2270000 { 4192607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4202607d724SMichael Walle reg = <0x0 0x2270000 0x0 0x1000>; 4212607d724SMichael Walle interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 4222607d724SMichael Walle clocks = <&clockgen 4 1>; 4232607d724SMichael Walle clock-names = "ipg"; 4242607d724SMichael Walle dma-names = "rx","tx"; 4252607d724SMichael Walle dmas = <&edma0 1 30>, 4262607d724SMichael Walle <&edma0 1 31>; 4272607d724SMichael Walle status = "disabled"; 4282607d724SMichael Walle }; 4292607d724SMichael Walle 4302607d724SMichael Walle lpuart2: serial@2280000 { 4312607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4322607d724SMichael Walle reg = <0x0 0x2280000 0x0 0x1000>; 4332607d724SMichael Walle interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 4342607d724SMichael Walle clocks = <&clockgen 4 1>; 4352607d724SMichael Walle clock-names = "ipg"; 4362607d724SMichael Walle dma-names = "rx","tx"; 4372607d724SMichael Walle dmas = <&edma0 1 28>, 4382607d724SMichael Walle <&edma0 1 29>; 4392607d724SMichael Walle status = "disabled"; 4402607d724SMichael Walle }; 4412607d724SMichael Walle 4422607d724SMichael Walle lpuart3: serial@2290000 { 4432607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4442607d724SMichael Walle reg = <0x0 0x2290000 0x0 0x1000>; 4452607d724SMichael Walle interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 4462607d724SMichael Walle clocks = <&clockgen 4 1>; 4472607d724SMichael Walle clock-names = "ipg"; 4482607d724SMichael Walle dma-names = "rx","tx"; 4492607d724SMichael Walle dmas = <&edma0 1 26>, 4502607d724SMichael Walle <&edma0 1 27>; 4512607d724SMichael Walle status = "disabled"; 4522607d724SMichael Walle }; 4532607d724SMichael Walle 4542607d724SMichael Walle lpuart4: serial@22a0000 { 4552607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4562607d724SMichael Walle reg = <0x0 0x22a0000 0x0 0x1000>; 4572607d724SMichael Walle interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 4582607d724SMichael Walle clocks = <&clockgen 4 1>; 4592607d724SMichael Walle clock-names = "ipg"; 4602607d724SMichael Walle dma-names = "rx","tx"; 4612607d724SMichael Walle dmas = <&edma0 1 24>, 4622607d724SMichael Walle <&edma0 1 25>; 4632607d724SMichael Walle status = "disabled"; 4642607d724SMichael Walle }; 4652607d724SMichael Walle 4662607d724SMichael Walle lpuart5: serial@22b0000 { 4672607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4682607d724SMichael Walle reg = <0x0 0x22b0000 0x0 0x1000>; 4692607d724SMichael Walle interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 4702607d724SMichael Walle clocks = <&clockgen 4 1>; 4712607d724SMichael Walle clock-names = "ipg"; 4722607d724SMichael Walle dma-names = "rx","tx"; 4732607d724SMichael Walle dmas = <&edma0 1 22>, 4742607d724SMichael Walle <&edma0 1 23>; 4752607d724SMichael Walle status = "disabled"; 4762607d724SMichael Walle }; 4772607d724SMichael Walle 478f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 479f54f7be5SAlison Wang #dma-cells = <2>; 480e0d7856eSMichael Walle compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 481f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 482f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 483f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 484f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 485f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 486f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 487f54f7be5SAlison Wang dma-channels = <32>; 488f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 489f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 490f54f7be5SAlison Wang <&clockgen 4 1>; 491f54f7be5SAlison Wang }; 492f54f7be5SAlison Wang 4938897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 494f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4958897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 4968897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 4978897f325SBhaskar Upadhaya gpio-controller; 4988897f325SBhaskar Upadhaya #gpio-cells = <2>; 4998897f325SBhaskar Upadhaya interrupt-controller; 5008897f325SBhaskar Upadhaya #interrupt-cells = <2>; 501f64697bdSSong Hui little-endian; 5028897f325SBhaskar Upadhaya }; 5038897f325SBhaskar Upadhaya 5048897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 505f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5068897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 5078897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5088897f325SBhaskar Upadhaya gpio-controller; 5098897f325SBhaskar Upadhaya #gpio-cells = <2>; 5108897f325SBhaskar Upadhaya interrupt-controller; 5118897f325SBhaskar Upadhaya #interrupt-cells = <2>; 512f64697bdSSong Hui little-endian; 5138897f325SBhaskar Upadhaya }; 5148897f325SBhaskar Upadhaya 5158897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 516f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5178897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 5188897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 5198897f325SBhaskar Upadhaya gpio-controller; 5208897f325SBhaskar Upadhaya #gpio-cells = <2>; 5218897f325SBhaskar Upadhaya interrupt-controller; 5228897f325SBhaskar Upadhaya #interrupt-cells = <2>; 523f64697bdSSong Hui little-endian; 5248897f325SBhaskar Upadhaya }; 5258897f325SBhaskar Upadhaya 526c92f56faSRan Wang usb0: usb@3100000 { 527c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 528c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 529c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 530c92f56faSRan Wang dr_mode = "host"; 531c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 532c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 533c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 534c92f56faSRan Wang }; 535c92f56faSRan Wang 536c92f56faSRan Wang usb1: usb@3110000 { 537c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 538c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 539c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 540c92f56faSRan Wang dr_mode = "host"; 541c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 542c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 543c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 5448897f325SBhaskar Upadhaya }; 5458897f325SBhaskar Upadhaya 5468897f325SBhaskar Upadhaya sata: sata@3200000 { 5478897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 5488897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 5493f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 5508897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 5518897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 5528897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 5538897f325SBhaskar Upadhaya status = "disabled"; 5548897f325SBhaskar Upadhaya }; 5558897f325SBhaskar Upadhaya 556f7d48ffcSWasim Khan pcie1: pcie@3400000 { 557f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 558f6ff3f6dSXiaowei Bao reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 559f6ff3f6dSXiaowei Bao 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 560f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 561f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 562f6ff3f6dSXiaowei Bao <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 563f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 564f6ff3f6dSXiaowei Bao #address-cells = <3>; 565f6ff3f6dSXiaowei Bao #size-cells = <2>; 566f6ff3f6dSXiaowei Bao device_type = "pci"; 567f6ff3f6dSXiaowei Bao dma-coherent; 568f6ff3f6dSXiaowei Bao num-viewport = <8>; 569f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 570f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 571f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 572f6ff3f6dSXiaowei Bao msi-parent = <&its>; 573f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 574f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 575f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 576f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 577f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 578f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 579f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 580f6ff3f6dSXiaowei Bao status = "disabled"; 581f6ff3f6dSXiaowei Bao }; 582f6ff3f6dSXiaowei Bao 583f7d48ffcSWasim Khan pcie2: pcie@3500000 { 584f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 585f6ff3f6dSXiaowei Bao reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 586f6ff3f6dSXiaowei Bao 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 587f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 588f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 589f6ff3f6dSXiaowei Bao <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 590f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 591f6ff3f6dSXiaowei Bao #address-cells = <3>; 592f6ff3f6dSXiaowei Bao #size-cells = <2>; 593f6ff3f6dSXiaowei Bao device_type = "pci"; 594f6ff3f6dSXiaowei Bao dma-coherent; 595f6ff3f6dSXiaowei Bao num-viewport = <8>; 596f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 597f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 598f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 599f6ff3f6dSXiaowei Bao msi-parent = <&its>; 600f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 601f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 602f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 603f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 604f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 605f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 606f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 607f6ff3f6dSXiaowei Bao status = "disabled"; 608f6ff3f6dSXiaowei Bao }; 609f6ff3f6dSXiaowei Bao 6108897f325SBhaskar Upadhaya smmu: iommu@5000000 { 6118897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 6128897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 6138897f325SBhaskar Upadhaya #global-interrupts = <8>; 6148897f325SBhaskar Upadhaya #iommu-cells = <1>; 6158897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 6168897f325SBhaskar Upadhaya /* global secure fault */ 6178897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 6188897f325SBhaskar Upadhaya /* combined secure interrupt */ 6198897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 6208897f325SBhaskar Upadhaya /* global non-secure fault */ 6218897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 6228897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 6238897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 6248897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 6258897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 6268897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 6278897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 6288897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6298897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6308897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 6318897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 6328897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 6338897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 6348897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 6358897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 6368897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 6378897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 6388897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 6398897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 6408897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 6418897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 6428897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 6438897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 6448897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 6458897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6468897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6478897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6488897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6498897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6508897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6518897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 6528897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 6538897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 6548897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 6558897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 6568897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 6578897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 6588897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 6598897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 6608897f325SBhaskar Upadhaya }; 661927d7f85SClaudiu Manoil 6621d0becabSHoria Geantă crypto: crypto@8000000 { 6631d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 6641d0becabSHoria Geantă fsl,sec-era = <10>; 6651d0becabSHoria Geantă #address-cells = <1>; 6661d0becabSHoria Geantă #size-cells = <1>; 6671d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 6681d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 6691d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 6701d0becabSHoria Geantă dma-coherent; 6711d0becabSHoria Geantă 6721d0becabSHoria Geantă sec_jr0: jr@10000 { 6731d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6741d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6751d0becabSHoria Geantă reg = <0x10000 0x10000>; 6761d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 6771d0becabSHoria Geantă }; 6781d0becabSHoria Geantă 6791d0becabSHoria Geantă sec_jr1: jr@20000 { 6801d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6811d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6821d0becabSHoria Geantă reg = <0x20000 0x10000>; 6831d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 6841d0becabSHoria Geantă }; 6851d0becabSHoria Geantă 6861d0becabSHoria Geantă sec_jr2: jr@30000 { 6871d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6881d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6891d0becabSHoria Geantă reg = <0x30000 0x10000>; 6901d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 6911d0becabSHoria Geantă }; 6921d0becabSHoria Geantă 6931d0becabSHoria Geantă sec_jr3: jr@40000 { 6941d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6951d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6961d0becabSHoria Geantă reg = <0x40000 0x10000>; 6971d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 6981d0becabSHoria Geantă }; 6991d0becabSHoria Geantă }; 7001d0becabSHoria Geantă 7017802f88dSPeng Ma qdma: dma-controller@8380000 { 7027802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 7037802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 7047802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 7057802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 7067802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 7077802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 7087802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 7097802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 7107802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 7117802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 7127802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 7137802f88dSPeng Ma dma-channels = <8>; 7147802f88dSPeng Ma block-number = <1>; 7157802f88dSPeng Ma block-offset = <0x10000>; 7167802f88dSPeng Ma fsl,dma-queues = <2>; 7177802f88dSPeng Ma status-sizes = <64>; 7187802f88dSPeng Ma queue-sizes = <64 64>; 7197802f88dSPeng Ma }; 7207802f88dSPeng Ma 72157aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 72257aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 72357aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 72457aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 725f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 72657aa1bc7SChuanhua Han }; 72757aa1bc7SChuanhua Han 72857aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 72957aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 73057aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 73157aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 732f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 73357aa1bc7SChuanhua Han }; 73457aa1bc7SChuanhua Han 735f54f7be5SAlison Wang sai1: audio-controller@f100000 { 736f54f7be5SAlison Wang #sound-dai-cells = <0>; 737f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 738f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 739f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 740f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 741f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 742f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 743f54f7be5SAlison Wang dma-names = "tx", "rx"; 744f54f7be5SAlison Wang dmas = <&edma0 1 4>, 745f54f7be5SAlison Wang <&edma0 1 3>; 7469c015e13SMichael Walle fsl,sai-asynchronous; 747f54f7be5SAlison Wang status = "disabled"; 748f54f7be5SAlison Wang }; 749f54f7be5SAlison Wang 750f54f7be5SAlison Wang sai2: audio-controller@f110000 { 751f54f7be5SAlison Wang #sound-dai-cells = <0>; 752f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 753f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 754f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 755f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 756f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 757f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 758f54f7be5SAlison Wang dma-names = "tx", "rx"; 759f54f7be5SAlison Wang dmas = <&edma0 1 6>, 760f54f7be5SAlison Wang <&edma0 1 5>; 7619c015e13SMichael Walle fsl,sai-asynchronous; 762f54f7be5SAlison Wang status = "disabled"; 763f54f7be5SAlison Wang }; 764f54f7be5SAlison Wang 765434f9cc1SMichael Walle sai3: audio-controller@f120000 { 766434f9cc1SMichael Walle #sound-dai-cells = <0>; 767434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 768434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 769434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 770434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 771434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 772434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 773434f9cc1SMichael Walle dma-names = "tx", "rx"; 774434f9cc1SMichael Walle dmas = <&edma0 1 8>, 775434f9cc1SMichael Walle <&edma0 1 7>; 7769c015e13SMichael Walle fsl,sai-asynchronous; 777f54f7be5SAlison Wang status = "disabled"; 778f54f7be5SAlison Wang }; 779f54f7be5SAlison Wang 780f54f7be5SAlison Wang sai4: audio-controller@f130000 { 781f54f7be5SAlison Wang #sound-dai-cells = <0>; 782f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 783f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 784f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 785f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 786f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 787f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 788f54f7be5SAlison Wang dma-names = "tx", "rx"; 789f54f7be5SAlison Wang dmas = <&edma0 1 10>, 790f54f7be5SAlison Wang <&edma0 1 9>; 7919c015e13SMichael Walle fsl,sai-asynchronous; 792f54f7be5SAlison Wang status = "disabled"; 793f54f7be5SAlison Wang }; 794f54f7be5SAlison Wang 795434f9cc1SMichael Walle sai5: audio-controller@f140000 { 796434f9cc1SMichael Walle #sound-dai-cells = <0>; 797434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 798434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 799434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 800434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 801434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 802434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 803434f9cc1SMichael Walle dma-names = "tx", "rx"; 804434f9cc1SMichael Walle dmas = <&edma0 1 12>, 805434f9cc1SMichael Walle <&edma0 1 11>; 8069c015e13SMichael Walle fsl,sai-asynchronous; 807434f9cc1SMichael Walle status = "disabled"; 808434f9cc1SMichael Walle }; 809434f9cc1SMichael Walle 810434f9cc1SMichael Walle sai6: audio-controller@f150000 { 811434f9cc1SMichael Walle #sound-dai-cells = <0>; 812434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 813434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 814434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 815434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 816434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 817434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 818434f9cc1SMichael Walle dma-names = "tx", "rx"; 819434f9cc1SMichael Walle dmas = <&edma0 1 14>, 820434f9cc1SMichael Walle <&edma0 1 13>; 8219c015e13SMichael Walle fsl,sai-asynchronous; 8228897f325SBhaskar Upadhaya status = "disabled"; 8238897f325SBhaskar Upadhaya }; 8248897f325SBhaskar Upadhaya 8250b680963SFabio Estevam tmu: tmu@1f80000 { 826571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 827571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 828571cebfeSYuantian Tang interrupts = <0 23 0x4>; 829571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 830571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 831571cebfeSYuantian Tang 0x00000001 0x0000002b 832571cebfeSYuantian Tang 0x00000002 0x00000031 833571cebfeSYuantian Tang 0x00000003 0x00000038 834571cebfeSYuantian Tang 0x00000004 0x0000003f 835571cebfeSYuantian Tang 0x00000005 0x00000045 836571cebfeSYuantian Tang 0x00000006 0x0000004c 837571cebfeSYuantian Tang 0x00000007 0x00000053 838571cebfeSYuantian Tang 0x00000008 0x00000059 839571cebfeSYuantian Tang 0x00000009 0x00000060 840571cebfeSYuantian Tang 0x0000000a 0x00000066 841571cebfeSYuantian Tang 0x0000000b 0x0000006d 842571cebfeSYuantian Tang 843571cebfeSYuantian Tang 0x00010000 0x0000001c 844571cebfeSYuantian Tang 0x00010001 0x00000024 845571cebfeSYuantian Tang 0x00010002 0x0000002c 846571cebfeSYuantian Tang 0x00010003 0x00000035 847571cebfeSYuantian Tang 0x00010004 0x0000003d 848571cebfeSYuantian Tang 0x00010005 0x00000045 849571cebfeSYuantian Tang 0x00010006 0x0000004d 850961f8209SMichael Walle 0x00010007 0x00000055 851571cebfeSYuantian Tang 0x00010008 0x0000005e 852571cebfeSYuantian Tang 0x00010009 0x00000066 853571cebfeSYuantian Tang 0x0001000a 0x0000006e 854571cebfeSYuantian Tang 855571cebfeSYuantian Tang 0x00020000 0x00000018 856571cebfeSYuantian Tang 0x00020001 0x00000022 857571cebfeSYuantian Tang 0x00020002 0x0000002d 858571cebfeSYuantian Tang 0x00020003 0x00000038 859571cebfeSYuantian Tang 0x00020004 0x00000043 860571cebfeSYuantian Tang 0x00020005 0x0000004d 861571cebfeSYuantian Tang 0x00020006 0x00000058 862571cebfeSYuantian Tang 0x00020007 0x00000063 863571cebfeSYuantian Tang 0x00020008 0x0000006e 864571cebfeSYuantian Tang 865571cebfeSYuantian Tang 0x00030000 0x00000010 866571cebfeSYuantian Tang 0x00030001 0x0000001c 867571cebfeSYuantian Tang 0x00030002 0x00000029 868571cebfeSYuantian Tang 0x00030003 0x00000036 869571cebfeSYuantian Tang 0x00030004 0x00000042 870571cebfeSYuantian Tang 0x00030005 0x0000004f 871571cebfeSYuantian Tang 0x00030006 0x0000005b 872571cebfeSYuantian Tang 0x00030007 0x00000068>; 873571cebfeSYuantian Tang little-endian; 874571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 875571cebfeSYuantian Tang }; 876571cebfeSYuantian Tang 8778897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 8788897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 8798897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 8808897f325SBhaskar Upadhaya #address-cells = <3>; 8818897f325SBhaskar Upadhaya #size-cells = <2>; 8828897f325SBhaskar Upadhaya msi-parent = <&its>; 8838897f325SBhaskar Upadhaya device_type = "pci"; 8848897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 8858897f325SBhaskar Upadhaya dma-coherent; 8868897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 8878897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 8888897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 8898897f325SBhaskar Upadhaya ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 8908897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 8918897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 8928897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 8938897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 8948897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 8958897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 8968897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 8978897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 8988897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 899b1520d8bSClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 900b1520d8bSClaudiu Manoil /* BAR4 (PF5) - non-prefetchable memory */ 901b1520d8bSClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; 9028897f325SBhaskar Upadhaya 9038897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 9048897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 9058897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 9061a4bfe0fSVladimir Oltean status = "disabled"; 9078897f325SBhaskar Upadhaya }; 9081a4bfe0fSVladimir Oltean 9098897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 9108897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 9118897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 9121a4bfe0fSVladimir Oltean status = "disabled"; 9138897f325SBhaskar Upadhaya }; 9141a4bfe0fSVladimir Oltean 915b1520d8bSClaudiu Manoil enetc_port2: ethernet@0,2 { 916b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 917b1520d8bSClaudiu Manoil reg = <0x000200 0 0 0 0>; 918b1520d8bSClaudiu Manoil phy-mode = "internal"; 919b1520d8bSClaudiu Manoil status = "disabled"; 920b1520d8bSClaudiu Manoil 921b1520d8bSClaudiu Manoil fixed-link { 922b1520d8bSClaudiu Manoil speed = <1000>; 923b1520d8bSClaudiu Manoil full-duplex; 924b1520d8bSClaudiu Manoil }; 925b1520d8bSClaudiu Manoil }; 926b1520d8bSClaudiu Manoil 9278488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 9288488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 9298488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 9308488d8e9SClaudiu Manoil #address-cells = <1>; 9318488d8e9SClaudiu Manoil #size-cells = <0>; 9328488d8e9SClaudiu Manoil }; 9331a4bfe0fSVladimir Oltean 93449401003SY.b. Lu ethernet@0,4 { 93549401003SY.b. Lu compatible = "fsl,enetc-ptp"; 93649401003SY.b. Lu reg = <0x000400 0 0 0 0>; 93749401003SY.b. Lu clocks = <&clockgen 4 0>; 93849401003SY.b. Lu little-endian; 939ab84bad5SYangbo Lu fsl,extts-fifo; 94049401003SY.b. Lu }; 941b1520d8bSClaudiu Manoil 942630952e1SMichael Walle mscc_felix: ethernet-switch@0,5 { 943b1520d8bSClaudiu Manoil reg = <0x000500 0 0 0 0>; 944b1520d8bSClaudiu Manoil /* IEP INT_B */ 945b1520d8bSClaudiu Manoil interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 946630952e1SMichael Walle status = "disabled"; 947b1520d8bSClaudiu Manoil 948b1520d8bSClaudiu Manoil ports { 949b1520d8bSClaudiu Manoil #address-cells = <1>; 950b1520d8bSClaudiu Manoil #size-cells = <0>; 951b1520d8bSClaudiu Manoil 952b1520d8bSClaudiu Manoil /* External ports */ 953b1520d8bSClaudiu Manoil mscc_felix_port0: port@0 { 954b1520d8bSClaudiu Manoil reg = <0>; 955b1520d8bSClaudiu Manoil status = "disabled"; 956b1520d8bSClaudiu Manoil }; 957b1520d8bSClaudiu Manoil 958b1520d8bSClaudiu Manoil mscc_felix_port1: port@1 { 959b1520d8bSClaudiu Manoil reg = <1>; 960b1520d8bSClaudiu Manoil status = "disabled"; 961b1520d8bSClaudiu Manoil }; 962b1520d8bSClaudiu Manoil 963b1520d8bSClaudiu Manoil mscc_felix_port2: port@2 { 964b1520d8bSClaudiu Manoil reg = <2>; 965b1520d8bSClaudiu Manoil status = "disabled"; 966b1520d8bSClaudiu Manoil }; 967b1520d8bSClaudiu Manoil 968b1520d8bSClaudiu Manoil mscc_felix_port3: port@3 { 969b1520d8bSClaudiu Manoil reg = <3>; 970b1520d8bSClaudiu Manoil status = "disabled"; 971b1520d8bSClaudiu Manoil }; 972b1520d8bSClaudiu Manoil 973b1520d8bSClaudiu Manoil /* Internal ports */ 974b1520d8bSClaudiu Manoil mscc_felix_port4: port@4 { 975b1520d8bSClaudiu Manoil reg = <4>; 976b1520d8bSClaudiu Manoil phy-mode = "internal"; 977b1520d8bSClaudiu Manoil status = "disabled"; 978b1520d8bSClaudiu Manoil 979b1520d8bSClaudiu Manoil fixed-link { 980b1520d8bSClaudiu Manoil speed = <2500>; 981b1520d8bSClaudiu Manoil full-duplex; 982b1520d8bSClaudiu Manoil }; 983b1520d8bSClaudiu Manoil }; 984b1520d8bSClaudiu Manoil 985b1520d8bSClaudiu Manoil mscc_felix_port5: port@5 { 986b1520d8bSClaudiu Manoil reg = <5>; 987b1520d8bSClaudiu Manoil phy-mode = "internal"; 988b1520d8bSClaudiu Manoil status = "disabled"; 989b1520d8bSClaudiu Manoil 990b1520d8bSClaudiu Manoil fixed-link { 991b1520d8bSClaudiu Manoil speed = <1000>; 992b1520d8bSClaudiu Manoil full-duplex; 993b1520d8bSClaudiu Manoil }; 994b1520d8bSClaudiu Manoil }; 995b1520d8bSClaudiu Manoil }; 996b1520d8bSClaudiu Manoil }; 997b1520d8bSClaudiu Manoil 998b1520d8bSClaudiu Manoil enetc_port3: ethernet@0,6 { 999b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 1000b1520d8bSClaudiu Manoil reg = <0x000600 0 0 0 0>; 1001b1520d8bSClaudiu Manoil phy-mode = "internal"; 1002b1520d8bSClaudiu Manoil status = "disabled"; 1003b1520d8bSClaudiu Manoil 1004b1520d8bSClaudiu Manoil fixed-link { 1005b1520d8bSClaudiu Manoil speed = <1000>; 1006b1520d8bSClaudiu Manoil full-duplex; 1007b1520d8bSClaudiu Manoil }; 10088897f325SBhaskar Upadhaya }; 10098897f325SBhaskar Upadhaya }; 1010791c88caSBiwen Li 1011791c88caSBiwen Li rcpm: power-controller@1e34040 { 1012791c88caSBiwen Li compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1013791c88caSBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 1014791c88caSBiwen Li #fsl,rcpm-wakeup-cells = <7>; 1015791c88caSBiwen Li }; 1016791c88caSBiwen Li 1017791c88caSBiwen Li ftm_alarm0: timer@2800000 { 1018791c88caSBiwen Li compatible = "fsl,ls1028a-ftm-alarm"; 1019791c88caSBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1020791c88caSBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1021791c88caSBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1022791c88caSBiwen Li }; 10238897f325SBhaskar Upadhaya }; 10247f538f19SWen He 10257f538f19SWen He malidp0: display@f080000 { 10267f538f19SWen He compatible = "arm,mali-dp500"; 10277f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 10287f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 10297f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 10307f538f19SWen He interrupt-names = "DE", "SE"; 103191035cb0SWen He clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 103213782597SWen He <&clockgen 2 2>; 10337f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 10347f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 10353a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 10367f538f19SWen He 10377f538f19SWen He port { 10387f538f19SWen He dp0_out: endpoint { 10397f538f19SWen He 10407f538f19SWen He }; 10417f538f19SWen He }; 10427f538f19SWen He }; 10438897f325SBhaskar Upadhaya}; 1044