18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 58897f325SBhaskar Upadhaya * Copyright 2018 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 208897f325SBhaskar Upadhaya cpus { 218897f325SBhaskar Upadhaya #address-cells = <1>; 228897f325SBhaskar Upadhaya #size-cells = <0>; 238897f325SBhaskar Upadhaya 248897f325SBhaskar Upadhaya cpu0: cpu@0 { 258897f325SBhaskar Upadhaya device_type = "cpu"; 268897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 278897f325SBhaskar Upadhaya reg = <0x0>; 288897f325SBhaskar Upadhaya enable-method = "psci"; 298897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 308897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3153f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 32571cebfeSYuantian Tang #cooling-cells = <2>; 338897f325SBhaskar Upadhaya }; 348897f325SBhaskar Upadhaya 358897f325SBhaskar Upadhaya cpu1: cpu@1 { 368897f325SBhaskar Upadhaya device_type = "cpu"; 378897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 388897f325SBhaskar Upadhaya reg = <0x1>; 398897f325SBhaskar Upadhaya enable-method = "psci"; 408897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 418897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 43571cebfeSYuantian Tang #cooling-cells = <2>; 448897f325SBhaskar Upadhaya }; 458897f325SBhaskar Upadhaya 468897f325SBhaskar Upadhaya l2: l2-cache { 478897f325SBhaskar Upadhaya compatible = "cache"; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya 518897f325SBhaskar Upadhaya idle-states { 528897f325SBhaskar Upadhaya /* 538897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 548897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 558897f325SBhaskar Upadhaya */ 568897f325SBhaskar Upadhaya entry-method = "arm,psci"; 578897f325SBhaskar Upadhaya 5853f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 598897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6053f2ac9dSRan Wang idle-state-name = "PW20"; 6153f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6253f2ac9dSRan Wang entry-latency-us = <2000>; 6353f2ac9dSRan Wang exit-latency-us = <2000>; 6453f2ac9dSRan Wang min-residency-us = <6000>; 658897f325SBhaskar Upadhaya }; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya 688897f325SBhaskar Upadhaya sysclk: clock-sysclk { 698897f325SBhaskar Upadhaya compatible = "fixed-clock"; 708897f325SBhaskar Upadhaya #clock-cells = <0>; 718897f325SBhaskar Upadhaya clock-frequency = <100000000>; 728897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 738897f325SBhaskar Upadhaya }; 748897f325SBhaskar Upadhaya 757f538f19SWen He dpclk: clock-dp { 767f538f19SWen He compatible = "fixed-clock"; 777f538f19SWen He #clock-cells = <0>; 787f538f19SWen He clock-frequency = <27000000>; 797f538f19SWen He clock-output-names= "dpclk"; 807f538f19SWen He }; 817f538f19SWen He 827f538f19SWen He aclk: clock-axi { 837f538f19SWen He compatible = "fixed-clock"; 847f538f19SWen He #clock-cells = <0>; 857f538f19SWen He clock-frequency = <650000000>; 867f538f19SWen He clock-output-names= "aclk"; 877f538f19SWen He }; 887f538f19SWen He 897f538f19SWen He pclk: clock-apb { 907f538f19SWen He compatible = "fixed-clock"; 917f538f19SWen He #clock-cells = <0>; 927f538f19SWen He clock-frequency = <650000000>; 937f538f19SWen He clock-output-names= "pclk"; 947f538f19SWen He }; 957f538f19SWen He 968897f325SBhaskar Upadhaya reboot { 978897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 988897f325SBhaskar Upadhaya regmap = <&dcfg>; 998897f325SBhaskar Upadhaya offset = <0xb0>; 1008897f325SBhaskar Upadhaya mask = <0x02>; 1018897f325SBhaskar Upadhaya }; 1028897f325SBhaskar Upadhaya 1038897f325SBhaskar Upadhaya timer { 1048897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 1058897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 1068897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1078897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1088897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1098897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1108897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1118897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1128897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1138897f325SBhaskar Upadhaya }; 1148897f325SBhaskar Upadhaya 115b9eb314aSAlison Wang pmu { 116b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 117b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 118b9eb314aSAlison Wang }; 119b9eb314aSAlison Wang 1208897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1218897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1228897f325SBhaskar Upadhaya #address-cells = <2>; 1238897f325SBhaskar Upadhaya #size-cells = <2>; 1248897f325SBhaskar Upadhaya ranges; 1258897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1268897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1278897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1288897f325SBhaskar Upadhaya interrupt-controller; 1298897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1308897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1318897f325SBhaskar Upadhaya its: gic-its@6020000 { 1328897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1338897f325SBhaskar Upadhaya msi-controller; 1348897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1358897f325SBhaskar Upadhaya }; 1368897f325SBhaskar Upadhaya }; 1378897f325SBhaskar Upadhaya 1388897f325SBhaskar Upadhaya soc: soc { 1398897f325SBhaskar Upadhaya compatible = "simple-bus"; 1408897f325SBhaskar Upadhaya #address-cells = <2>; 1418897f325SBhaskar Upadhaya #size-cells = <2>; 1428897f325SBhaskar Upadhaya ranges; 1438897f325SBhaskar Upadhaya 1448897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1458897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1468897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1478897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1488897f325SBhaskar Upadhaya big-endian; 1498897f325SBhaskar Upadhaya }; 1508897f325SBhaskar Upadhaya 1518897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 1528897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 1538897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 1548897f325SBhaskar Upadhaya big-endian; 1558897f325SBhaskar Upadhaya }; 1568897f325SBhaskar Upadhaya 1578897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 1588897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 1598897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 1608897f325SBhaskar Upadhaya big-endian; 1618897f325SBhaskar Upadhaya }; 1628897f325SBhaskar Upadhaya 1638897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 1648897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 1658897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 1668897f325SBhaskar Upadhaya #clock-cells = <2>; 1678897f325SBhaskar Upadhaya clocks = <&sysclk>; 1688897f325SBhaskar Upadhaya }; 1698897f325SBhaskar Upadhaya 1708897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 1718897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 1728897f325SBhaskar Upadhaya #address-cells = <1>; 1738897f325SBhaskar Upadhaya #size-cells = <0>; 1748897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 1758897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 176ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 1778897f325SBhaskar Upadhaya status = "disabled"; 1788897f325SBhaskar Upadhaya }; 1798897f325SBhaskar Upadhaya 1808897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 1818897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 1828897f325SBhaskar Upadhaya #address-cells = <1>; 1838897f325SBhaskar Upadhaya #size-cells = <0>; 1848897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 1858897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 186ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 1878897f325SBhaskar Upadhaya status = "disabled"; 1888897f325SBhaskar Upadhaya }; 1898897f325SBhaskar Upadhaya 1908897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 1918897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 1928897f325SBhaskar Upadhaya #address-cells = <1>; 1938897f325SBhaskar Upadhaya #size-cells = <0>; 1948897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 1958897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 196ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 1978897f325SBhaskar Upadhaya status = "disabled"; 1988897f325SBhaskar Upadhaya }; 1998897f325SBhaskar Upadhaya 2008897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2018897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2028897f325SBhaskar Upadhaya #address-cells = <1>; 2038897f325SBhaskar Upadhaya #size-cells = <0>; 2048897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2058897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 206ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2078897f325SBhaskar Upadhaya status = "disabled"; 2088897f325SBhaskar Upadhaya }; 2098897f325SBhaskar Upadhaya 2108897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2118897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2128897f325SBhaskar Upadhaya #address-cells = <1>; 2138897f325SBhaskar Upadhaya #size-cells = <0>; 2148897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2158897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 216ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2178897f325SBhaskar Upadhaya status = "disabled"; 2188897f325SBhaskar Upadhaya }; 2198897f325SBhaskar Upadhaya 2208897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2218897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2228897f325SBhaskar Upadhaya #address-cells = <1>; 2238897f325SBhaskar Upadhaya #size-cells = <0>; 2248897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2258897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 226ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2278897f325SBhaskar Upadhaya status = "disabled"; 2288897f325SBhaskar Upadhaya }; 2298897f325SBhaskar Upadhaya 2308897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2318897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2328897f325SBhaskar Upadhaya #address-cells = <1>; 2338897f325SBhaskar Upadhaya #size-cells = <0>; 2348897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2358897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 236ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2378897f325SBhaskar Upadhaya status = "disabled"; 2388897f325SBhaskar Upadhaya }; 2398897f325SBhaskar Upadhaya 2408897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2418897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2428897f325SBhaskar Upadhaya #address-cells = <1>; 2438897f325SBhaskar Upadhaya #size-cells = <0>; 2448897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2458897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 246ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2478897f325SBhaskar Upadhaya status = "disabled"; 2488897f325SBhaskar Upadhaya }; 2498897f325SBhaskar Upadhaya 2508897f325SBhaskar Upadhaya duart0: serial@21c0500 { 2518897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 2528897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 2538897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2548897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 2558897f325SBhaskar Upadhaya status = "disabled"; 2568897f325SBhaskar Upadhaya }; 2578897f325SBhaskar Upadhaya 2588897f325SBhaskar Upadhaya duart1: serial@21c0600 { 2598897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 2608897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 2618897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2628897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 2638897f325SBhaskar Upadhaya status = "disabled"; 2648897f325SBhaskar Upadhaya }; 2658897f325SBhaskar Upadhaya 266f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 267f54f7be5SAlison Wang #dma-cells = <2>; 268f54f7be5SAlison Wang compatible = "fsl,vf610-edma"; 269f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 270f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 271f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 272f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 273f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 274f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 275f54f7be5SAlison Wang dma-channels = <32>; 276f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 277f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 278f54f7be5SAlison Wang <&clockgen 4 1>; 279f54f7be5SAlison Wang }; 280f54f7be5SAlison Wang 2818897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 282f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 2838897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 2848897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2858897f325SBhaskar Upadhaya gpio-controller; 2868897f325SBhaskar Upadhaya #gpio-cells = <2>; 2878897f325SBhaskar Upadhaya interrupt-controller; 2888897f325SBhaskar Upadhaya #interrupt-cells = <2>; 289f64697bdSSong Hui little-endian; 2908897f325SBhaskar Upadhaya }; 2918897f325SBhaskar Upadhaya 2928897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 293f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 2948897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 2958897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2968897f325SBhaskar Upadhaya gpio-controller; 2978897f325SBhaskar Upadhaya #gpio-cells = <2>; 2988897f325SBhaskar Upadhaya interrupt-controller; 2998897f325SBhaskar Upadhaya #interrupt-cells = <2>; 300f64697bdSSong Hui little-endian; 3018897f325SBhaskar Upadhaya }; 3028897f325SBhaskar Upadhaya 3038897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 304f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3058897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 3068897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3078897f325SBhaskar Upadhaya gpio-controller; 3088897f325SBhaskar Upadhaya #gpio-cells = <2>; 3098897f325SBhaskar Upadhaya interrupt-controller; 3108897f325SBhaskar Upadhaya #interrupt-cells = <2>; 311f64697bdSSong Hui little-endian; 3128897f325SBhaskar Upadhaya }; 3138897f325SBhaskar Upadhaya 314c92f56faSRan Wang usb0: usb@3100000 { 315c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 316c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 317c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 318c92f56faSRan Wang dr_mode = "host"; 319c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 320c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 321c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 322c92f56faSRan Wang }; 323c92f56faSRan Wang 324c92f56faSRan Wang usb1: usb@3110000 { 325c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 326c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 327c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 328c92f56faSRan Wang dr_mode = "host"; 329c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 330c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 331c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 3328897f325SBhaskar Upadhaya }; 3338897f325SBhaskar Upadhaya 3348897f325SBhaskar Upadhaya sata: sata@3200000 { 3358897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 3368897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 3373f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 3388897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 3398897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3408897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3418897f325SBhaskar Upadhaya status = "disabled"; 3428897f325SBhaskar Upadhaya }; 3438897f325SBhaskar Upadhaya 3448897f325SBhaskar Upadhaya smmu: iommu@5000000 { 3458897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 3468897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 3478897f325SBhaskar Upadhaya #global-interrupts = <8>; 3488897f325SBhaskar Upadhaya #iommu-cells = <1>; 3498897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 3508897f325SBhaskar Upadhaya /* global secure fault */ 3518897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 3528897f325SBhaskar Upadhaya /* combined secure interrupt */ 3538897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 3548897f325SBhaskar Upadhaya /* global non-secure fault */ 3558897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 3568897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 3578897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 3588897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 3598897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 3608897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 3618897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 3628897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3638897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3648897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3658897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 3668897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 3678897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 3688897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 3698897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 3708897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 3718897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 3728897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 3738897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3748897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 3758897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 3768897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 3778897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 3788897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 3798897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3808897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3818897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3828897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3838897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3848897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3858897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 3868897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 3878897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 3888897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 3898897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 3908897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 3918897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 3928897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3938897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 3948897f325SBhaskar Upadhaya }; 395927d7f85SClaudiu Manoil 3961d0becabSHoria Geantă crypto: crypto@8000000 { 3971d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 3981d0becabSHoria Geantă fsl,sec-era = <10>; 3991d0becabSHoria Geantă #address-cells = <1>; 4001d0becabSHoria Geantă #size-cells = <1>; 4011d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 4021d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 4031d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4041d0becabSHoria Geantă dma-coherent; 4051d0becabSHoria Geantă 4061d0becabSHoria Geantă sec_jr0: jr@10000 { 4071d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4081d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4091d0becabSHoria Geantă reg = <0x10000 0x10000>; 4101d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4111d0becabSHoria Geantă }; 4121d0becabSHoria Geantă 4131d0becabSHoria Geantă sec_jr1: jr@20000 { 4141d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4151d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4161d0becabSHoria Geantă reg = <0x20000 0x10000>; 4171d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4181d0becabSHoria Geantă }; 4191d0becabSHoria Geantă 4201d0becabSHoria Geantă sec_jr2: jr@30000 { 4211d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4221d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4231d0becabSHoria Geantă reg = <0x30000 0x10000>; 4241d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4251d0becabSHoria Geantă }; 4261d0becabSHoria Geantă 4271d0becabSHoria Geantă sec_jr3: jr@40000 { 4281d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4291d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4301d0becabSHoria Geantă reg = <0x40000 0x10000>; 4311d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4321d0becabSHoria Geantă }; 4331d0becabSHoria Geantă }; 4341d0becabSHoria Geantă 4357802f88dSPeng Ma qdma: dma-controller@8380000 { 4367802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 4377802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 4387802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 4397802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 4407802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 4417802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 4427802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 4437802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 4447802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 4457802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 4467802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 4477802f88dSPeng Ma dma-channels = <8>; 4487802f88dSPeng Ma block-number = <1>; 4497802f88dSPeng Ma block-offset = <0x10000>; 4507802f88dSPeng Ma fsl,dma-queues = <2>; 4517802f88dSPeng Ma status-sizes = <64>; 4527802f88dSPeng Ma queue-sizes = <64 64>; 4537802f88dSPeng Ma }; 4547802f88dSPeng Ma 45557aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 45657aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 45757aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 45857aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 45957aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 46057aa1bc7SChuanhua Han }; 46157aa1bc7SChuanhua Han 46257aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 46357aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 46457aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 46557aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 46657aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 46757aa1bc7SChuanhua Han }; 46857aa1bc7SChuanhua Han 469f54f7be5SAlison Wang sai1: audio-controller@f100000 { 470f54f7be5SAlison Wang #sound-dai-cells = <0>; 471f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 472f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 473f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 474f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 475f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 476f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 477f54f7be5SAlison Wang dma-names = "tx", "rx"; 478f54f7be5SAlison Wang dmas = <&edma0 1 4>, 479f54f7be5SAlison Wang <&edma0 1 3>; 480f54f7be5SAlison Wang status = "disabled"; 481f54f7be5SAlison Wang }; 482f54f7be5SAlison Wang 483f54f7be5SAlison Wang sai2: audio-controller@f110000 { 484f54f7be5SAlison Wang #sound-dai-cells = <0>; 485f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 486f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 487f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 488f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 489f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 490f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 491f54f7be5SAlison Wang dma-names = "tx", "rx"; 492f54f7be5SAlison Wang dmas = <&edma0 1 6>, 493f54f7be5SAlison Wang <&edma0 1 5>; 494f54f7be5SAlison Wang status = "disabled"; 495f54f7be5SAlison Wang }; 496f54f7be5SAlison Wang 497f54f7be5SAlison Wang sai4: audio-controller@f130000 { 498f54f7be5SAlison Wang #sound-dai-cells = <0>; 499f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 500f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 501f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 502f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 503f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 504f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 505f54f7be5SAlison Wang dma-names = "tx", "rx"; 506f54f7be5SAlison Wang dmas = <&edma0 1 10>, 507f54f7be5SAlison Wang <&edma0 1 9>; 508f54f7be5SAlison Wang status = "disabled"; 509f54f7be5SAlison Wang }; 510f54f7be5SAlison Wang 511571cebfeSYuantian Tang tmu: tmu@1f00000 { 512571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 513571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 514571cebfeSYuantian Tang interrupts = <0 23 0x4>; 515571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 516571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 517571cebfeSYuantian Tang 0x00000001 0x0000002b 518571cebfeSYuantian Tang 0x00000002 0x00000031 519571cebfeSYuantian Tang 0x00000003 0x00000038 520571cebfeSYuantian Tang 0x00000004 0x0000003f 521571cebfeSYuantian Tang 0x00000005 0x00000045 522571cebfeSYuantian Tang 0x00000006 0x0000004c 523571cebfeSYuantian Tang 0x00000007 0x00000053 524571cebfeSYuantian Tang 0x00000008 0x00000059 525571cebfeSYuantian Tang 0x00000009 0x00000060 526571cebfeSYuantian Tang 0x0000000a 0x00000066 527571cebfeSYuantian Tang 0x0000000b 0x0000006d 528571cebfeSYuantian Tang 529571cebfeSYuantian Tang 0x00010000 0x0000001c 530571cebfeSYuantian Tang 0x00010001 0x00000024 531571cebfeSYuantian Tang 0x00010002 0x0000002c 532571cebfeSYuantian Tang 0x00010003 0x00000035 533571cebfeSYuantian Tang 0x00010004 0x0000003d 534571cebfeSYuantian Tang 0x00010005 0x00000045 535571cebfeSYuantian Tang 0x00010006 0x0000004d 536571cebfeSYuantian Tang 0x00010007 0x00000045 537571cebfeSYuantian Tang 0x00010008 0x0000005e 538571cebfeSYuantian Tang 0x00010009 0x00000066 539571cebfeSYuantian Tang 0x0001000a 0x0000006e 540571cebfeSYuantian Tang 541571cebfeSYuantian Tang 0x00020000 0x00000018 542571cebfeSYuantian Tang 0x00020001 0x00000022 543571cebfeSYuantian Tang 0x00020002 0x0000002d 544571cebfeSYuantian Tang 0x00020003 0x00000038 545571cebfeSYuantian Tang 0x00020004 0x00000043 546571cebfeSYuantian Tang 0x00020005 0x0000004d 547571cebfeSYuantian Tang 0x00020006 0x00000058 548571cebfeSYuantian Tang 0x00020007 0x00000063 549571cebfeSYuantian Tang 0x00020008 0x0000006e 550571cebfeSYuantian Tang 551571cebfeSYuantian Tang 0x00030000 0x00000010 552571cebfeSYuantian Tang 0x00030001 0x0000001c 553571cebfeSYuantian Tang 0x00030002 0x00000029 554571cebfeSYuantian Tang 0x00030003 0x00000036 555571cebfeSYuantian Tang 0x00030004 0x00000042 556571cebfeSYuantian Tang 0x00030005 0x0000004f 557571cebfeSYuantian Tang 0x00030006 0x0000005b 558571cebfeSYuantian Tang 0x00030007 0x00000068>; 559571cebfeSYuantian Tang little-endian; 560571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 561571cebfeSYuantian Tang }; 562571cebfeSYuantian Tang 563571cebfeSYuantian Tang thermal-zones { 564571cebfeSYuantian Tang core-cluster { 565571cebfeSYuantian Tang polling-delay-passive = <1000>; 566571cebfeSYuantian Tang polling-delay = <5000>; 567571cebfeSYuantian Tang thermal-sensors = <&tmu 0>; 568571cebfeSYuantian Tang 569571cebfeSYuantian Tang trips { 570571cebfeSYuantian Tang core_cluster_alert: core-cluster-alert { 571571cebfeSYuantian Tang temperature = <85000>; 572571cebfeSYuantian Tang hysteresis = <2000>; 573571cebfeSYuantian Tang type = "passive"; 574571cebfeSYuantian Tang }; 575571cebfeSYuantian Tang 576571cebfeSYuantian Tang core_cluster_crit: core-cluster-crit { 577571cebfeSYuantian Tang temperature = <95000>; 578571cebfeSYuantian Tang hysteresis = <2000>; 579571cebfeSYuantian Tang type = "critical"; 580571cebfeSYuantian Tang }; 581571cebfeSYuantian Tang }; 582571cebfeSYuantian Tang 583571cebfeSYuantian Tang cooling-maps { 584571cebfeSYuantian Tang map0 { 585571cebfeSYuantian Tang trip = <&core_cluster_alert>; 586571cebfeSYuantian Tang cooling-device = 587571cebfeSYuantian Tang <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 588571cebfeSYuantian Tang <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 589571cebfeSYuantian Tang }; 590571cebfeSYuantian Tang }; 591571cebfeSYuantian Tang }; 592571cebfeSYuantian Tang }; 593571cebfeSYuantian Tang 594927d7f85SClaudiu Manoil pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 595927d7f85SClaudiu Manoil compatible = "pci-host-ecam-generic"; 596927d7f85SClaudiu Manoil reg = <0x01 0xf0000000 0x0 0x100000>; 597927d7f85SClaudiu Manoil #address-cells = <3>; 598927d7f85SClaudiu Manoil #size-cells = <2>; 599927d7f85SClaudiu Manoil #interrupt-cells = <1>; 600927d7f85SClaudiu Manoil msi-parent = <&its>; 601927d7f85SClaudiu Manoil device_type = "pci"; 602927d7f85SClaudiu Manoil bus-range = <0x0 0x0>; 603927d7f85SClaudiu Manoil dma-coherent; 604927d7f85SClaudiu Manoil msi-map = <0 &its 0x17 0xe>; 605927d7f85SClaudiu Manoil iommu-map = <0 &smmu 0x17 0xe>; 606927d7f85SClaudiu Manoil /* PF0-6 BAR0 - non-prefetchable memory */ 607927d7f85SClaudiu Manoil ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 608927d7f85SClaudiu Manoil /* PF0-6 BAR2 - prefetchable memory */ 609927d7f85SClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 610927d7f85SClaudiu Manoil /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 611927d7f85SClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 612927d7f85SClaudiu Manoil /* PF0: VF0-1 BAR2 - prefetchable memory */ 613927d7f85SClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 614927d7f85SClaudiu Manoil /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 615927d7f85SClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 616927d7f85SClaudiu Manoil /* PF1: VF0-1 BAR2 - prefetchable memory */ 617927d7f85SClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 618927d7f85SClaudiu Manoil 619927d7f85SClaudiu Manoil enetc_port0: ethernet@0,0 { 620927d7f85SClaudiu Manoil compatible = "fsl,enetc"; 621927d7f85SClaudiu Manoil reg = <0x000000 0 0 0 0>; 622927d7f85SClaudiu Manoil }; 623927d7f85SClaudiu Manoil enetc_port1: ethernet@0,1 { 624927d7f85SClaudiu Manoil compatible = "fsl,enetc"; 625927d7f85SClaudiu Manoil reg = <0x000100 0 0 0 0>; 626927d7f85SClaudiu Manoil }; 62749401003SY.b. Lu ethernet@0,4 { 62849401003SY.b. Lu compatible = "fsl,enetc-ptp"; 62949401003SY.b. Lu reg = <0x000400 0 0 0 0>; 63049401003SY.b. Lu clocks = <&clockgen 4 0>; 63149401003SY.b. Lu little-endian; 63249401003SY.b. Lu }; 633927d7f85SClaudiu Manoil }; 6348897f325SBhaskar Upadhaya }; 6357f538f19SWen He 6367f538f19SWen He malidp0: display@f080000 { 6377f538f19SWen He compatible = "arm,mali-dp500"; 6387f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 6397f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 6407f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 6417f538f19SWen He interrupt-names = "DE", "SE"; 6427f538f19SWen He clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>; 6437f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 6447f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 6453a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 6467f538f19SWen He 6477f538f19SWen He port { 6487f538f19SWen He dp0_out: endpoint { 6497f538f19SWen He 6507f538f19SWen He }; 6517f538f19SWen He }; 6527f538f19SWen He }; 6538897f325SBhaskar Upadhaya}; 654