18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 58897f325SBhaskar Upadhaya * Copyright 2018 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 208897f325SBhaskar Upadhaya cpus { 218897f325SBhaskar Upadhaya #address-cells = <1>; 228897f325SBhaskar Upadhaya #size-cells = <0>; 238897f325SBhaskar Upadhaya 248897f325SBhaskar Upadhaya cpu0: cpu@0 { 258897f325SBhaskar Upadhaya device_type = "cpu"; 268897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 278897f325SBhaskar Upadhaya reg = <0x0>; 288897f325SBhaskar Upadhaya enable-method = "psci"; 298897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 308897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3153f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 32571cebfeSYuantian Tang #cooling-cells = <2>; 338897f325SBhaskar Upadhaya }; 348897f325SBhaskar Upadhaya 358897f325SBhaskar Upadhaya cpu1: cpu@1 { 368897f325SBhaskar Upadhaya device_type = "cpu"; 378897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 388897f325SBhaskar Upadhaya reg = <0x1>; 398897f325SBhaskar Upadhaya enable-method = "psci"; 408897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 418897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 43571cebfeSYuantian Tang #cooling-cells = <2>; 448897f325SBhaskar Upadhaya }; 458897f325SBhaskar Upadhaya 468897f325SBhaskar Upadhaya l2: l2-cache { 478897f325SBhaskar Upadhaya compatible = "cache"; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya 518897f325SBhaskar Upadhaya idle-states { 528897f325SBhaskar Upadhaya /* 538897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 548897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 558897f325SBhaskar Upadhaya */ 568897f325SBhaskar Upadhaya entry-method = "arm,psci"; 578897f325SBhaskar Upadhaya 5853f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 598897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6053f2ac9dSRan Wang idle-state-name = "PW20"; 6153f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6253f2ac9dSRan Wang entry-latency-us = <2000>; 6353f2ac9dSRan Wang exit-latency-us = <2000>; 6453f2ac9dSRan Wang min-residency-us = <6000>; 658897f325SBhaskar Upadhaya }; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya 688897f325SBhaskar Upadhaya sysclk: clock-sysclk { 698897f325SBhaskar Upadhaya compatible = "fixed-clock"; 708897f325SBhaskar Upadhaya #clock-cells = <0>; 718897f325SBhaskar Upadhaya clock-frequency = <100000000>; 728897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 738897f325SBhaskar Upadhaya }; 748897f325SBhaskar Upadhaya 7581f36887SWen He osc_27m: clock-osc-27m { 767f538f19SWen He compatible = "fixed-clock"; 777f538f19SWen He #clock-cells = <0>; 787f538f19SWen He clock-frequency = <27000000>; 7981f36887SWen He clock-output-names = "phy_27m"; 8081f36887SWen He }; 8181f36887SWen He 8281f36887SWen He dpclk: clock-controller@f1f0000 { 8381f36887SWen He compatible = "fsl,ls1028a-plldig"; 8481f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8591035cb0SWen He #clock-cells = <0>; 8681f36887SWen He clocks = <&osc_27m>; 877f538f19SWen He }; 887f538f19SWen He 898897f325SBhaskar Upadhaya reboot { 908897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 913f0fb37bSMichael Walle regmap = <&rst>; 928897f325SBhaskar Upadhaya offset = <0xb0>; 938897f325SBhaskar Upadhaya mask = <0x02>; 948897f325SBhaskar Upadhaya }; 958897f325SBhaskar Upadhaya 968897f325SBhaskar Upadhaya timer { 978897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 988897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 998897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1008897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1018897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1028897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1038897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1048897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1058897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1068897f325SBhaskar Upadhaya }; 1078897f325SBhaskar Upadhaya 108b9eb314aSAlison Wang pmu { 109b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 110b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111b9eb314aSAlison Wang }; 112b9eb314aSAlison Wang 1138897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1148897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1158897f325SBhaskar Upadhaya #address-cells = <2>; 1168897f325SBhaskar Upadhaya #size-cells = <2>; 1178897f325SBhaskar Upadhaya ranges; 1188897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1198897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1208897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1218897f325SBhaskar Upadhaya interrupt-controller; 1228897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1238897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1248897f325SBhaskar Upadhaya its: gic-its@6020000 { 1258897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1268897f325SBhaskar Upadhaya msi-controller; 1278897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1288897f325SBhaskar Upadhaya }; 1298897f325SBhaskar Upadhaya }; 1308897f325SBhaskar Upadhaya 13168e36a42SFabio Estevam thermal-zones { 13268e36a42SFabio Estevam core-cluster { 13368e36a42SFabio Estevam polling-delay-passive = <1000>; 13468e36a42SFabio Estevam polling-delay = <5000>; 13568e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 13668e36a42SFabio Estevam 13768e36a42SFabio Estevam trips { 13868e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 13968e36a42SFabio Estevam temperature = <85000>; 14068e36a42SFabio Estevam hysteresis = <2000>; 14168e36a42SFabio Estevam type = "passive"; 14268e36a42SFabio Estevam }; 14368e36a42SFabio Estevam 14468e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 14568e36a42SFabio Estevam temperature = <95000>; 14668e36a42SFabio Estevam hysteresis = <2000>; 14768e36a42SFabio Estevam type = "critical"; 14868e36a42SFabio Estevam }; 14968e36a42SFabio Estevam }; 15068e36a42SFabio Estevam 15168e36a42SFabio Estevam cooling-maps { 15268e36a42SFabio Estevam map0 { 15368e36a42SFabio Estevam trip = <&core_cluster_alert>; 15468e36a42SFabio Estevam cooling-device = 15568e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 15668e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 15768e36a42SFabio Estevam }; 15868e36a42SFabio Estevam }; 15968e36a42SFabio Estevam }; 16068e36a42SFabio Estevam }; 16168e36a42SFabio Estevam 1628897f325SBhaskar Upadhaya soc: soc { 1638897f325SBhaskar Upadhaya compatible = "simple-bus"; 1648897f325SBhaskar Upadhaya #address-cells = <2>; 1658897f325SBhaskar Upadhaya #size-cells = <2>; 1668897f325SBhaskar Upadhaya ranges; 1678897f325SBhaskar Upadhaya 1688897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1698897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1708897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1718897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1728897f325SBhaskar Upadhaya big-endian; 1738897f325SBhaskar Upadhaya }; 1748897f325SBhaskar Upadhaya 1758897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 1768897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 1778897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 17833eae7fbSYinbo Zhu little-endian; 1798897f325SBhaskar Upadhaya }; 1808897f325SBhaskar Upadhaya 1813f0fb37bSMichael Walle rst: syscon@1e60000 { 1823f0fb37bSMichael Walle compatible = "syscon"; 1833f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 1843f0fb37bSMichael Walle little-endian; 1853f0fb37bSMichael Walle }; 1863f0fb37bSMichael Walle 1878897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 1888897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 1898897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 1908897f325SBhaskar Upadhaya big-endian; 1918897f325SBhaskar Upadhaya }; 1928897f325SBhaskar Upadhaya 1938897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 1948897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 1958897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 1968897f325SBhaskar Upadhaya #clock-cells = <2>; 1978897f325SBhaskar Upadhaya clocks = <&sysclk>; 1988897f325SBhaskar Upadhaya }; 1998897f325SBhaskar Upadhaya 2008897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2018897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2028897f325SBhaskar Upadhaya #address-cells = <1>; 2038897f325SBhaskar Upadhaya #size-cells = <0>; 2048897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2058897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 206ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2078897f325SBhaskar Upadhaya status = "disabled"; 2088897f325SBhaskar Upadhaya }; 2098897f325SBhaskar Upadhaya 2108897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2118897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2128897f325SBhaskar Upadhaya #address-cells = <1>; 2138897f325SBhaskar Upadhaya #size-cells = <0>; 2148897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2158897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 216ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2178897f325SBhaskar Upadhaya status = "disabled"; 2188897f325SBhaskar Upadhaya }; 2198897f325SBhaskar Upadhaya 2208897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2218897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2228897f325SBhaskar Upadhaya #address-cells = <1>; 2238897f325SBhaskar Upadhaya #size-cells = <0>; 2248897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2258897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 226ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2278897f325SBhaskar Upadhaya status = "disabled"; 2288897f325SBhaskar Upadhaya }; 2298897f325SBhaskar Upadhaya 2308897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2318897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2328897f325SBhaskar Upadhaya #address-cells = <1>; 2338897f325SBhaskar Upadhaya #size-cells = <0>; 2348897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2358897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 236ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2378897f325SBhaskar Upadhaya status = "disabled"; 2388897f325SBhaskar Upadhaya }; 2398897f325SBhaskar Upadhaya 2408897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2418897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2428897f325SBhaskar Upadhaya #address-cells = <1>; 2438897f325SBhaskar Upadhaya #size-cells = <0>; 2448897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2458897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 246ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2478897f325SBhaskar Upadhaya status = "disabled"; 2488897f325SBhaskar Upadhaya }; 2498897f325SBhaskar Upadhaya 2508897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2518897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2528897f325SBhaskar Upadhaya #address-cells = <1>; 2538897f325SBhaskar Upadhaya #size-cells = <0>; 2548897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2558897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 256ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2578897f325SBhaskar Upadhaya status = "disabled"; 2588897f325SBhaskar Upadhaya }; 2598897f325SBhaskar Upadhaya 2608897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2618897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2628897f325SBhaskar Upadhaya #address-cells = <1>; 2638897f325SBhaskar Upadhaya #size-cells = <0>; 2648897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2658897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 266ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2678897f325SBhaskar Upadhaya status = "disabled"; 2688897f325SBhaskar Upadhaya }; 2698897f325SBhaskar Upadhaya 2708897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2718897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2728897f325SBhaskar Upadhaya #address-cells = <1>; 2738897f325SBhaskar Upadhaya #size-cells = <0>; 2748897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2758897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 276ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2778897f325SBhaskar Upadhaya status = "disabled"; 2788897f325SBhaskar Upadhaya }; 2798897f325SBhaskar Upadhaya 280c77fae5bSAshish Kumar fspi: spi@20c0000 { 281c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 282c77fae5bSAshish Kumar #address-cells = <1>; 283c77fae5bSAshish Kumar #size-cells = <0>; 284c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 285c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 286c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 287c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 288c77fae5bSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 289c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 290c77fae5bSAshish Kumar status = "disabled"; 291c77fae5bSAshish Kumar }; 292c77fae5bSAshish Kumar 293c2d35adaSMichael Walle dspi0: spi@2100000 { 294c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 295c2d35adaSMichael Walle #address-cells = <1>; 296c2d35adaSMichael Walle #size-cells = <0>; 297c2d35adaSMichael Walle reg = <0x0 0x2100000 0x0 0x10000>; 298c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 299c2d35adaSMichael Walle clock-names = "dspi"; 300c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 301c2d35adaSMichael Walle spi-num-chipselects = <4>; 302c2d35adaSMichael Walle little-endian; 303c2d35adaSMichael Walle status = "disabled"; 304c2d35adaSMichael Walle }; 305c2d35adaSMichael Walle 306c2d35adaSMichael Walle dspi1: spi@2110000 { 307c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 308c2d35adaSMichael Walle #address-cells = <1>; 309c2d35adaSMichael Walle #size-cells = <0>; 310c2d35adaSMichael Walle reg = <0x0 0x2110000 0x0 0x10000>; 311c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 312c2d35adaSMichael Walle clock-names = "dspi"; 313c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 314c2d35adaSMichael Walle spi-num-chipselects = <4>; 315c2d35adaSMichael Walle little-endian; 316c2d35adaSMichael Walle status = "disabled"; 317c2d35adaSMichael Walle }; 318c2d35adaSMichael Walle 319c2d35adaSMichael Walle dspi2: spi@2120000 { 320c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 321c2d35adaSMichael Walle #address-cells = <1>; 322c2d35adaSMichael Walle #size-cells = <0>; 323c2d35adaSMichael Walle reg = <0x0 0x2120000 0x0 0x10000>; 324c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 325c2d35adaSMichael Walle clock-names = "dspi"; 326c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 327c2d35adaSMichael Walle spi-num-chipselects = <3>; 328c2d35adaSMichael Walle little-endian; 329c2d35adaSMichael Walle status = "disabled"; 330c2d35adaSMichael Walle }; 331c2d35adaSMichael Walle 332491d3a3fSAshish Kumar esdhc: mmc@2140000 { 333491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 334491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 335491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 336491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 337491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 338491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 339491d3a3fSAshish Kumar sdhci,auto-cmd12; 340491d3a3fSAshish Kumar little-endian; 341491d3a3fSAshish Kumar bus-width = <4>; 342491d3a3fSAshish Kumar status = "disabled"; 343491d3a3fSAshish Kumar }; 344491d3a3fSAshish Kumar 345491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 346491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 347491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 348491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 349491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 350491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 351491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 352491d3a3fSAshish Kumar sdhci,auto-cmd12; 353491d3a3fSAshish Kumar broken-cd; 354491d3a3fSAshish Kumar little-endian; 355491d3a3fSAshish Kumar bus-width = <4>; 356491d3a3fSAshish Kumar status = "disabled"; 357491d3a3fSAshish Kumar }; 358491d3a3fSAshish Kumar 3598897f325SBhaskar Upadhaya duart0: serial@21c0500 { 3608897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3618897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 3628897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3638897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3648897f325SBhaskar Upadhaya status = "disabled"; 3658897f325SBhaskar Upadhaya }; 3668897f325SBhaskar Upadhaya 3678897f325SBhaskar Upadhaya duart1: serial@21c0600 { 3688897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3698897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 3708897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3718897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3728897f325SBhaskar Upadhaya status = "disabled"; 3738897f325SBhaskar Upadhaya }; 3748897f325SBhaskar Upadhaya 375f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 376f54f7be5SAlison Wang #dma-cells = <2>; 377869bf854SPeng Ma compatible = "fsl,ls1028a-edma"; 378f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 379f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 380f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 381f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 382f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 383f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 384f54f7be5SAlison Wang dma-channels = <32>; 385f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 386f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 387f54f7be5SAlison Wang <&clockgen 4 1>; 388f54f7be5SAlison Wang }; 389f54f7be5SAlison Wang 3908897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 391f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3928897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 3938897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3948897f325SBhaskar Upadhaya gpio-controller; 3958897f325SBhaskar Upadhaya #gpio-cells = <2>; 3968897f325SBhaskar Upadhaya interrupt-controller; 3978897f325SBhaskar Upadhaya #interrupt-cells = <2>; 398f64697bdSSong Hui little-endian; 3998897f325SBhaskar Upadhaya }; 4008897f325SBhaskar Upadhaya 4018897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 402f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4038897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 4048897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 4058897f325SBhaskar Upadhaya gpio-controller; 4068897f325SBhaskar Upadhaya #gpio-cells = <2>; 4078897f325SBhaskar Upadhaya interrupt-controller; 4088897f325SBhaskar Upadhaya #interrupt-cells = <2>; 409f64697bdSSong Hui little-endian; 4108897f325SBhaskar Upadhaya }; 4118897f325SBhaskar Upadhaya 4128897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 413f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4148897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 4158897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 4168897f325SBhaskar Upadhaya gpio-controller; 4178897f325SBhaskar Upadhaya #gpio-cells = <2>; 4188897f325SBhaskar Upadhaya interrupt-controller; 4198897f325SBhaskar Upadhaya #interrupt-cells = <2>; 420f64697bdSSong Hui little-endian; 4218897f325SBhaskar Upadhaya }; 4228897f325SBhaskar Upadhaya 423c92f56faSRan Wang usb0: usb@3100000 { 424c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 425c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 426c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 427c92f56faSRan Wang dr_mode = "host"; 428c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 429c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 430c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 431c92f56faSRan Wang }; 432c92f56faSRan Wang 433c92f56faSRan Wang usb1: usb@3110000 { 434c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 435c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 436c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 437c92f56faSRan Wang dr_mode = "host"; 438c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 439c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 440c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 4418897f325SBhaskar Upadhaya }; 4428897f325SBhaskar Upadhaya 4438897f325SBhaskar Upadhaya sata: sata@3200000 { 4448897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 4458897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 4463f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 4478897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 4488897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4498897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 4508897f325SBhaskar Upadhaya status = "disabled"; 4518897f325SBhaskar Upadhaya }; 4528897f325SBhaskar Upadhaya 4538897f325SBhaskar Upadhaya smmu: iommu@5000000 { 4548897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 4558897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 4568897f325SBhaskar Upadhaya #global-interrupts = <8>; 4578897f325SBhaskar Upadhaya #iommu-cells = <1>; 4588897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 4598897f325SBhaskar Upadhaya /* global secure fault */ 4608897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 4618897f325SBhaskar Upadhaya /* combined secure interrupt */ 4628897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 4638897f325SBhaskar Upadhaya /* global non-secure fault */ 4648897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 4658897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 4668897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 4678897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 4688897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 4698897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 4708897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 4718897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 4728897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 4738897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 4748897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 4758897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 4768897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 4778897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 4788897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 4798897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4808897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 4818897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 4828897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 4838897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 4848897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 4858897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 4868897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 4878897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 4888897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4898897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4908897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4918897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4928897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4938897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4948897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 4958897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 4968897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 4978897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 4988897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 4998897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 5008897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 5018897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 5028897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 5038897f325SBhaskar Upadhaya }; 504927d7f85SClaudiu Manoil 5051d0becabSHoria Geantă crypto: crypto@8000000 { 5061d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 5071d0becabSHoria Geantă fsl,sec-era = <10>; 5081d0becabSHoria Geantă #address-cells = <1>; 5091d0becabSHoria Geantă #size-cells = <1>; 5101d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 5111d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 5121d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 5131d0becabSHoria Geantă dma-coherent; 5141d0becabSHoria Geantă 5151d0becabSHoria Geantă sec_jr0: jr@10000 { 5161d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5171d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5181d0becabSHoria Geantă reg = <0x10000 0x10000>; 5191d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 5201d0becabSHoria Geantă }; 5211d0becabSHoria Geantă 5221d0becabSHoria Geantă sec_jr1: jr@20000 { 5231d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5241d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5251d0becabSHoria Geantă reg = <0x20000 0x10000>; 5261d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 5271d0becabSHoria Geantă }; 5281d0becabSHoria Geantă 5291d0becabSHoria Geantă sec_jr2: jr@30000 { 5301d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5311d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5321d0becabSHoria Geantă reg = <0x30000 0x10000>; 5331d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 5341d0becabSHoria Geantă }; 5351d0becabSHoria Geantă 5361d0becabSHoria Geantă sec_jr3: jr@40000 { 5371d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5381d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5391d0becabSHoria Geantă reg = <0x40000 0x10000>; 5401d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5411d0becabSHoria Geantă }; 5421d0becabSHoria Geantă }; 5431d0becabSHoria Geantă 5447802f88dSPeng Ma qdma: dma-controller@8380000 { 5457802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 5467802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 5477802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 5487802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 5497802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 5507802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 5517802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 5527802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 5537802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 5547802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 5557802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 5567802f88dSPeng Ma dma-channels = <8>; 5577802f88dSPeng Ma block-number = <1>; 5587802f88dSPeng Ma block-offset = <0x10000>; 5597802f88dSPeng Ma fsl,dma-queues = <2>; 5607802f88dSPeng Ma status-sizes = <64>; 5617802f88dSPeng Ma queue-sizes = <64 64>; 5627802f88dSPeng Ma }; 5637802f88dSPeng Ma 56457aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 56557aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 56657aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 56757aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 56857aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 56957aa1bc7SChuanhua Han }; 57057aa1bc7SChuanhua Han 57157aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 57257aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 57357aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 57457aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 57557aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 57657aa1bc7SChuanhua Han }; 57757aa1bc7SChuanhua Han 578f54f7be5SAlison Wang sai1: audio-controller@f100000 { 579f54f7be5SAlison Wang #sound-dai-cells = <0>; 580f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 581f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 582f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 583f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 584f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 585f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 586f54f7be5SAlison Wang dma-names = "tx", "rx"; 587f54f7be5SAlison Wang dmas = <&edma0 1 4>, 588f54f7be5SAlison Wang <&edma0 1 3>; 5899c015e13SMichael Walle fsl,sai-asynchronous; 590f54f7be5SAlison Wang status = "disabled"; 591f54f7be5SAlison Wang }; 592f54f7be5SAlison Wang 593f54f7be5SAlison Wang sai2: audio-controller@f110000 { 594f54f7be5SAlison Wang #sound-dai-cells = <0>; 595f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 596f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 597f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 598f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 599f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 600f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 601f54f7be5SAlison Wang dma-names = "tx", "rx"; 602f54f7be5SAlison Wang dmas = <&edma0 1 6>, 603f54f7be5SAlison Wang <&edma0 1 5>; 6049c015e13SMichael Walle fsl,sai-asynchronous; 605f54f7be5SAlison Wang status = "disabled"; 606f54f7be5SAlison Wang }; 607f54f7be5SAlison Wang 608434f9cc1SMichael Walle sai3: audio-controller@f120000 { 609434f9cc1SMichael Walle #sound-dai-cells = <0>; 610434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 611434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 612434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 613434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 614434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 615434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 616434f9cc1SMichael Walle dma-names = "tx", "rx"; 617434f9cc1SMichael Walle dmas = <&edma0 1 8>, 618434f9cc1SMichael Walle <&edma0 1 7>; 6199c015e13SMichael Walle fsl,sai-asynchronous; 620f54f7be5SAlison Wang status = "disabled"; 621f54f7be5SAlison Wang }; 622f54f7be5SAlison Wang 623f54f7be5SAlison Wang sai4: audio-controller@f130000 { 624f54f7be5SAlison Wang #sound-dai-cells = <0>; 625f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 626f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 627f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 628f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 629f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 630f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 631f54f7be5SAlison Wang dma-names = "tx", "rx"; 632f54f7be5SAlison Wang dmas = <&edma0 1 10>, 633f54f7be5SAlison Wang <&edma0 1 9>; 6349c015e13SMichael Walle fsl,sai-asynchronous; 635f54f7be5SAlison Wang status = "disabled"; 636f54f7be5SAlison Wang }; 637f54f7be5SAlison Wang 638434f9cc1SMichael Walle sai5: audio-controller@f140000 { 639434f9cc1SMichael Walle #sound-dai-cells = <0>; 640434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 641434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 642434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 643434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 644434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 645434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 646434f9cc1SMichael Walle dma-names = "tx", "rx"; 647434f9cc1SMichael Walle dmas = <&edma0 1 12>, 648434f9cc1SMichael Walle <&edma0 1 11>; 6499c015e13SMichael Walle fsl,sai-asynchronous; 650434f9cc1SMichael Walle status = "disabled"; 651434f9cc1SMichael Walle }; 652434f9cc1SMichael Walle 653434f9cc1SMichael Walle sai6: audio-controller@f150000 { 654434f9cc1SMichael Walle #sound-dai-cells = <0>; 655434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 656434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 657434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 658434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 659434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 660434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 661434f9cc1SMichael Walle dma-names = "tx", "rx"; 662434f9cc1SMichael Walle dmas = <&edma0 1 14>, 663434f9cc1SMichael Walle <&edma0 1 13>; 6649c015e13SMichael Walle fsl,sai-asynchronous; 6658897f325SBhaskar Upadhaya status = "disabled"; 6668897f325SBhaskar Upadhaya }; 6678897f325SBhaskar Upadhaya 6680b680963SFabio Estevam tmu: tmu@1f80000 { 669571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 670571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 671571cebfeSYuantian Tang interrupts = <0 23 0x4>; 672571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 673571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 674571cebfeSYuantian Tang 0x00000001 0x0000002b 675571cebfeSYuantian Tang 0x00000002 0x00000031 676571cebfeSYuantian Tang 0x00000003 0x00000038 677571cebfeSYuantian Tang 0x00000004 0x0000003f 678571cebfeSYuantian Tang 0x00000005 0x00000045 679571cebfeSYuantian Tang 0x00000006 0x0000004c 680571cebfeSYuantian Tang 0x00000007 0x00000053 681571cebfeSYuantian Tang 0x00000008 0x00000059 682571cebfeSYuantian Tang 0x00000009 0x00000060 683571cebfeSYuantian Tang 0x0000000a 0x00000066 684571cebfeSYuantian Tang 0x0000000b 0x0000006d 685571cebfeSYuantian Tang 686571cebfeSYuantian Tang 0x00010000 0x0000001c 687571cebfeSYuantian Tang 0x00010001 0x00000024 688571cebfeSYuantian Tang 0x00010002 0x0000002c 689571cebfeSYuantian Tang 0x00010003 0x00000035 690571cebfeSYuantian Tang 0x00010004 0x0000003d 691571cebfeSYuantian Tang 0x00010005 0x00000045 692571cebfeSYuantian Tang 0x00010006 0x0000004d 693961f8209SMichael Walle 0x00010007 0x00000055 694571cebfeSYuantian Tang 0x00010008 0x0000005e 695571cebfeSYuantian Tang 0x00010009 0x00000066 696571cebfeSYuantian Tang 0x0001000a 0x0000006e 697571cebfeSYuantian Tang 698571cebfeSYuantian Tang 0x00020000 0x00000018 699571cebfeSYuantian Tang 0x00020001 0x00000022 700571cebfeSYuantian Tang 0x00020002 0x0000002d 701571cebfeSYuantian Tang 0x00020003 0x00000038 702571cebfeSYuantian Tang 0x00020004 0x00000043 703571cebfeSYuantian Tang 0x00020005 0x0000004d 704571cebfeSYuantian Tang 0x00020006 0x00000058 705571cebfeSYuantian Tang 0x00020007 0x00000063 706571cebfeSYuantian Tang 0x00020008 0x0000006e 707571cebfeSYuantian Tang 708571cebfeSYuantian Tang 0x00030000 0x00000010 709571cebfeSYuantian Tang 0x00030001 0x0000001c 710571cebfeSYuantian Tang 0x00030002 0x00000029 711571cebfeSYuantian Tang 0x00030003 0x00000036 712571cebfeSYuantian Tang 0x00030004 0x00000042 713571cebfeSYuantian Tang 0x00030005 0x0000004f 714571cebfeSYuantian Tang 0x00030006 0x0000005b 715571cebfeSYuantian Tang 0x00030007 0x00000068>; 716571cebfeSYuantian Tang little-endian; 717571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 718571cebfeSYuantian Tang }; 719571cebfeSYuantian Tang 7208897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 7218897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 7228897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 7238897f325SBhaskar Upadhaya #address-cells = <3>; 7248897f325SBhaskar Upadhaya #size-cells = <2>; 7258897f325SBhaskar Upadhaya #interrupt-cells = <1>; 7268897f325SBhaskar Upadhaya msi-parent = <&its>; 7278897f325SBhaskar Upadhaya device_type = "pci"; 7288897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 7298897f325SBhaskar Upadhaya dma-coherent; 7308897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 7318897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 7328897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 7338897f325SBhaskar Upadhaya ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 7348897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 7358897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 7368897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 7378897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 7388897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 7398897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 7408897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 7418897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 7428897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 7438897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 7448897f325SBhaskar Upadhaya 7458897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 7468897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 7478897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 7488897f325SBhaskar Upadhaya }; 7498897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 7508897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 7518897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 7528897f325SBhaskar Upadhaya }; 7538488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 7548488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 7558488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 7568488d8e9SClaudiu Manoil #address-cells = <1>; 7578488d8e9SClaudiu Manoil #size-cells = <0>; 7588488d8e9SClaudiu Manoil }; 75949401003SY.b. Lu ethernet@0,4 { 76049401003SY.b. Lu compatible = "fsl,enetc-ptp"; 76149401003SY.b. Lu reg = <0x000400 0 0 0 0>; 76249401003SY.b. Lu clocks = <&clockgen 4 0>; 76349401003SY.b. Lu little-endian; 764ab84bad5SYangbo Lu fsl,extts-fifo; 76549401003SY.b. Lu }; 7668897f325SBhaskar Upadhaya }; 7678897f325SBhaskar Upadhaya }; 7687f538f19SWen He 7697f538f19SWen He malidp0: display@f080000 { 7707f538f19SWen He compatible = "arm,mali-dp500"; 7717f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 7727f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 7737f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 7747f538f19SWen He interrupt-names = "DE", "SE"; 77591035cb0SWen He clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 77613782597SWen He <&clockgen 2 2>; 7777f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 7787f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 7793a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 7807f538f19SWen He 7817f538f19SWen He port { 7827f538f19SWen He dp0_out: endpoint { 7837f538f19SWen He 7847f538f19SWen He }; 7857f538f19SWen He }; 7867f538f19SWen He }; 7878897f325SBhaskar Upadhaya}; 788