18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 58897f325SBhaskar Upadhaya * Copyright 2018 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 208897f325SBhaskar Upadhaya cpus { 218897f325SBhaskar Upadhaya #address-cells = <1>; 228897f325SBhaskar Upadhaya #size-cells = <0>; 238897f325SBhaskar Upadhaya 248897f325SBhaskar Upadhaya cpu0: cpu@0 { 258897f325SBhaskar Upadhaya device_type = "cpu"; 268897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 278897f325SBhaskar Upadhaya reg = <0x0>; 288897f325SBhaskar Upadhaya enable-method = "psci"; 298897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 308897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3153f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 32571cebfeSYuantian Tang #cooling-cells = <2>; 338897f325SBhaskar Upadhaya }; 348897f325SBhaskar Upadhaya 358897f325SBhaskar Upadhaya cpu1: cpu@1 { 368897f325SBhaskar Upadhaya device_type = "cpu"; 378897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 388897f325SBhaskar Upadhaya reg = <0x1>; 398897f325SBhaskar Upadhaya enable-method = "psci"; 408897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 418897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 43571cebfeSYuantian Tang #cooling-cells = <2>; 448897f325SBhaskar Upadhaya }; 458897f325SBhaskar Upadhaya 468897f325SBhaskar Upadhaya l2: l2-cache { 478897f325SBhaskar Upadhaya compatible = "cache"; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya 518897f325SBhaskar Upadhaya idle-states { 528897f325SBhaskar Upadhaya /* 538897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 548897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 558897f325SBhaskar Upadhaya */ 568897f325SBhaskar Upadhaya entry-method = "arm,psci"; 578897f325SBhaskar Upadhaya 5853f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 598897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6053f2ac9dSRan Wang idle-state-name = "PW20"; 6153f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6253f2ac9dSRan Wang entry-latency-us = <2000>; 6353f2ac9dSRan Wang exit-latency-us = <2000>; 6453f2ac9dSRan Wang min-residency-us = <6000>; 658897f325SBhaskar Upadhaya }; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya 688897f325SBhaskar Upadhaya sysclk: clock-sysclk { 698897f325SBhaskar Upadhaya compatible = "fixed-clock"; 708897f325SBhaskar Upadhaya #clock-cells = <0>; 718897f325SBhaskar Upadhaya clock-frequency = <100000000>; 728897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 738897f325SBhaskar Upadhaya }; 748897f325SBhaskar Upadhaya 7581f36887SWen He osc_27m: clock-osc-27m { 767f538f19SWen He compatible = "fixed-clock"; 777f538f19SWen He #clock-cells = <0>; 787f538f19SWen He clock-frequency = <27000000>; 7981f36887SWen He clock-output-names = "phy_27m"; 8081f36887SWen He }; 8181f36887SWen He 8281f36887SWen He dpclk: clock-controller@f1f0000 { 8381f36887SWen He compatible = "fsl,ls1028a-plldig"; 8481f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8591035cb0SWen He #clock-cells = <0>; 8681f36887SWen He clocks = <&osc_27m>; 877f538f19SWen He }; 887f538f19SWen He 898897f325SBhaskar Upadhaya reboot { 908897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 913f0fb37bSMichael Walle regmap = <&rst>; 928897f325SBhaskar Upadhaya offset = <0xb0>; 938897f325SBhaskar Upadhaya mask = <0x02>; 948897f325SBhaskar Upadhaya }; 958897f325SBhaskar Upadhaya 968897f325SBhaskar Upadhaya timer { 978897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 988897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 998897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1008897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1018897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1028897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1038897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1048897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1058897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1068897f325SBhaskar Upadhaya }; 1078897f325SBhaskar Upadhaya 108b9eb314aSAlison Wang pmu { 109b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 110b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111b9eb314aSAlison Wang }; 112b9eb314aSAlison Wang 1138897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1148897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1158897f325SBhaskar Upadhaya #address-cells = <2>; 1168897f325SBhaskar Upadhaya #size-cells = <2>; 1178897f325SBhaskar Upadhaya ranges; 1188897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1198897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1208897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1218897f325SBhaskar Upadhaya interrupt-controller; 1228897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1238897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1248897f325SBhaskar Upadhaya its: gic-its@6020000 { 1258897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1268897f325SBhaskar Upadhaya msi-controller; 1278897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1288897f325SBhaskar Upadhaya }; 1298897f325SBhaskar Upadhaya }; 1308897f325SBhaskar Upadhaya 13168e36a42SFabio Estevam thermal-zones { 13268e36a42SFabio Estevam core-cluster { 13368e36a42SFabio Estevam polling-delay-passive = <1000>; 13468e36a42SFabio Estevam polling-delay = <5000>; 13568e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 13668e36a42SFabio Estevam 13768e36a42SFabio Estevam trips { 13868e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 13968e36a42SFabio Estevam temperature = <85000>; 14068e36a42SFabio Estevam hysteresis = <2000>; 14168e36a42SFabio Estevam type = "passive"; 14268e36a42SFabio Estevam }; 14368e36a42SFabio Estevam 14468e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 14568e36a42SFabio Estevam temperature = <95000>; 14668e36a42SFabio Estevam hysteresis = <2000>; 14768e36a42SFabio Estevam type = "critical"; 14868e36a42SFabio Estevam }; 14968e36a42SFabio Estevam }; 15068e36a42SFabio Estevam 15168e36a42SFabio Estevam cooling-maps { 15268e36a42SFabio Estevam map0 { 15368e36a42SFabio Estevam trip = <&core_cluster_alert>; 15468e36a42SFabio Estevam cooling-device = 15568e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 15668e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 15768e36a42SFabio Estevam }; 15868e36a42SFabio Estevam }; 15968e36a42SFabio Estevam }; 16068e36a42SFabio Estevam }; 16168e36a42SFabio Estevam 1628897f325SBhaskar Upadhaya soc: soc { 1638897f325SBhaskar Upadhaya compatible = "simple-bus"; 1648897f325SBhaskar Upadhaya #address-cells = <2>; 1658897f325SBhaskar Upadhaya #size-cells = <2>; 1668897f325SBhaskar Upadhaya ranges; 1678897f325SBhaskar Upadhaya 1688897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1698897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1708897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1718897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1728897f325SBhaskar Upadhaya big-endian; 1738897f325SBhaskar Upadhaya }; 1748897f325SBhaskar Upadhaya 1758897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 1768897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 1778897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 17833eae7fbSYinbo Zhu little-endian; 1798897f325SBhaskar Upadhaya }; 1808897f325SBhaskar Upadhaya 1813f0fb37bSMichael Walle rst: syscon@1e60000 { 1823f0fb37bSMichael Walle compatible = "syscon"; 1833f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 1843f0fb37bSMichael Walle little-endian; 1853f0fb37bSMichael Walle }; 1863f0fb37bSMichael Walle 1878897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 1888897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 1898897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 1908897f325SBhaskar Upadhaya big-endian; 1918897f325SBhaskar Upadhaya }; 1928897f325SBhaskar Upadhaya 1938897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 1948897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 1958897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 1968897f325SBhaskar Upadhaya #clock-cells = <2>; 1978897f325SBhaskar Upadhaya clocks = <&sysclk>; 1988897f325SBhaskar Upadhaya }; 1998897f325SBhaskar Upadhaya 2008897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2018897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2028897f325SBhaskar Upadhaya #address-cells = <1>; 2038897f325SBhaskar Upadhaya #size-cells = <0>; 2048897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2058897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 206ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2078897f325SBhaskar Upadhaya status = "disabled"; 2088897f325SBhaskar Upadhaya }; 2098897f325SBhaskar Upadhaya 2108897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2118897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2128897f325SBhaskar Upadhaya #address-cells = <1>; 2138897f325SBhaskar Upadhaya #size-cells = <0>; 2148897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2158897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 216ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2178897f325SBhaskar Upadhaya status = "disabled"; 2188897f325SBhaskar Upadhaya }; 2198897f325SBhaskar Upadhaya 2208897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2218897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2228897f325SBhaskar Upadhaya #address-cells = <1>; 2238897f325SBhaskar Upadhaya #size-cells = <0>; 2248897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2258897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 226ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2278897f325SBhaskar Upadhaya status = "disabled"; 2288897f325SBhaskar Upadhaya }; 2298897f325SBhaskar Upadhaya 2308897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2318897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2328897f325SBhaskar Upadhaya #address-cells = <1>; 2338897f325SBhaskar Upadhaya #size-cells = <0>; 2348897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2358897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 236ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2378897f325SBhaskar Upadhaya status = "disabled"; 2388897f325SBhaskar Upadhaya }; 2398897f325SBhaskar Upadhaya 2408897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2418897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2428897f325SBhaskar Upadhaya #address-cells = <1>; 2438897f325SBhaskar Upadhaya #size-cells = <0>; 2448897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2458897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 246ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2478897f325SBhaskar Upadhaya status = "disabled"; 2488897f325SBhaskar Upadhaya }; 2498897f325SBhaskar Upadhaya 2508897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2518897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2528897f325SBhaskar Upadhaya #address-cells = <1>; 2538897f325SBhaskar Upadhaya #size-cells = <0>; 2548897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2558897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 256ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2578897f325SBhaskar Upadhaya status = "disabled"; 2588897f325SBhaskar Upadhaya }; 2598897f325SBhaskar Upadhaya 2608897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2618897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2628897f325SBhaskar Upadhaya #address-cells = <1>; 2638897f325SBhaskar Upadhaya #size-cells = <0>; 2648897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2658897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 266ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2678897f325SBhaskar Upadhaya status = "disabled"; 2688897f325SBhaskar Upadhaya }; 2698897f325SBhaskar Upadhaya 2708897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2718897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2728897f325SBhaskar Upadhaya #address-cells = <1>; 2738897f325SBhaskar Upadhaya #size-cells = <0>; 2748897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2758897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 276ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2778897f325SBhaskar Upadhaya status = "disabled"; 2788897f325SBhaskar Upadhaya }; 2798897f325SBhaskar Upadhaya 280c77fae5bSAshish Kumar fspi: spi@20c0000 { 281c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 282c77fae5bSAshish Kumar #address-cells = <1>; 283c77fae5bSAshish Kumar #size-cells = <0>; 284c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 285c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 286c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 287c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 288c77fae5bSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 289c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 290c77fae5bSAshish Kumar status = "disabled"; 291c77fae5bSAshish Kumar }; 292c77fae5bSAshish Kumar 293491d3a3fSAshish Kumar esdhc: mmc@2140000 { 294491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 295491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 296491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 297491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 298491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 299491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 300491d3a3fSAshish Kumar sdhci,auto-cmd12; 301491d3a3fSAshish Kumar little-endian; 302491d3a3fSAshish Kumar bus-width = <4>; 303491d3a3fSAshish Kumar status = "disabled"; 304491d3a3fSAshish Kumar }; 305491d3a3fSAshish Kumar 306491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 307491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 308491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 309491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 310491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 311491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 312491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 313491d3a3fSAshish Kumar sdhci,auto-cmd12; 314491d3a3fSAshish Kumar broken-cd; 315491d3a3fSAshish Kumar little-endian; 316491d3a3fSAshish Kumar bus-width = <4>; 317491d3a3fSAshish Kumar status = "disabled"; 318491d3a3fSAshish Kumar }; 319491d3a3fSAshish Kumar 3208897f325SBhaskar Upadhaya duart0: serial@21c0500 { 3218897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3228897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 3238897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3248897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3258897f325SBhaskar Upadhaya status = "disabled"; 3268897f325SBhaskar Upadhaya }; 3278897f325SBhaskar Upadhaya 3288897f325SBhaskar Upadhaya duart1: serial@21c0600 { 3298897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3308897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 3318897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3328897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3338897f325SBhaskar Upadhaya status = "disabled"; 3348897f325SBhaskar Upadhaya }; 3358897f325SBhaskar Upadhaya 336f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 337f54f7be5SAlison Wang #dma-cells = <2>; 338869bf854SPeng Ma compatible = "fsl,ls1028a-edma"; 339f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 340f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 341f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 342f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 343f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 344f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 345f54f7be5SAlison Wang dma-channels = <32>; 346f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 347f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 348f54f7be5SAlison Wang <&clockgen 4 1>; 349f54f7be5SAlison Wang }; 350f54f7be5SAlison Wang 3518897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 352f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3538897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 3548897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3558897f325SBhaskar Upadhaya gpio-controller; 3568897f325SBhaskar Upadhaya #gpio-cells = <2>; 3578897f325SBhaskar Upadhaya interrupt-controller; 3588897f325SBhaskar Upadhaya #interrupt-cells = <2>; 359f64697bdSSong Hui little-endian; 3608897f325SBhaskar Upadhaya }; 3618897f325SBhaskar Upadhaya 3628897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 363f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3648897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 3658897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3668897f325SBhaskar Upadhaya gpio-controller; 3678897f325SBhaskar Upadhaya #gpio-cells = <2>; 3688897f325SBhaskar Upadhaya interrupt-controller; 3698897f325SBhaskar Upadhaya #interrupt-cells = <2>; 370f64697bdSSong Hui little-endian; 3718897f325SBhaskar Upadhaya }; 3728897f325SBhaskar Upadhaya 3738897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 374f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3758897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 3768897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3778897f325SBhaskar Upadhaya gpio-controller; 3788897f325SBhaskar Upadhaya #gpio-cells = <2>; 3798897f325SBhaskar Upadhaya interrupt-controller; 3808897f325SBhaskar Upadhaya #interrupt-cells = <2>; 381f64697bdSSong Hui little-endian; 3828897f325SBhaskar Upadhaya }; 3838897f325SBhaskar Upadhaya 384c92f56faSRan Wang usb0: usb@3100000 { 385c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 386c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 387c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 388c92f56faSRan Wang dr_mode = "host"; 389c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 390c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 391c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 392c92f56faSRan Wang }; 393c92f56faSRan Wang 394c92f56faSRan Wang usb1: usb@3110000 { 395c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 396c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 397c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 398c92f56faSRan Wang dr_mode = "host"; 399c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 400c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 401c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 4028897f325SBhaskar Upadhaya }; 4038897f325SBhaskar Upadhaya 4048897f325SBhaskar Upadhaya sata: sata@3200000 { 4058897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 4068897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 4073f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 4088897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 4098897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4108897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 4118897f325SBhaskar Upadhaya status = "disabled"; 4128897f325SBhaskar Upadhaya }; 4138897f325SBhaskar Upadhaya 4148897f325SBhaskar Upadhaya smmu: iommu@5000000 { 4158897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 4168897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 4178897f325SBhaskar Upadhaya #global-interrupts = <8>; 4188897f325SBhaskar Upadhaya #iommu-cells = <1>; 4198897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 4208897f325SBhaskar Upadhaya /* global secure fault */ 4218897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 4228897f325SBhaskar Upadhaya /* combined secure interrupt */ 4238897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 4248897f325SBhaskar Upadhaya /* global non-secure fault */ 4258897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 4268897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 4278897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 4288897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 4298897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 4308897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 4318897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 4328897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 4338897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 4348897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 4358897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 4368897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 4378897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 4388897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 4398897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 4408897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4418897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 4428897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 4438897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 4448897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 4458897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 4468897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 4478897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 4488897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 4498897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4508897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4518897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4528897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4538897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4548897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4558897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 4568897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 4578897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 4588897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 4598897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 4608897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 4618897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 4628897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4638897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 4648897f325SBhaskar Upadhaya }; 465927d7f85SClaudiu Manoil 4661d0becabSHoria Geantă crypto: crypto@8000000 { 4671d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 4681d0becabSHoria Geantă fsl,sec-era = <10>; 4691d0becabSHoria Geantă #address-cells = <1>; 4701d0becabSHoria Geantă #size-cells = <1>; 4711d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 4721d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 4731d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4741d0becabSHoria Geantă dma-coherent; 4751d0becabSHoria Geantă 4761d0becabSHoria Geantă sec_jr0: jr@10000 { 4771d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4781d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4791d0becabSHoria Geantă reg = <0x10000 0x10000>; 4801d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4811d0becabSHoria Geantă }; 4821d0becabSHoria Geantă 4831d0becabSHoria Geantă sec_jr1: jr@20000 { 4841d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4851d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4861d0becabSHoria Geantă reg = <0x20000 0x10000>; 4871d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4881d0becabSHoria Geantă }; 4891d0becabSHoria Geantă 4901d0becabSHoria Geantă sec_jr2: jr@30000 { 4911d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4921d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4931d0becabSHoria Geantă reg = <0x30000 0x10000>; 4941d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4951d0becabSHoria Geantă }; 4961d0becabSHoria Geantă 4971d0becabSHoria Geantă sec_jr3: jr@40000 { 4981d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4991d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5001d0becabSHoria Geantă reg = <0x40000 0x10000>; 5011d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5021d0becabSHoria Geantă }; 5031d0becabSHoria Geantă }; 5041d0becabSHoria Geantă 5057802f88dSPeng Ma qdma: dma-controller@8380000 { 5067802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 5077802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 5087802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 5097802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 5107802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 5117802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 5127802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 5137802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 5147802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 5157802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 5167802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 5177802f88dSPeng Ma dma-channels = <8>; 5187802f88dSPeng Ma block-number = <1>; 5197802f88dSPeng Ma block-offset = <0x10000>; 5207802f88dSPeng Ma fsl,dma-queues = <2>; 5217802f88dSPeng Ma status-sizes = <64>; 5227802f88dSPeng Ma queue-sizes = <64 64>; 5237802f88dSPeng Ma }; 5247802f88dSPeng Ma 52557aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 52657aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 52757aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 52857aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 52957aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 53057aa1bc7SChuanhua Han }; 53157aa1bc7SChuanhua Han 53257aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 53357aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 53457aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 53557aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 53657aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 53757aa1bc7SChuanhua Han }; 53857aa1bc7SChuanhua Han 539f54f7be5SAlison Wang sai1: audio-controller@f100000 { 540f54f7be5SAlison Wang #sound-dai-cells = <0>; 541f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 542f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 543f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 544f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 545f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 546f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 547f54f7be5SAlison Wang dma-names = "tx", "rx"; 548f54f7be5SAlison Wang dmas = <&edma0 1 4>, 549f54f7be5SAlison Wang <&edma0 1 3>; 5509c015e13SMichael Walle fsl,sai-asynchronous; 551f54f7be5SAlison Wang status = "disabled"; 552f54f7be5SAlison Wang }; 553f54f7be5SAlison Wang 554f54f7be5SAlison Wang sai2: audio-controller@f110000 { 555f54f7be5SAlison Wang #sound-dai-cells = <0>; 556f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 557f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 558f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 559f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 560f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 561f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 562f54f7be5SAlison Wang dma-names = "tx", "rx"; 563f54f7be5SAlison Wang dmas = <&edma0 1 6>, 564f54f7be5SAlison Wang <&edma0 1 5>; 5659c015e13SMichael Walle fsl,sai-asynchronous; 566f54f7be5SAlison Wang status = "disabled"; 567f54f7be5SAlison Wang }; 568f54f7be5SAlison Wang 569434f9cc1SMichael Walle sai3: audio-controller@f120000 { 570434f9cc1SMichael Walle #sound-dai-cells = <0>; 571434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 572434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 573434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 574434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 575434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 576434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 577434f9cc1SMichael Walle dma-names = "tx", "rx"; 578434f9cc1SMichael Walle dmas = <&edma0 1 8>, 579434f9cc1SMichael Walle <&edma0 1 7>; 5809c015e13SMichael Walle fsl,sai-asynchronous; 581f54f7be5SAlison Wang status = "disabled"; 582f54f7be5SAlison Wang }; 583f54f7be5SAlison Wang 584f54f7be5SAlison Wang sai4: audio-controller@f130000 { 585f54f7be5SAlison Wang #sound-dai-cells = <0>; 586f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 587f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 588f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 589f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 590f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 591f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 592f54f7be5SAlison Wang dma-names = "tx", "rx"; 593f54f7be5SAlison Wang dmas = <&edma0 1 10>, 594f54f7be5SAlison Wang <&edma0 1 9>; 5959c015e13SMichael Walle fsl,sai-asynchronous; 596f54f7be5SAlison Wang status = "disabled"; 597f54f7be5SAlison Wang }; 598f54f7be5SAlison Wang 599434f9cc1SMichael Walle sai5: audio-controller@f140000 { 600434f9cc1SMichael Walle #sound-dai-cells = <0>; 601434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 602434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 603434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 604434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 605434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 606434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 607434f9cc1SMichael Walle dma-names = "tx", "rx"; 608434f9cc1SMichael Walle dmas = <&edma0 1 12>, 609434f9cc1SMichael Walle <&edma0 1 11>; 6109c015e13SMichael Walle fsl,sai-asynchronous; 611434f9cc1SMichael Walle status = "disabled"; 612434f9cc1SMichael Walle }; 613434f9cc1SMichael Walle 614434f9cc1SMichael Walle sai6: audio-controller@f150000 { 615434f9cc1SMichael Walle #sound-dai-cells = <0>; 616434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 617434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 618434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 619434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 620434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 621434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 622434f9cc1SMichael Walle dma-names = "tx", "rx"; 623434f9cc1SMichael Walle dmas = <&edma0 1 14>, 624434f9cc1SMichael Walle <&edma0 1 13>; 6259c015e13SMichael Walle fsl,sai-asynchronous; 6268897f325SBhaskar Upadhaya status = "disabled"; 6278897f325SBhaskar Upadhaya }; 6288897f325SBhaskar Upadhaya 6290b680963SFabio Estevam tmu: tmu@1f80000 { 630571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 631571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 632571cebfeSYuantian Tang interrupts = <0 23 0x4>; 633571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 634571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 635571cebfeSYuantian Tang 0x00000001 0x0000002b 636571cebfeSYuantian Tang 0x00000002 0x00000031 637571cebfeSYuantian Tang 0x00000003 0x00000038 638571cebfeSYuantian Tang 0x00000004 0x0000003f 639571cebfeSYuantian Tang 0x00000005 0x00000045 640571cebfeSYuantian Tang 0x00000006 0x0000004c 641571cebfeSYuantian Tang 0x00000007 0x00000053 642571cebfeSYuantian Tang 0x00000008 0x00000059 643571cebfeSYuantian Tang 0x00000009 0x00000060 644571cebfeSYuantian Tang 0x0000000a 0x00000066 645571cebfeSYuantian Tang 0x0000000b 0x0000006d 646571cebfeSYuantian Tang 647571cebfeSYuantian Tang 0x00010000 0x0000001c 648571cebfeSYuantian Tang 0x00010001 0x00000024 649571cebfeSYuantian Tang 0x00010002 0x0000002c 650571cebfeSYuantian Tang 0x00010003 0x00000035 651571cebfeSYuantian Tang 0x00010004 0x0000003d 652571cebfeSYuantian Tang 0x00010005 0x00000045 653571cebfeSYuantian Tang 0x00010006 0x0000004d 654961f8209SMichael Walle 0x00010007 0x00000055 655571cebfeSYuantian Tang 0x00010008 0x0000005e 656571cebfeSYuantian Tang 0x00010009 0x00000066 657571cebfeSYuantian Tang 0x0001000a 0x0000006e 658571cebfeSYuantian Tang 659571cebfeSYuantian Tang 0x00020000 0x00000018 660571cebfeSYuantian Tang 0x00020001 0x00000022 661571cebfeSYuantian Tang 0x00020002 0x0000002d 662571cebfeSYuantian Tang 0x00020003 0x00000038 663571cebfeSYuantian Tang 0x00020004 0x00000043 664571cebfeSYuantian Tang 0x00020005 0x0000004d 665571cebfeSYuantian Tang 0x00020006 0x00000058 666571cebfeSYuantian Tang 0x00020007 0x00000063 667571cebfeSYuantian Tang 0x00020008 0x0000006e 668571cebfeSYuantian Tang 669571cebfeSYuantian Tang 0x00030000 0x00000010 670571cebfeSYuantian Tang 0x00030001 0x0000001c 671571cebfeSYuantian Tang 0x00030002 0x00000029 672571cebfeSYuantian Tang 0x00030003 0x00000036 673571cebfeSYuantian Tang 0x00030004 0x00000042 674571cebfeSYuantian Tang 0x00030005 0x0000004f 675571cebfeSYuantian Tang 0x00030006 0x0000005b 676571cebfeSYuantian Tang 0x00030007 0x00000068>; 677571cebfeSYuantian Tang little-endian; 678571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 679571cebfeSYuantian Tang }; 680571cebfeSYuantian Tang 6818897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 6828897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 6838897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 6848897f325SBhaskar Upadhaya #address-cells = <3>; 6858897f325SBhaskar Upadhaya #size-cells = <2>; 6868897f325SBhaskar Upadhaya #interrupt-cells = <1>; 6878897f325SBhaskar Upadhaya msi-parent = <&its>; 6888897f325SBhaskar Upadhaya device_type = "pci"; 6898897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 6908897f325SBhaskar Upadhaya dma-coherent; 6918897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 6928897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 6938897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 6948897f325SBhaskar Upadhaya ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 6958897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 6968897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 6978897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 6988897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 6998897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 7008897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 7018897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 7028897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 7038897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 7048897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 7058897f325SBhaskar Upadhaya 7068897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 7078897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 7088897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 7098897f325SBhaskar Upadhaya }; 7108897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 7118897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 7128897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 7138897f325SBhaskar Upadhaya }; 7148488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 7158488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 7168488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 7178488d8e9SClaudiu Manoil #address-cells = <1>; 7188488d8e9SClaudiu Manoil #size-cells = <0>; 7198488d8e9SClaudiu Manoil }; 72049401003SY.b. Lu ethernet@0,4 { 72149401003SY.b. Lu compatible = "fsl,enetc-ptp"; 72249401003SY.b. Lu reg = <0x000400 0 0 0 0>; 72349401003SY.b. Lu clocks = <&clockgen 4 0>; 72449401003SY.b. Lu little-endian; 725ab84bad5SYangbo Lu fsl,extts-fifo; 72649401003SY.b. Lu }; 7278897f325SBhaskar Upadhaya }; 7288897f325SBhaskar Upadhaya }; 7297f538f19SWen He 7307f538f19SWen He malidp0: display@f080000 { 7317f538f19SWen He compatible = "arm,mali-dp500"; 7327f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 7337f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 7347f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 7357f538f19SWen He interrupt-names = "DE", "SE"; 73691035cb0SWen He clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 73713782597SWen He <&clockgen 2 2>; 7387f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 7397f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 7403a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 7417f538f19SWen He 7427f538f19SWen He port { 7437f538f19SWen He dp0_out: endpoint { 7447f538f19SWen He 7457f538f19SWen He }; 7467f538f19SWen He }; 7477f538f19SWen He }; 7488897f325SBhaskar Upadhaya}; 749