18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 5f7d48ffcSWasim Khan * Copyright 2018-2020 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 1199314eb1SMichael Walle#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 138897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 148897f325SBhaskar Upadhaya 158897f325SBhaskar Upadhaya/ { 168897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 178897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 188897f325SBhaskar Upadhaya #address-cells = <2>; 198897f325SBhaskar Upadhaya #size-cells = <2>; 208897f325SBhaskar Upadhaya 218897f325SBhaskar Upadhaya cpus { 228897f325SBhaskar Upadhaya #address-cells = <1>; 238897f325SBhaskar Upadhaya #size-cells = <0>; 248897f325SBhaskar Upadhaya 258897f325SBhaskar Upadhaya cpu0: cpu@0 { 268897f325SBhaskar Upadhaya device_type = "cpu"; 278897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 288897f325SBhaskar Upadhaya reg = <0x0>; 298897f325SBhaskar Upadhaya enable-method = "psci"; 3099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 318897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 33571cebfeSYuantian Tang #cooling-cells = <2>; 348897f325SBhaskar Upadhaya }; 358897f325SBhaskar Upadhaya 368897f325SBhaskar Upadhaya cpu1: cpu@1 { 378897f325SBhaskar Upadhaya device_type = "cpu"; 388897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 398897f325SBhaskar Upadhaya reg = <0x1>; 408897f325SBhaskar Upadhaya enable-method = "psci"; 4199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_CMUX 0>; 428897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4353f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 44571cebfeSYuantian Tang #cooling-cells = <2>; 458897f325SBhaskar Upadhaya }; 468897f325SBhaskar Upadhaya 478897f325SBhaskar Upadhaya l2: l2-cache { 488897f325SBhaskar Upadhaya compatible = "cache"; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya }; 518897f325SBhaskar Upadhaya 528897f325SBhaskar Upadhaya idle-states { 538897f325SBhaskar Upadhaya /* 548897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 558897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 568897f325SBhaskar Upadhaya */ 579b631649SLinus Walleij entry-method = "psci"; 588897f325SBhaskar Upadhaya 5953f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 608897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6153f2ac9dSRan Wang idle-state-name = "PW20"; 6253f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6353f2ac9dSRan Wang entry-latency-us = <2000>; 6453f2ac9dSRan Wang exit-latency-us = <2000>; 6553f2ac9dSRan Wang min-residency-us = <6000>; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya }; 688897f325SBhaskar Upadhaya 697e71b854SVladimir Oltean sysclk: sysclk { 708897f325SBhaskar Upadhaya compatible = "fixed-clock"; 718897f325SBhaskar Upadhaya #clock-cells = <0>; 728897f325SBhaskar Upadhaya clock-frequency = <100000000>; 738897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 748897f325SBhaskar Upadhaya }; 758897f325SBhaskar Upadhaya 7681f36887SWen He osc_27m: clock-osc-27m { 777f538f19SWen He compatible = "fixed-clock"; 787f538f19SWen He #clock-cells = <0>; 797f538f19SWen He clock-frequency = <27000000>; 8081f36887SWen He clock-output-names = "phy_27m"; 8181f36887SWen He }; 8281f36887SWen He 83f90931aeSMichael Walle firmware { 84c67b761aSSahil Malhotra optee: optee { 85f90931aeSMichael Walle compatible = "linaro,optee-tz"; 86f90931aeSMichael Walle method = "smc"; 87f90931aeSMichael Walle status = "disabled"; 88f90931aeSMichael Walle }; 89f90931aeSMichael Walle }; 90f90931aeSMichael Walle 918897f325SBhaskar Upadhaya reboot { 928897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 933f0fb37bSMichael Walle regmap = <&rst>; 941653e3d4SMichael Walle offset = <0>; 958897f325SBhaskar Upadhaya mask = <0x02>; 968897f325SBhaskar Upadhaya }; 978897f325SBhaskar Upadhaya 988897f325SBhaskar Upadhaya timer { 998897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 1008897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 1018897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1028897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1038897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1048897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1058897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1068897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1078897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1088897f325SBhaskar Upadhaya }; 1098897f325SBhaskar Upadhaya 110b9eb314aSAlison Wang pmu { 111b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 112b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 113b9eb314aSAlison Wang }; 114b9eb314aSAlison Wang 1158897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1168897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1178897f325SBhaskar Upadhaya #address-cells = <2>; 1188897f325SBhaskar Upadhaya #size-cells = <2>; 1198897f325SBhaskar Upadhaya ranges; 1208897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1218897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1228897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1238897f325SBhaskar Upadhaya interrupt-controller; 1248897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1258897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1268897f325SBhaskar Upadhaya its: gic-its@6020000 { 1278897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1288897f325SBhaskar Upadhaya msi-controller; 1298897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1308897f325SBhaskar Upadhaya }; 1318897f325SBhaskar Upadhaya }; 1328897f325SBhaskar Upadhaya 13368e36a42SFabio Estevam thermal-zones { 1343269c178SYuantian Tang ddr-controller { 13568e36a42SFabio Estevam polling-delay-passive = <1000>; 13668e36a42SFabio Estevam polling-delay = <5000>; 13768e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 13868e36a42SFabio Estevam 13968e36a42SFabio Estevam trips { 1403269c178SYuantian Tang ddr-ctrler-alert { 1413269c178SYuantian Tang temperature = <85000>; 1423269c178SYuantian Tang hysteresis = <2000>; 1433269c178SYuantian Tang type = "passive"; 1443269c178SYuantian Tang }; 1453269c178SYuantian Tang 1463269c178SYuantian Tang ddr-ctrler-crit { 1473269c178SYuantian Tang temperature = <95000>; 1483269c178SYuantian Tang hysteresis = <2000>; 1493269c178SYuantian Tang type = "critical"; 1503269c178SYuantian Tang }; 1513269c178SYuantian Tang }; 1523269c178SYuantian Tang }; 1533269c178SYuantian Tang 1543269c178SYuantian Tang core-cluster { 1553269c178SYuantian Tang polling-delay-passive = <1000>; 1563269c178SYuantian Tang polling-delay = <5000>; 1573269c178SYuantian Tang thermal-sensors = <&tmu 1>; 1583269c178SYuantian Tang 1593269c178SYuantian Tang trips { 16068e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 16168e36a42SFabio Estevam temperature = <85000>; 16268e36a42SFabio Estevam hysteresis = <2000>; 16368e36a42SFabio Estevam type = "passive"; 16468e36a42SFabio Estevam }; 16568e36a42SFabio Estevam 16668e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 16768e36a42SFabio Estevam temperature = <95000>; 16868e36a42SFabio Estevam hysteresis = <2000>; 16968e36a42SFabio Estevam type = "critical"; 17068e36a42SFabio Estevam }; 17168e36a42SFabio Estevam }; 17268e36a42SFabio Estevam 17368e36a42SFabio Estevam cooling-maps { 17468e36a42SFabio Estevam map0 { 17568e36a42SFabio Estevam trip = <&core_cluster_alert>; 17668e36a42SFabio Estevam cooling-device = 17768e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 17868e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 17968e36a42SFabio Estevam }; 18068e36a42SFabio Estevam }; 18168e36a42SFabio Estevam }; 18268e36a42SFabio Estevam }; 18368e36a42SFabio Estevam 1848897f325SBhaskar Upadhaya soc: soc { 1858897f325SBhaskar Upadhaya compatible = "simple-bus"; 1868897f325SBhaskar Upadhaya #address-cells = <2>; 1878897f325SBhaskar Upadhaya #size-cells = <2>; 1888897f325SBhaskar Upadhaya ranges; 1898897f325SBhaskar Upadhaya 1908897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1918897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1928897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 193dabea675SMichael Walle interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 194dabea675SMichael Walle little-endian; 1958897f325SBhaskar Upadhaya }; 1968897f325SBhaskar Upadhaya 1978897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 19869c910d3SMichael Walle #address-cells = <1>; 19969c910d3SMichael Walle #size-cells = <1>; 20069c910d3SMichael Walle compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 2018897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 20269c910d3SMichael Walle ranges = <0x0 0x0 0x1e00000 0x10000>; 20333eae7fbSYinbo Zhu little-endian; 20469c910d3SMichael Walle 20569c910d3SMichael Walle fspi_clk: clock-controller@900 { 20669c910d3SMichael Walle compatible = "fsl,ls1028a-flexspi-clk"; 20769c910d3SMichael Walle reg = <0x900 0x4>; 20869c910d3SMichael Walle #clock-cells = <0>; 20969c910d3SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 21069c910d3SMichael Walle clock-output-names = "fspi_clk"; 21169c910d3SMichael Walle }; 2128897f325SBhaskar Upadhaya }; 2138897f325SBhaskar Upadhaya 2143f0fb37bSMichael Walle rst: syscon@1e60000 { 2153f0fb37bSMichael Walle compatible = "syscon"; 2163f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 2173f0fb37bSMichael Walle little-endian; 2183f0fb37bSMichael Walle }; 2193f0fb37bSMichael Walle 2208897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 2218897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 2228897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 2238897f325SBhaskar Upadhaya big-endian; 2248897f325SBhaskar Upadhaya }; 2258897f325SBhaskar Upadhaya 2268897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 2278897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 2288897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 2298897f325SBhaskar Upadhaya #clock-cells = <2>; 2308897f325SBhaskar Upadhaya clocks = <&sysclk>; 2318897f325SBhaskar Upadhaya }; 2328897f325SBhaskar Upadhaya 2338897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2348897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2358897f325SBhaskar Upadhaya #address-cells = <1>; 2368897f325SBhaskar Upadhaya #size-cells = <0>; 2378897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2388897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 23999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 24099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2418897f325SBhaskar Upadhaya status = "disabled"; 2428897f325SBhaskar Upadhaya }; 2438897f325SBhaskar Upadhaya 2448897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2458897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2468897f325SBhaskar Upadhaya #address-cells = <1>; 2478897f325SBhaskar Upadhaya #size-cells = <0>; 2488897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2498897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 25099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 25199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2528897f325SBhaskar Upadhaya status = "disabled"; 2538897f325SBhaskar Upadhaya }; 2548897f325SBhaskar Upadhaya 2558897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2568897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2578897f325SBhaskar Upadhaya #address-cells = <1>; 2588897f325SBhaskar Upadhaya #size-cells = <0>; 2598897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2608897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 26199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 26299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2638897f325SBhaskar Upadhaya status = "disabled"; 2648897f325SBhaskar Upadhaya }; 2658897f325SBhaskar Upadhaya 2668897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2678897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2688897f325SBhaskar Upadhaya #address-cells = <1>; 2698897f325SBhaskar Upadhaya #size-cells = <0>; 2708897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2718897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 27299314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 27399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2748897f325SBhaskar Upadhaya status = "disabled"; 2758897f325SBhaskar Upadhaya }; 2768897f325SBhaskar Upadhaya 2778897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2788897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2798897f325SBhaskar Upadhaya #address-cells = <1>; 2808897f325SBhaskar Upadhaya #size-cells = <0>; 2818897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2828897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 28399314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 28499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2858897f325SBhaskar Upadhaya status = "disabled"; 2868897f325SBhaskar Upadhaya }; 2878897f325SBhaskar Upadhaya 2888897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2898897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2908897f325SBhaskar Upadhaya #address-cells = <1>; 2918897f325SBhaskar Upadhaya #size-cells = <0>; 2928897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2938897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 29499314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 29599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 2968897f325SBhaskar Upadhaya status = "disabled"; 2978897f325SBhaskar Upadhaya }; 2988897f325SBhaskar Upadhaya 2998897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 3008897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3018897f325SBhaskar Upadhaya #address-cells = <1>; 3028897f325SBhaskar Upadhaya #size-cells = <0>; 3038897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 3048897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 30599314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 30699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3078897f325SBhaskar Upadhaya status = "disabled"; 3088897f325SBhaskar Upadhaya }; 3098897f325SBhaskar Upadhaya 3108897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 3118897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 3128897f325SBhaskar Upadhaya #address-cells = <1>; 3138897f325SBhaskar Upadhaya #size-cells = <0>; 3148897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 3158897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 31699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 31799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(4)>; 3188897f325SBhaskar Upadhaya status = "disabled"; 3198897f325SBhaskar Upadhaya }; 3208897f325SBhaskar Upadhaya 321c77fae5bSAshish Kumar fspi: spi@20c0000 { 322c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 323c77fae5bSAshish Kumar #address-cells = <1>; 324c77fae5bSAshish Kumar #size-cells = <0>; 325c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 326c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 327c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 328c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 32969c910d3SMichael Walle clocks = <&fspi_clk>, <&fspi_clk>; 330c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 331c77fae5bSAshish Kumar status = "disabled"; 332c77fae5bSAshish Kumar }; 333c77fae5bSAshish Kumar 334c2d35adaSMichael Walle dspi0: spi@2100000 { 335c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 336c2d35adaSMichael Walle #address-cells = <1>; 337c2d35adaSMichael Walle #size-cells = <0>; 338c2d35adaSMichael Walle reg = <0x0 0x2100000 0x0 0x10000>; 339c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 340c2d35adaSMichael Walle clock-names = "dspi"; 34199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 34299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 343dd12fa69SVladimir Oltean dmas = <&edma0 0 62>, <&edma0 0 60>; 344dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 345c2d35adaSMichael Walle spi-num-chipselects = <4>; 346c2d35adaSMichael Walle little-endian; 347c2d35adaSMichael Walle status = "disabled"; 348c2d35adaSMichael Walle }; 349c2d35adaSMichael Walle 350c2d35adaSMichael Walle dspi1: spi@2110000 { 351c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 352c2d35adaSMichael Walle #address-cells = <1>; 353c2d35adaSMichael Walle #size-cells = <0>; 354c2d35adaSMichael Walle reg = <0x0 0x2110000 0x0 0x10000>; 355c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 356c2d35adaSMichael Walle clock-names = "dspi"; 35799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 35899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 359dd12fa69SVladimir Oltean dmas = <&edma0 0 58>, <&edma0 0 56>; 360dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 361c2d35adaSMichael Walle spi-num-chipselects = <4>; 362c2d35adaSMichael Walle little-endian; 363c2d35adaSMichael Walle status = "disabled"; 364c2d35adaSMichael Walle }; 365c2d35adaSMichael Walle 366c2d35adaSMichael Walle dspi2: spi@2120000 { 367c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 368c2d35adaSMichael Walle #address-cells = <1>; 369c2d35adaSMichael Walle #size-cells = <0>; 370c2d35adaSMichael Walle reg = <0x0 0x2120000 0x0 0x10000>; 371c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 372c2d35adaSMichael Walle clock-names = "dspi"; 37399314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 37499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 375dd12fa69SVladimir Oltean dmas = <&edma0 0 54>, <&edma0 0 2>; 376dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 377c2d35adaSMichael Walle spi-num-chipselects = <3>; 378c2d35adaSMichael Walle little-endian; 379c2d35adaSMichael Walle status = "disabled"; 380c2d35adaSMichael Walle }; 381c2d35adaSMichael Walle 382491d3a3fSAshish Kumar esdhc: mmc@2140000 { 383491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 384491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 385491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 386491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 38799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 388491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 389491d3a3fSAshish Kumar sdhci,auto-cmd12; 390491d3a3fSAshish Kumar little-endian; 391491d3a3fSAshish Kumar bus-width = <4>; 392491d3a3fSAshish Kumar status = "disabled"; 393491d3a3fSAshish Kumar }; 394491d3a3fSAshish Kumar 395491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 396491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 397491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 398491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 399491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 40099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 401491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 402491d3a3fSAshish Kumar sdhci,auto-cmd12; 403491d3a3fSAshish Kumar broken-cd; 404491d3a3fSAshish Kumar little-endian; 405491d3a3fSAshish Kumar bus-width = <4>; 406491d3a3fSAshish Kumar status = "disabled"; 407491d3a3fSAshish Kumar }; 408491d3a3fSAshish Kumar 40904fa4f03SMichael Walle can0: can@2180000 { 410c9e5ef8cSKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 41104fa4f03SMichael Walle reg = <0x0 0x2180000 0x0 0x10000>; 41204fa4f03SMichael Walle interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 413c9e5ef8cSKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 414c9e5ef8cSKuldeep Singh QORIQ_CLK_PLL_DIV(2)>, 415c9e5ef8cSKuldeep Singh <&clockgen QORIQ_CLK_PLATFORM_PLL 41699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 41704fa4f03SMichael Walle clock-names = "ipg", "per"; 41804fa4f03SMichael Walle status = "disabled"; 41904fa4f03SMichael Walle }; 42004fa4f03SMichael Walle 42104fa4f03SMichael Walle can1: can@2190000 { 422c9e5ef8cSKuldeep Singh compatible = "fsl,lx2160ar1-flexcan"; 42304fa4f03SMichael Walle reg = <0x0 0x2190000 0x0 0x10000>; 42404fa4f03SMichael Walle interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 425c9e5ef8cSKuldeep Singh clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 426c9e5ef8cSKuldeep Singh QORIQ_CLK_PLL_DIV(2)>, 427c9e5ef8cSKuldeep Singh <&clockgen QORIQ_CLK_PLATFORM_PLL 42899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 42904fa4f03SMichael Walle clock-names = "ipg", "per"; 43004fa4f03SMichael Walle status = "disabled"; 43104fa4f03SMichael Walle }; 43204fa4f03SMichael Walle 4338897f325SBhaskar Upadhaya duart0: serial@21c0500 { 4348897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 4358897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 4368897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 43799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 43899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4398897f325SBhaskar Upadhaya status = "disabled"; 4408897f325SBhaskar Upadhaya }; 4418897f325SBhaskar Upadhaya 4428897f325SBhaskar Upadhaya duart1: serial@21c0600 { 4438897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 4448897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 4458897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 44699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 44799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4488897f325SBhaskar Upadhaya status = "disabled"; 4498897f325SBhaskar Upadhaya }; 4508897f325SBhaskar Upadhaya 4512607d724SMichael Walle 4522607d724SMichael Walle lpuart0: serial@2260000 { 4532607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4542607d724SMichael Walle reg = <0x0 0x2260000 0x0 0x1000>; 4552607d724SMichael Walle interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 45699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 45799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4582607d724SMichael Walle clock-names = "ipg"; 4592607d724SMichael Walle dma-names = "rx","tx"; 4602607d724SMichael Walle dmas = <&edma0 1 32>, 4612607d724SMichael Walle <&edma0 1 33>; 4622607d724SMichael Walle status = "disabled"; 4632607d724SMichael Walle }; 4642607d724SMichael Walle 4652607d724SMichael Walle lpuart1: serial@2270000 { 4662607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4672607d724SMichael Walle reg = <0x0 0x2270000 0x0 0x1000>; 4682607d724SMichael Walle interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 46999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 47099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4712607d724SMichael Walle clock-names = "ipg"; 4722607d724SMichael Walle dma-names = "rx","tx"; 4732607d724SMichael Walle dmas = <&edma0 1 30>, 4742607d724SMichael Walle <&edma0 1 31>; 4752607d724SMichael Walle status = "disabled"; 4762607d724SMichael Walle }; 4772607d724SMichael Walle 4782607d724SMichael Walle lpuart2: serial@2280000 { 4792607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4802607d724SMichael Walle reg = <0x0 0x2280000 0x0 0x1000>; 4812607d724SMichael Walle interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 48299314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 48399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4842607d724SMichael Walle clock-names = "ipg"; 4852607d724SMichael Walle dma-names = "rx","tx"; 4862607d724SMichael Walle dmas = <&edma0 1 28>, 4872607d724SMichael Walle <&edma0 1 29>; 4882607d724SMichael Walle status = "disabled"; 4892607d724SMichael Walle }; 4902607d724SMichael Walle 4912607d724SMichael Walle lpuart3: serial@2290000 { 4922607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4932607d724SMichael Walle reg = <0x0 0x2290000 0x0 0x1000>; 4942607d724SMichael Walle interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 49599314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 49699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 4972607d724SMichael Walle clock-names = "ipg"; 4982607d724SMichael Walle dma-names = "rx","tx"; 4992607d724SMichael Walle dmas = <&edma0 1 26>, 5002607d724SMichael Walle <&edma0 1 27>; 5012607d724SMichael Walle status = "disabled"; 5022607d724SMichael Walle }; 5032607d724SMichael Walle 5042607d724SMichael Walle lpuart4: serial@22a0000 { 5052607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5062607d724SMichael Walle reg = <0x0 0x22a0000 0x0 0x1000>; 5072607d724SMichael Walle interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 50899314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 50999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5102607d724SMichael Walle clock-names = "ipg"; 5112607d724SMichael Walle dma-names = "rx","tx"; 5122607d724SMichael Walle dmas = <&edma0 1 24>, 5132607d724SMichael Walle <&edma0 1 25>; 5142607d724SMichael Walle status = "disabled"; 5152607d724SMichael Walle }; 5162607d724SMichael Walle 5172607d724SMichael Walle lpuart5: serial@22b0000 { 5182607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 5192607d724SMichael Walle reg = <0x0 0x22b0000 0x0 0x1000>; 5202607d724SMichael Walle interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 52199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 52299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 5232607d724SMichael Walle clock-names = "ipg"; 5242607d724SMichael Walle dma-names = "rx","tx"; 5252607d724SMichael Walle dmas = <&edma0 1 22>, 5262607d724SMichael Walle <&edma0 1 23>; 5272607d724SMichael Walle status = "disabled"; 5282607d724SMichael Walle }; 5292607d724SMichael Walle 530f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 531f54f7be5SAlison Wang #dma-cells = <2>; 532e0d7856eSMichael Walle compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 533f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 534f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 535f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 536f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 537f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 538f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 539f54f7be5SAlison Wang dma-channels = <32>; 540f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 54199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 54299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 54399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 54499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 545f54f7be5SAlison Wang }; 546f54f7be5SAlison Wang 5478897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 548f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5498897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 5508897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5518897f325SBhaskar Upadhaya gpio-controller; 5528897f325SBhaskar Upadhaya #gpio-cells = <2>; 5538897f325SBhaskar Upadhaya interrupt-controller; 5548897f325SBhaskar Upadhaya #interrupt-cells = <2>; 555f64697bdSSong Hui little-endian; 5568897f325SBhaskar Upadhaya }; 5578897f325SBhaskar Upadhaya 5588897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 559f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5608897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 5618897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5628897f325SBhaskar Upadhaya gpio-controller; 5638897f325SBhaskar Upadhaya #gpio-cells = <2>; 5648897f325SBhaskar Upadhaya interrupt-controller; 5658897f325SBhaskar Upadhaya #interrupt-cells = <2>; 566f64697bdSSong Hui little-endian; 5678897f325SBhaskar Upadhaya }; 5688897f325SBhaskar Upadhaya 5698897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 570f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5718897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 5728897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 5738897f325SBhaskar Upadhaya gpio-controller; 5748897f325SBhaskar Upadhaya #gpio-cells = <2>; 5758897f325SBhaskar Upadhaya interrupt-controller; 5768897f325SBhaskar Upadhaya #interrupt-cells = <2>; 577f64697bdSSong Hui little-endian; 5788897f325SBhaskar Upadhaya }; 5798897f325SBhaskar Upadhaya 580c92f56faSRan Wang usb0: usb@3100000 { 581c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 582c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 583c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 584c92f56faSRan Wang dr_mode = "host"; 585c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 586c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 587c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 58870293beaSMichael Walle status = "disabled"; 589c92f56faSRan Wang }; 590c92f56faSRan Wang 591c92f56faSRan Wang usb1: usb@3110000 { 592c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 593c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 594c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 595c92f56faSRan Wang dr_mode = "host"; 596c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 597c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 598c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 59970293beaSMichael Walle status = "disabled"; 6008897f325SBhaskar Upadhaya }; 6018897f325SBhaskar Upadhaya 6028897f325SBhaskar Upadhaya sata: sata@3200000 { 6038897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 6048897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 6053f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 6068897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 6078897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 60899314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 60999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 6108897f325SBhaskar Upadhaya status = "disabled"; 6118897f325SBhaskar Upadhaya }; 6128897f325SBhaskar Upadhaya 613f7d48ffcSWasim Khan pcie1: pcie@3400000 { 614f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 615ce87d936SZhen Lei reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 616ce87d936SZhen Lei <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 617f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 618f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 619f6ff3f6dSXiaowei Bao <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 620f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 621f6ff3f6dSXiaowei Bao #address-cells = <3>; 622f6ff3f6dSXiaowei Bao #size-cells = <2>; 623f6ff3f6dSXiaowei Bao device_type = "pci"; 624f6ff3f6dSXiaowei Bao dma-coherent; 625f6ff3f6dSXiaowei Bao num-viewport = <8>; 626f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 627f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 628f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 629f6ff3f6dSXiaowei Bao msi-parent = <&its>; 630f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 631f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 632f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 633f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 634f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 635f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 636f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 637f6ff3f6dSXiaowei Bao status = "disabled"; 638f6ff3f6dSXiaowei Bao }; 639f6ff3f6dSXiaowei Bao 640f7d48ffcSWasim Khan pcie2: pcie@3500000 { 641f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 642ce87d936SZhen Lei reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 643ce87d936SZhen Lei <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 644f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 645f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 646f6ff3f6dSXiaowei Bao <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 647f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 648f6ff3f6dSXiaowei Bao #address-cells = <3>; 649f6ff3f6dSXiaowei Bao #size-cells = <2>; 650f6ff3f6dSXiaowei Bao device_type = "pci"; 651f6ff3f6dSXiaowei Bao dma-coherent; 652f6ff3f6dSXiaowei Bao num-viewport = <8>; 653f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 654f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 655f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 656f6ff3f6dSXiaowei Bao msi-parent = <&its>; 657f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 658f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 659f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 660f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 661f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 662f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 663f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 664f6ff3f6dSXiaowei Bao status = "disabled"; 665f6ff3f6dSXiaowei Bao }; 666f6ff3f6dSXiaowei Bao 6678897f325SBhaskar Upadhaya smmu: iommu@5000000 { 6688897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 6698897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 6708897f325SBhaskar Upadhaya #global-interrupts = <8>; 6718897f325SBhaskar Upadhaya #iommu-cells = <1>; 6728897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 6738897f325SBhaskar Upadhaya /* global secure fault */ 6748897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 6758897f325SBhaskar Upadhaya /* combined secure interrupt */ 6768897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 6778897f325SBhaskar Upadhaya /* global non-secure fault */ 6788897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 6798897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 6808897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 6818897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 6828897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 6838897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 6848897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 6858897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6868897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6878897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 6888897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 6898897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 6908897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 6918897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 6928897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 6938897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 6948897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 6958897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 6968897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 6978897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 6988897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 6998897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 7008897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 7018897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 7028897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7038897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7048897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7058897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7068897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7078897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7088897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 7098897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 7108897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 7118897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 7128897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 7138897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 7148897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 7158897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 7168897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 7178897f325SBhaskar Upadhaya }; 718927d7f85SClaudiu Manoil 7191d0becabSHoria Geantă crypto: crypto@8000000 { 7201d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 7211d0becabSHoria Geantă fsl,sec-era = <10>; 7221d0becabSHoria Geantă #address-cells = <1>; 7231d0becabSHoria Geantă #size-cells = <1>; 7241d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 7251d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 7261d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 7271d0becabSHoria Geantă dma-coherent; 7281d0becabSHoria Geantă 7291d0becabSHoria Geantă sec_jr0: jr@10000 { 7301d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7311d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7321d0becabSHoria Geantă reg = <0x10000 0x10000>; 7331d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 7341d0becabSHoria Geantă }; 7351d0becabSHoria Geantă 7361d0becabSHoria Geantă sec_jr1: jr@20000 { 7371d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7381d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7391d0becabSHoria Geantă reg = <0x20000 0x10000>; 7401d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 7411d0becabSHoria Geantă }; 7421d0becabSHoria Geantă 7431d0becabSHoria Geantă sec_jr2: jr@30000 { 7441d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7451d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7461d0becabSHoria Geantă reg = <0x30000 0x10000>; 7471d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 7481d0becabSHoria Geantă }; 7491d0becabSHoria Geantă 7501d0becabSHoria Geantă sec_jr3: jr@40000 { 7511d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 7521d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 7531d0becabSHoria Geantă reg = <0x40000 0x10000>; 7541d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 7551d0becabSHoria Geantă }; 7561d0becabSHoria Geantă }; 7571d0becabSHoria Geantă 7587802f88dSPeng Ma qdma: dma-controller@8380000 { 7597802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 7607802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 7617802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 7627802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 7637802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 7647802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 7657802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 7667802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 7677802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 7687802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 7697802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 7707802f88dSPeng Ma dma-channels = <8>; 7717802f88dSPeng Ma block-number = <1>; 7727802f88dSPeng Ma block-offset = <0x10000>; 7737802f88dSPeng Ma fsl,dma-queues = <2>; 7747802f88dSPeng Ma status-sizes = <64>; 7757802f88dSPeng Ma queue-sizes = <64 64>; 7767802f88dSPeng Ma }; 7777802f88dSPeng Ma 77857aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 77957aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 78057aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 78199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 78299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 78399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 78499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 785f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 78657aa1bc7SChuanhua Han }; 78757aa1bc7SChuanhua Han 78857aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 78957aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 79057aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 79199314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 79299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>, 79399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 79499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(16)>; 795f2dc2359SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 79657aa1bc7SChuanhua Han }; 79757aa1bc7SChuanhua Han 7987de87eaeSMichael Walle malidp0: display@f080000 { 7997de87eaeSMichael Walle compatible = "arm,mali-dp500"; 8007de87eaeSMichael Walle reg = <0x0 0xf080000 0x0 0x10000>; 8017de87eaeSMichael Walle interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 8027de87eaeSMichael Walle <0 223 IRQ_TYPE_LEVEL_HIGH>; 8037de87eaeSMichael Walle interrupt-names = "DE", "SE"; 8047de87eaeSMichael Walle clocks = <&dpclk>, 8057de87eaeSMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>, 8067de87eaeSMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>, 8077de87eaeSMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>; 8087de87eaeSMichael Walle clock-names = "pxlclk", "mclk", "aclk", "pclk"; 8097de87eaeSMichael Walle arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 8107de87eaeSMichael Walle arm,malidp-arqos-value = <0xd000d000>; 8117de87eaeSMichael Walle 8127de87eaeSMichael Walle port { 8137de87eaeSMichael Walle dpi0_out: endpoint { 8147de87eaeSMichael Walle 8157de87eaeSMichael Walle }; 8167de87eaeSMichael Walle }; 8177de87eaeSMichael Walle }; 8187de87eaeSMichael Walle 81955ca18c0SMichael Walle gpu: gpu@f0c0000 { 82055ca18c0SMichael Walle compatible = "vivante,gc"; 82155ca18c0SMichael Walle reg = <0x0 0xf0c0000 0x0 0x10000>; 82255ca18c0SMichael Walle interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 82355ca18c0SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 82455ca18c0SMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>, 82555ca18c0SMichael Walle <&clockgen QORIQ_CLK_HWACCEL 2>; 82655ca18c0SMichael Walle clock-names = "core", "shader", "bus"; 82755ca18c0SMichael Walle #cooling-cells = <2>; 82855ca18c0SMichael Walle }; 82955ca18c0SMichael Walle 830f54f7be5SAlison Wang sai1: audio-controller@f100000 { 831f54f7be5SAlison Wang #sound-dai-cells = <0>; 832f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 833f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 834f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 83599314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 83699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 83799314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 83899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 83999314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 84099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 84199314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 84299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 843f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 844f54f7be5SAlison Wang dma-names = "tx", "rx"; 845f54f7be5SAlison Wang dmas = <&edma0 1 4>, 846f54f7be5SAlison Wang <&edma0 1 3>; 8479c015e13SMichael Walle fsl,sai-asynchronous; 848f54f7be5SAlison Wang status = "disabled"; 849f54f7be5SAlison Wang }; 850f54f7be5SAlison Wang 851f54f7be5SAlison Wang sai2: audio-controller@f110000 { 852f54f7be5SAlison Wang #sound-dai-cells = <0>; 853f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 854f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 855f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 85699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 85799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 85899314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 85999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 86099314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 86199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 86299314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 86399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 864f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 865f54f7be5SAlison Wang dma-names = "tx", "rx"; 866f54f7be5SAlison Wang dmas = <&edma0 1 6>, 867f54f7be5SAlison Wang <&edma0 1 5>; 8689c015e13SMichael Walle fsl,sai-asynchronous; 869f54f7be5SAlison Wang status = "disabled"; 870f54f7be5SAlison Wang }; 871f54f7be5SAlison Wang 872434f9cc1SMichael Walle sai3: audio-controller@f120000 { 873434f9cc1SMichael Walle #sound-dai-cells = <0>; 874434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 875434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 876434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 87799314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 87899314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 87999314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 88099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 88199314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 88299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 88399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 88499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 885434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 886434f9cc1SMichael Walle dma-names = "tx", "rx"; 887434f9cc1SMichael Walle dmas = <&edma0 1 8>, 888434f9cc1SMichael Walle <&edma0 1 7>; 8899c015e13SMichael Walle fsl,sai-asynchronous; 890f54f7be5SAlison Wang status = "disabled"; 891f54f7be5SAlison Wang }; 892f54f7be5SAlison Wang 893f54f7be5SAlison Wang sai4: audio-controller@f130000 { 894f54f7be5SAlison Wang #sound-dai-cells = <0>; 895f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 896f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 897f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 89899314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 89999314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 90099314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 90199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 90299314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 90399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 90499314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 90599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 906f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 907f54f7be5SAlison Wang dma-names = "tx", "rx"; 908f54f7be5SAlison Wang dmas = <&edma0 1 10>, 909f54f7be5SAlison Wang <&edma0 1 9>; 9109c015e13SMichael Walle fsl,sai-asynchronous; 911f54f7be5SAlison Wang status = "disabled"; 912f54f7be5SAlison Wang }; 913f54f7be5SAlison Wang 914434f9cc1SMichael Walle sai5: audio-controller@f140000 { 915434f9cc1SMichael Walle #sound-dai-cells = <0>; 916434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 917434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 918434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 91999314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 92099314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 92199314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 92299314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 92399314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 92499314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 92599314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 92699314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 927434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 928434f9cc1SMichael Walle dma-names = "tx", "rx"; 929434f9cc1SMichael Walle dmas = <&edma0 1 12>, 930434f9cc1SMichael Walle <&edma0 1 11>; 9319c015e13SMichael Walle fsl,sai-asynchronous; 932434f9cc1SMichael Walle status = "disabled"; 933434f9cc1SMichael Walle }; 934434f9cc1SMichael Walle 935434f9cc1SMichael Walle sai6: audio-controller@f150000 { 936434f9cc1SMichael Walle #sound-dai-cells = <0>; 937434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 938434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 939434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 94099314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 94199314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 94299314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 94399314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 94499314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 94599314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>, 94699314eb1SMichael Walle <&clockgen QORIQ_CLK_PLATFORM_PLL 94799314eb1SMichael Walle QORIQ_CLK_PLL_DIV(2)>; 948434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 949434f9cc1SMichael Walle dma-names = "tx", "rx"; 950434f9cc1SMichael Walle dmas = <&edma0 1 14>, 951434f9cc1SMichael Walle <&edma0 1 13>; 9529c015e13SMichael Walle fsl,sai-asynchronous; 9538897f325SBhaskar Upadhaya status = "disabled"; 9548897f325SBhaskar Upadhaya }; 9558897f325SBhaskar Upadhaya 956b4751afbSMichael Walle dpclk: clock-controller@f1f0000 { 957b4751afbSMichael Walle compatible = "fsl,ls1028a-plldig"; 958b4751afbSMichael Walle reg = <0x0 0xf1f0000 0x0 0x10000>; 959b4751afbSMichael Walle #clock-cells = <0>; 960b4751afbSMichael Walle clocks = <&osc_27m>; 961b4751afbSMichael Walle }; 962b4751afbSMichael Walle 9630b680963SFabio Estevam tmu: tmu@1f80000 { 964571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 965571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 966571cebfeSYuantian Tang interrupts = <0 23 0x4>; 967571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 968571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 969571cebfeSYuantian Tang 0x00000001 0x0000002b 970571cebfeSYuantian Tang 0x00000002 0x00000031 971571cebfeSYuantian Tang 0x00000003 0x00000038 972571cebfeSYuantian Tang 0x00000004 0x0000003f 973571cebfeSYuantian Tang 0x00000005 0x00000045 974571cebfeSYuantian Tang 0x00000006 0x0000004c 975571cebfeSYuantian Tang 0x00000007 0x00000053 976571cebfeSYuantian Tang 0x00000008 0x00000059 977571cebfeSYuantian Tang 0x00000009 0x00000060 978571cebfeSYuantian Tang 0x0000000a 0x00000066 979571cebfeSYuantian Tang 0x0000000b 0x0000006d 980571cebfeSYuantian Tang 981571cebfeSYuantian Tang 0x00010000 0x0000001c 982571cebfeSYuantian Tang 0x00010001 0x00000024 983571cebfeSYuantian Tang 0x00010002 0x0000002c 984571cebfeSYuantian Tang 0x00010003 0x00000035 985571cebfeSYuantian Tang 0x00010004 0x0000003d 986571cebfeSYuantian Tang 0x00010005 0x00000045 987571cebfeSYuantian Tang 0x00010006 0x0000004d 988961f8209SMichael Walle 0x00010007 0x00000055 989571cebfeSYuantian Tang 0x00010008 0x0000005e 990571cebfeSYuantian Tang 0x00010009 0x00000066 991571cebfeSYuantian Tang 0x0001000a 0x0000006e 992571cebfeSYuantian Tang 993571cebfeSYuantian Tang 0x00020000 0x00000018 994571cebfeSYuantian Tang 0x00020001 0x00000022 995571cebfeSYuantian Tang 0x00020002 0x0000002d 996571cebfeSYuantian Tang 0x00020003 0x00000038 997571cebfeSYuantian Tang 0x00020004 0x00000043 998571cebfeSYuantian Tang 0x00020005 0x0000004d 999571cebfeSYuantian Tang 0x00020006 0x00000058 1000571cebfeSYuantian Tang 0x00020007 0x00000063 1001571cebfeSYuantian Tang 0x00020008 0x0000006e 1002571cebfeSYuantian Tang 1003571cebfeSYuantian Tang 0x00030000 0x00000010 1004571cebfeSYuantian Tang 0x00030001 0x0000001c 1005571cebfeSYuantian Tang 0x00030002 0x00000029 1006571cebfeSYuantian Tang 0x00030003 0x00000036 1007571cebfeSYuantian Tang 0x00030004 0x00000042 1008571cebfeSYuantian Tang 0x00030005 0x0000004f 1009571cebfeSYuantian Tang 0x00030006 0x0000005b 1010571cebfeSYuantian Tang 0x00030007 0x00000068>; 1011571cebfeSYuantian Tang little-endian; 1012571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 1013571cebfeSYuantian Tang }; 1014571cebfeSYuantian Tang 10158897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 10168897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 10178897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 10188897f325SBhaskar Upadhaya #address-cells = <3>; 10198897f325SBhaskar Upadhaya #size-cells = <2>; 10208897f325SBhaskar Upadhaya msi-parent = <&its>; 10218897f325SBhaskar Upadhaya device_type = "pci"; 10228897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 10238897f325SBhaskar Upadhaya dma-coherent; 10248897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 10258897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 10268897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 10276bee93d9SKornel Duleba ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 10288897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 10296bee93d9SKornel Duleba 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 10308897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 10316bee93d9SKornel Duleba 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 10328897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 10336bee93d9SKornel Duleba 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 10348897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 10356bee93d9SKornel Duleba 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 10368897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 10376bee93d9SKornel Duleba 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1038b1520d8bSClaudiu Manoil /* BAR4 (PF5) - non-prefetchable memory */ 10396bee93d9SKornel Duleba 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 10408897f325SBhaskar Upadhaya 10418897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 10428897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 10438897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 10441a4bfe0fSVladimir Oltean status = "disabled"; 10458897f325SBhaskar Upadhaya }; 10461a4bfe0fSVladimir Oltean 10478897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 10488897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 10498897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 10501a4bfe0fSVladimir Oltean status = "disabled"; 10518897f325SBhaskar Upadhaya }; 10521a4bfe0fSVladimir Oltean 1053b1520d8bSClaudiu Manoil enetc_port2: ethernet@0,2 { 1054b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 1055b1520d8bSClaudiu Manoil reg = <0x000200 0 0 0 0>; 1056b1520d8bSClaudiu Manoil phy-mode = "internal"; 1057b1520d8bSClaudiu Manoil status = "disabled"; 1058b1520d8bSClaudiu Manoil 1059b1520d8bSClaudiu Manoil fixed-link { 10602c832fe4SVladimir Oltean speed = <2500>; 1061b1520d8bSClaudiu Manoil full-duplex; 1062*8fcea7beSVladimir Oltean pause; 1063b1520d8bSClaudiu Manoil }; 1064b1520d8bSClaudiu Manoil }; 1065b1520d8bSClaudiu Manoil 10668488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 10678488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 10688488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 10698488d8e9SClaudiu Manoil #address-cells = <1>; 10708488d8e9SClaudiu Manoil #size-cells = <0>; 10718488d8e9SClaudiu Manoil }; 10721a4bfe0fSVladimir Oltean 107349401003SY.b. Lu ethernet@0,4 { 107449401003SY.b. Lu compatible = "fsl,enetc-ptp"; 107549401003SY.b. Lu reg = <0x000400 0 0 0 0>; 107699314eb1SMichael Walle clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 107749401003SY.b. Lu little-endian; 1078ab84bad5SYangbo Lu fsl,extts-fifo; 107949401003SY.b. Lu }; 1080b1520d8bSClaudiu Manoil 1081630952e1SMichael Walle mscc_felix: ethernet-switch@0,5 { 1082b1520d8bSClaudiu Manoil reg = <0x000500 0 0 0 0>; 1083b1520d8bSClaudiu Manoil /* IEP INT_B */ 1084b1520d8bSClaudiu Manoil interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1085630952e1SMichael Walle status = "disabled"; 1086b1520d8bSClaudiu Manoil 1087b1520d8bSClaudiu Manoil ports { 1088b1520d8bSClaudiu Manoil #address-cells = <1>; 1089b1520d8bSClaudiu Manoil #size-cells = <0>; 1090b1520d8bSClaudiu Manoil 1091b1520d8bSClaudiu Manoil /* External ports */ 1092b1520d8bSClaudiu Manoil mscc_felix_port0: port@0 { 1093b1520d8bSClaudiu Manoil reg = <0>; 1094b1520d8bSClaudiu Manoil status = "disabled"; 1095b1520d8bSClaudiu Manoil }; 1096b1520d8bSClaudiu Manoil 1097b1520d8bSClaudiu Manoil mscc_felix_port1: port@1 { 1098b1520d8bSClaudiu Manoil reg = <1>; 1099b1520d8bSClaudiu Manoil status = "disabled"; 1100b1520d8bSClaudiu Manoil }; 1101b1520d8bSClaudiu Manoil 1102b1520d8bSClaudiu Manoil mscc_felix_port2: port@2 { 1103b1520d8bSClaudiu Manoil reg = <2>; 1104b1520d8bSClaudiu Manoil status = "disabled"; 1105b1520d8bSClaudiu Manoil }; 1106b1520d8bSClaudiu Manoil 1107b1520d8bSClaudiu Manoil mscc_felix_port3: port@3 { 1108b1520d8bSClaudiu Manoil reg = <3>; 1109b1520d8bSClaudiu Manoil status = "disabled"; 1110b1520d8bSClaudiu Manoil }; 1111b1520d8bSClaudiu Manoil 1112b1520d8bSClaudiu Manoil /* Internal ports */ 1113b1520d8bSClaudiu Manoil mscc_felix_port4: port@4 { 1114b1520d8bSClaudiu Manoil reg = <4>; 1115b1520d8bSClaudiu Manoil phy-mode = "internal"; 1116b1520d8bSClaudiu Manoil status = "disabled"; 1117b1520d8bSClaudiu Manoil 1118b1520d8bSClaudiu Manoil fixed-link { 1119b1520d8bSClaudiu Manoil speed = <2500>; 1120b1520d8bSClaudiu Manoil full-duplex; 1121*8fcea7beSVladimir Oltean pause; 1122b1520d8bSClaudiu Manoil }; 1123b1520d8bSClaudiu Manoil }; 1124b1520d8bSClaudiu Manoil 1125b1520d8bSClaudiu Manoil mscc_felix_port5: port@5 { 1126b1520d8bSClaudiu Manoil reg = <5>; 1127b1520d8bSClaudiu Manoil phy-mode = "internal"; 1128b1520d8bSClaudiu Manoil status = "disabled"; 1129b1520d8bSClaudiu Manoil 1130b1520d8bSClaudiu Manoil fixed-link { 1131b1520d8bSClaudiu Manoil speed = <1000>; 1132b1520d8bSClaudiu Manoil full-duplex; 1133*8fcea7beSVladimir Oltean pause; 1134b1520d8bSClaudiu Manoil }; 1135b1520d8bSClaudiu Manoil }; 1136b1520d8bSClaudiu Manoil }; 1137b1520d8bSClaudiu Manoil }; 1138b1520d8bSClaudiu Manoil 1139b1520d8bSClaudiu Manoil enetc_port3: ethernet@0,6 { 1140b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 1141b1520d8bSClaudiu Manoil reg = <0x000600 0 0 0 0>; 1142b1520d8bSClaudiu Manoil phy-mode = "internal"; 1143b1520d8bSClaudiu Manoil status = "disabled"; 1144b1520d8bSClaudiu Manoil 1145b1520d8bSClaudiu Manoil fixed-link { 1146b1520d8bSClaudiu Manoil speed = <1000>; 1147b1520d8bSClaudiu Manoil full-duplex; 1148*8fcea7beSVladimir Oltean pause; 1149b1520d8bSClaudiu Manoil }; 11508897f325SBhaskar Upadhaya }; 1151dfee46f1SMichael Walle 1152dfee46f1SMichael Walle rcec@1f,0 { 1153dfee46f1SMichael Walle reg = <0x00f800 0 0 0 0>; 1154dfee46f1SMichael Walle /* IEP INT_A */ 1155dfee46f1SMichael Walle interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1156dfee46f1SMichael Walle }; 11578897f325SBhaskar Upadhaya }; 1158791c88caSBiwen Li 1159b764dc6cSVladimir Oltean /* Integrated Endpoint Register Block */ 1160b764dc6cSVladimir Oltean ierb@1f0800000 { 1161b764dc6cSVladimir Oltean compatible = "fsl,ls1028a-enetc-ierb"; 1162b764dc6cSVladimir Oltean reg = <0x01 0xf0800000 0x0 0x10000>; 1163b764dc6cSVladimir Oltean }; 1164b764dc6cSVladimir Oltean 1165791c88caSBiwen Li rcpm: power-controller@1e34040 { 1166791c88caSBiwen Li compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1167791c88caSBiwen Li reg = <0x0 0x1e34040 0x0 0x1c>; 1168791c88caSBiwen Li #fsl,rcpm-wakeup-cells = <7>; 1169d9245428SBiwen Li little-endian; 1170791c88caSBiwen Li }; 1171791c88caSBiwen Li 1172791c88caSBiwen Li ftm_alarm0: timer@2800000 { 1173791c88caSBiwen Li compatible = "fsl,ls1028a-ftm-alarm"; 1174791c88caSBiwen Li reg = <0x0 0x2800000 0x0 0x10000>; 1175791c88caSBiwen Li fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1176791c88caSBiwen Li interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1177791c88caSBiwen Li }; 11788897f325SBhaskar Upadhaya }; 11797f538f19SWen He 11808897f325SBhaskar Upadhaya}; 1181