18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 58897f325SBhaskar Upadhaya * Copyright 2018 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 208897f325SBhaskar Upadhaya cpus { 218897f325SBhaskar Upadhaya #address-cells = <1>; 228897f325SBhaskar Upadhaya #size-cells = <0>; 238897f325SBhaskar Upadhaya 248897f325SBhaskar Upadhaya cpu0: cpu@0 { 258897f325SBhaskar Upadhaya device_type = "cpu"; 268897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 278897f325SBhaskar Upadhaya reg = <0x0>; 288897f325SBhaskar Upadhaya enable-method = "psci"; 298897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 308897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3153f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 32571cebfeSYuantian Tang #cooling-cells = <2>; 338897f325SBhaskar Upadhaya }; 348897f325SBhaskar Upadhaya 358897f325SBhaskar Upadhaya cpu1: cpu@1 { 368897f325SBhaskar Upadhaya device_type = "cpu"; 378897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 388897f325SBhaskar Upadhaya reg = <0x1>; 398897f325SBhaskar Upadhaya enable-method = "psci"; 408897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 418897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 43571cebfeSYuantian Tang #cooling-cells = <2>; 448897f325SBhaskar Upadhaya }; 458897f325SBhaskar Upadhaya 468897f325SBhaskar Upadhaya l2: l2-cache { 478897f325SBhaskar Upadhaya compatible = "cache"; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya 518897f325SBhaskar Upadhaya idle-states { 528897f325SBhaskar Upadhaya /* 538897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 548897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 558897f325SBhaskar Upadhaya */ 568897f325SBhaskar Upadhaya entry-method = "arm,psci"; 578897f325SBhaskar Upadhaya 5853f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 598897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6053f2ac9dSRan Wang idle-state-name = "PW20"; 6153f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6253f2ac9dSRan Wang entry-latency-us = <2000>; 6353f2ac9dSRan Wang exit-latency-us = <2000>; 6453f2ac9dSRan Wang min-residency-us = <6000>; 658897f325SBhaskar Upadhaya }; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya 688897f325SBhaskar Upadhaya sysclk: clock-sysclk { 698897f325SBhaskar Upadhaya compatible = "fixed-clock"; 708897f325SBhaskar Upadhaya #clock-cells = <0>; 718897f325SBhaskar Upadhaya clock-frequency = <100000000>; 728897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 738897f325SBhaskar Upadhaya }; 748897f325SBhaskar Upadhaya 7581f36887SWen He osc_27m: clock-osc-27m { 767f538f19SWen He compatible = "fixed-clock"; 777f538f19SWen He #clock-cells = <0>; 787f538f19SWen He clock-frequency = <27000000>; 7981f36887SWen He clock-output-names = "phy_27m"; 8081f36887SWen He }; 8181f36887SWen He 8281f36887SWen He dpclk: clock-controller@f1f0000 { 8381f36887SWen He compatible = "fsl,ls1028a-plldig"; 8481f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8581f36887SWen He #clock-cells = <1>; 8681f36887SWen He clocks = <&osc_27m>; 877f538f19SWen He }; 887f538f19SWen He 897f538f19SWen He aclk: clock-axi { 907f538f19SWen He compatible = "fixed-clock"; 917f538f19SWen He #clock-cells = <0>; 927f538f19SWen He clock-frequency = <650000000>; 937f538f19SWen He clock-output-names= "aclk"; 947f538f19SWen He }; 957f538f19SWen He 967f538f19SWen He pclk: clock-apb { 977f538f19SWen He compatible = "fixed-clock"; 987f538f19SWen He #clock-cells = <0>; 997f538f19SWen He clock-frequency = <650000000>; 1007f538f19SWen He clock-output-names= "pclk"; 1017f538f19SWen He }; 1027f538f19SWen He 1038897f325SBhaskar Upadhaya reboot { 1048897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 1058897f325SBhaskar Upadhaya regmap = <&dcfg>; 1068897f325SBhaskar Upadhaya offset = <0xb0>; 1078897f325SBhaskar Upadhaya mask = <0x02>; 1088897f325SBhaskar Upadhaya }; 1098897f325SBhaskar Upadhaya 1108897f325SBhaskar Upadhaya timer { 1118897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 1128897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 1138897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1148897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1158897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1168897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1178897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1188897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1198897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1208897f325SBhaskar Upadhaya }; 1218897f325SBhaskar Upadhaya 122b9eb314aSAlison Wang pmu { 123b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 124b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 125b9eb314aSAlison Wang }; 126b9eb314aSAlison Wang 1278897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1288897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1298897f325SBhaskar Upadhaya #address-cells = <2>; 1308897f325SBhaskar Upadhaya #size-cells = <2>; 1318897f325SBhaskar Upadhaya ranges; 1328897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1338897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1348897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1358897f325SBhaskar Upadhaya interrupt-controller; 1368897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1378897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1388897f325SBhaskar Upadhaya its: gic-its@6020000 { 1398897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1408897f325SBhaskar Upadhaya msi-controller; 1418897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1428897f325SBhaskar Upadhaya }; 1438897f325SBhaskar Upadhaya }; 1448897f325SBhaskar Upadhaya 1458897f325SBhaskar Upadhaya soc: soc { 1468897f325SBhaskar Upadhaya compatible = "simple-bus"; 1478897f325SBhaskar Upadhaya #address-cells = <2>; 1488897f325SBhaskar Upadhaya #size-cells = <2>; 1498897f325SBhaskar Upadhaya ranges; 1508897f325SBhaskar Upadhaya 1518897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1528897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1538897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1548897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1558897f325SBhaskar Upadhaya big-endian; 1568897f325SBhaskar Upadhaya }; 1578897f325SBhaskar Upadhaya 1588897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 1598897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 1608897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 1618897f325SBhaskar Upadhaya big-endian; 1628897f325SBhaskar Upadhaya }; 1638897f325SBhaskar Upadhaya 1648897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 1658897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 1668897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 1678897f325SBhaskar Upadhaya big-endian; 1688897f325SBhaskar Upadhaya }; 1698897f325SBhaskar Upadhaya 1708897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 1718897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 1728897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 1738897f325SBhaskar Upadhaya #clock-cells = <2>; 1748897f325SBhaskar Upadhaya clocks = <&sysclk>; 1758897f325SBhaskar Upadhaya }; 1768897f325SBhaskar Upadhaya 1778897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 1788897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 1798897f325SBhaskar Upadhaya #address-cells = <1>; 1808897f325SBhaskar Upadhaya #size-cells = <0>; 1818897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 1828897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 183ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 1848897f325SBhaskar Upadhaya status = "disabled"; 1858897f325SBhaskar Upadhaya }; 1868897f325SBhaskar Upadhaya 1878897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 1888897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 1898897f325SBhaskar Upadhaya #address-cells = <1>; 1908897f325SBhaskar Upadhaya #size-cells = <0>; 1918897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 1928897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 193ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 1948897f325SBhaskar Upadhaya status = "disabled"; 1958897f325SBhaskar Upadhaya }; 1968897f325SBhaskar Upadhaya 1978897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 1988897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 1998897f325SBhaskar Upadhaya #address-cells = <1>; 2008897f325SBhaskar Upadhaya #size-cells = <0>; 2018897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2028897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 203ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2048897f325SBhaskar Upadhaya status = "disabled"; 2058897f325SBhaskar Upadhaya }; 2068897f325SBhaskar Upadhaya 2078897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2088897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2098897f325SBhaskar Upadhaya #address-cells = <1>; 2108897f325SBhaskar Upadhaya #size-cells = <0>; 2118897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2128897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 213ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2148897f325SBhaskar Upadhaya status = "disabled"; 2158897f325SBhaskar Upadhaya }; 2168897f325SBhaskar Upadhaya 2178897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2188897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2198897f325SBhaskar Upadhaya #address-cells = <1>; 2208897f325SBhaskar Upadhaya #size-cells = <0>; 2218897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2228897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 223ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2248897f325SBhaskar Upadhaya status = "disabled"; 2258897f325SBhaskar Upadhaya }; 2268897f325SBhaskar Upadhaya 2278897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2288897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2298897f325SBhaskar Upadhaya #address-cells = <1>; 2308897f325SBhaskar Upadhaya #size-cells = <0>; 2318897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2328897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 233ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2348897f325SBhaskar Upadhaya status = "disabled"; 2358897f325SBhaskar Upadhaya }; 2368897f325SBhaskar Upadhaya 2378897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2388897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2398897f325SBhaskar Upadhaya #address-cells = <1>; 2408897f325SBhaskar Upadhaya #size-cells = <0>; 2418897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2428897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 243ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2448897f325SBhaskar Upadhaya status = "disabled"; 2458897f325SBhaskar Upadhaya }; 2468897f325SBhaskar Upadhaya 2478897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2488897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2498897f325SBhaskar Upadhaya #address-cells = <1>; 2508897f325SBhaskar Upadhaya #size-cells = <0>; 2518897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2528897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 253ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2548897f325SBhaskar Upadhaya status = "disabled"; 2558897f325SBhaskar Upadhaya }; 2568897f325SBhaskar Upadhaya 257491d3a3fSAshish Kumar esdhc: mmc@2140000 { 258491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 259491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 260491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 261491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 262491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 263491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 264491d3a3fSAshish Kumar sdhci,auto-cmd12; 265491d3a3fSAshish Kumar little-endian; 266491d3a3fSAshish Kumar bus-width = <4>; 267491d3a3fSAshish Kumar status = "disabled"; 268491d3a3fSAshish Kumar }; 269491d3a3fSAshish Kumar 270491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 271491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 272491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 273491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 274491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 275491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 276491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 277491d3a3fSAshish Kumar sdhci,auto-cmd12; 278491d3a3fSAshish Kumar broken-cd; 279491d3a3fSAshish Kumar little-endian; 280491d3a3fSAshish Kumar bus-width = <4>; 281491d3a3fSAshish Kumar status = "disabled"; 282491d3a3fSAshish Kumar }; 283491d3a3fSAshish Kumar 2848897f325SBhaskar Upadhaya duart0: serial@21c0500 { 2858897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 2868897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 2878897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2888897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 2898897f325SBhaskar Upadhaya status = "disabled"; 2908897f325SBhaskar Upadhaya }; 2918897f325SBhaskar Upadhaya 2928897f325SBhaskar Upadhaya duart1: serial@21c0600 { 2938897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 2948897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 2958897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2968897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 2978897f325SBhaskar Upadhaya status = "disabled"; 2988897f325SBhaskar Upadhaya }; 2998897f325SBhaskar Upadhaya 300f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 301f54f7be5SAlison Wang #dma-cells = <2>; 302f54f7be5SAlison Wang compatible = "fsl,vf610-edma"; 303f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 304f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 305f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 306f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 307f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 308f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 309f54f7be5SAlison Wang dma-channels = <32>; 310f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 311f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 312f54f7be5SAlison Wang <&clockgen 4 1>; 313f54f7be5SAlison Wang }; 314f54f7be5SAlison Wang 3158897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 316f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3178897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 3188897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3198897f325SBhaskar Upadhaya gpio-controller; 3208897f325SBhaskar Upadhaya #gpio-cells = <2>; 3218897f325SBhaskar Upadhaya interrupt-controller; 3228897f325SBhaskar Upadhaya #interrupt-cells = <2>; 323f64697bdSSong Hui little-endian; 3248897f325SBhaskar Upadhaya }; 3258897f325SBhaskar Upadhaya 3268897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 327f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3288897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 3298897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3308897f325SBhaskar Upadhaya gpio-controller; 3318897f325SBhaskar Upadhaya #gpio-cells = <2>; 3328897f325SBhaskar Upadhaya interrupt-controller; 3338897f325SBhaskar Upadhaya #interrupt-cells = <2>; 334f64697bdSSong Hui little-endian; 3358897f325SBhaskar Upadhaya }; 3368897f325SBhaskar Upadhaya 3378897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 338f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 3398897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 3408897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3418897f325SBhaskar Upadhaya gpio-controller; 3428897f325SBhaskar Upadhaya #gpio-cells = <2>; 3438897f325SBhaskar Upadhaya interrupt-controller; 3448897f325SBhaskar Upadhaya #interrupt-cells = <2>; 345f64697bdSSong Hui little-endian; 3468897f325SBhaskar Upadhaya }; 3478897f325SBhaskar Upadhaya 348c92f56faSRan Wang usb0: usb@3100000 { 349c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 350c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 351c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 352c92f56faSRan Wang dr_mode = "host"; 353c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 354c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 355c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 356c92f56faSRan Wang }; 357c92f56faSRan Wang 358c92f56faSRan Wang usb1: usb@3110000 { 359c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 360c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 361c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 362c92f56faSRan Wang dr_mode = "host"; 363c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 364c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 365c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 3668897f325SBhaskar Upadhaya }; 3678897f325SBhaskar Upadhaya 3688897f325SBhaskar Upadhaya sata: sata@3200000 { 3698897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 3708897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 3713f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 3728897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 3738897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3748897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3758897f325SBhaskar Upadhaya status = "disabled"; 3768897f325SBhaskar Upadhaya }; 3778897f325SBhaskar Upadhaya 3788897f325SBhaskar Upadhaya smmu: iommu@5000000 { 3798897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 3808897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 3818897f325SBhaskar Upadhaya #global-interrupts = <8>; 3828897f325SBhaskar Upadhaya #iommu-cells = <1>; 3838897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 3848897f325SBhaskar Upadhaya /* global secure fault */ 3858897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 3868897f325SBhaskar Upadhaya /* combined secure interrupt */ 3878897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 3888897f325SBhaskar Upadhaya /* global non-secure fault */ 3898897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 3908897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 3918897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 3928897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 3938897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 3948897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 3958897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 3968897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3978897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3988897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3998897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 4008897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 4018897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 4028897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 4038897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 4048897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4058897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 4068897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 4078897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 4088897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 4098897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 4108897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 4118897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 4128897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 4138897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4148897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4158897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4168897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4178897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4188897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4198897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 4208897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 4218897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 4228897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 4238897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 4248897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 4258897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 4268897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4278897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 4288897f325SBhaskar Upadhaya }; 429927d7f85SClaudiu Manoil 4301d0becabSHoria Geantă crypto: crypto@8000000 { 4311d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 4321d0becabSHoria Geantă fsl,sec-era = <10>; 4331d0becabSHoria Geantă #address-cells = <1>; 4341d0becabSHoria Geantă #size-cells = <1>; 4351d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 4361d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 4371d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4381d0becabSHoria Geantă dma-coherent; 4391d0becabSHoria Geantă 4401d0becabSHoria Geantă sec_jr0: jr@10000 { 4411d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4421d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4431d0becabSHoria Geantă reg = <0x10000 0x10000>; 4441d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4451d0becabSHoria Geantă }; 4461d0becabSHoria Geantă 4471d0becabSHoria Geantă sec_jr1: jr@20000 { 4481d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4491d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4501d0becabSHoria Geantă reg = <0x20000 0x10000>; 4511d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4521d0becabSHoria Geantă }; 4531d0becabSHoria Geantă 4541d0becabSHoria Geantă sec_jr2: jr@30000 { 4551d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4561d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4571d0becabSHoria Geantă reg = <0x30000 0x10000>; 4581d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4591d0becabSHoria Geantă }; 4601d0becabSHoria Geantă 4611d0becabSHoria Geantă sec_jr3: jr@40000 { 4621d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 4631d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 4641d0becabSHoria Geantă reg = <0x40000 0x10000>; 4651d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4661d0becabSHoria Geantă }; 4671d0becabSHoria Geantă }; 4681d0becabSHoria Geantă 4697802f88dSPeng Ma qdma: dma-controller@8380000 { 4707802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 4717802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 4727802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 4737802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 4747802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 4757802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 4767802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 4777802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 4787802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 4797802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 4807802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 4817802f88dSPeng Ma dma-channels = <8>; 4827802f88dSPeng Ma block-number = <1>; 4837802f88dSPeng Ma block-offset = <0x10000>; 4847802f88dSPeng Ma fsl,dma-queues = <2>; 4857802f88dSPeng Ma status-sizes = <64>; 4867802f88dSPeng Ma queue-sizes = <64 64>; 4877802f88dSPeng Ma }; 4887802f88dSPeng Ma 48957aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 49057aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 49157aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 49257aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 49357aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 49457aa1bc7SChuanhua Han }; 49557aa1bc7SChuanhua Han 49657aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 49757aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 49857aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 49957aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 50057aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 50157aa1bc7SChuanhua Han }; 50257aa1bc7SChuanhua Han 503f54f7be5SAlison Wang sai1: audio-controller@f100000 { 504f54f7be5SAlison Wang #sound-dai-cells = <0>; 505f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 506f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 507f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 508f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 509f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 510f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 511f54f7be5SAlison Wang dma-names = "tx", "rx"; 512f54f7be5SAlison Wang dmas = <&edma0 1 4>, 513f54f7be5SAlison Wang <&edma0 1 3>; 514f54f7be5SAlison Wang status = "disabled"; 515f54f7be5SAlison Wang }; 516f54f7be5SAlison Wang 517f54f7be5SAlison Wang sai2: audio-controller@f110000 { 518f54f7be5SAlison Wang #sound-dai-cells = <0>; 519f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 520f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 521f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 522f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 523f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 524f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 525f54f7be5SAlison Wang dma-names = "tx", "rx"; 526f54f7be5SAlison Wang dmas = <&edma0 1 6>, 527f54f7be5SAlison Wang <&edma0 1 5>; 528f54f7be5SAlison Wang status = "disabled"; 529f54f7be5SAlison Wang }; 530f54f7be5SAlison Wang 531f54f7be5SAlison Wang sai4: audio-controller@f130000 { 532f54f7be5SAlison Wang #sound-dai-cells = <0>; 533f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 534f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 535f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 536f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 537f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 538f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 539f54f7be5SAlison Wang dma-names = "tx", "rx"; 540f54f7be5SAlison Wang dmas = <&edma0 1 10>, 541f54f7be5SAlison Wang <&edma0 1 9>; 542f54f7be5SAlison Wang status = "disabled"; 543f54f7be5SAlison Wang }; 544f54f7be5SAlison Wang 545571cebfeSYuantian Tang tmu: tmu@1f00000 { 546571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 547571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 548571cebfeSYuantian Tang interrupts = <0 23 0x4>; 549571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 550571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 551571cebfeSYuantian Tang 0x00000001 0x0000002b 552571cebfeSYuantian Tang 0x00000002 0x00000031 553571cebfeSYuantian Tang 0x00000003 0x00000038 554571cebfeSYuantian Tang 0x00000004 0x0000003f 555571cebfeSYuantian Tang 0x00000005 0x00000045 556571cebfeSYuantian Tang 0x00000006 0x0000004c 557571cebfeSYuantian Tang 0x00000007 0x00000053 558571cebfeSYuantian Tang 0x00000008 0x00000059 559571cebfeSYuantian Tang 0x00000009 0x00000060 560571cebfeSYuantian Tang 0x0000000a 0x00000066 561571cebfeSYuantian Tang 0x0000000b 0x0000006d 562571cebfeSYuantian Tang 563571cebfeSYuantian Tang 0x00010000 0x0000001c 564571cebfeSYuantian Tang 0x00010001 0x00000024 565571cebfeSYuantian Tang 0x00010002 0x0000002c 566571cebfeSYuantian Tang 0x00010003 0x00000035 567571cebfeSYuantian Tang 0x00010004 0x0000003d 568571cebfeSYuantian Tang 0x00010005 0x00000045 569571cebfeSYuantian Tang 0x00010006 0x0000004d 570571cebfeSYuantian Tang 0x00010007 0x00000045 571571cebfeSYuantian Tang 0x00010008 0x0000005e 572571cebfeSYuantian Tang 0x00010009 0x00000066 573571cebfeSYuantian Tang 0x0001000a 0x0000006e 574571cebfeSYuantian Tang 575571cebfeSYuantian Tang 0x00020000 0x00000018 576571cebfeSYuantian Tang 0x00020001 0x00000022 577571cebfeSYuantian Tang 0x00020002 0x0000002d 578571cebfeSYuantian Tang 0x00020003 0x00000038 579571cebfeSYuantian Tang 0x00020004 0x00000043 580571cebfeSYuantian Tang 0x00020005 0x0000004d 581571cebfeSYuantian Tang 0x00020006 0x00000058 582571cebfeSYuantian Tang 0x00020007 0x00000063 583571cebfeSYuantian Tang 0x00020008 0x0000006e 584571cebfeSYuantian Tang 585571cebfeSYuantian Tang 0x00030000 0x00000010 586571cebfeSYuantian Tang 0x00030001 0x0000001c 587571cebfeSYuantian Tang 0x00030002 0x00000029 588571cebfeSYuantian Tang 0x00030003 0x00000036 589571cebfeSYuantian Tang 0x00030004 0x00000042 590571cebfeSYuantian Tang 0x00030005 0x0000004f 591571cebfeSYuantian Tang 0x00030006 0x0000005b 592571cebfeSYuantian Tang 0x00030007 0x00000068>; 593571cebfeSYuantian Tang little-endian; 594571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 595571cebfeSYuantian Tang }; 596571cebfeSYuantian Tang 597571cebfeSYuantian Tang thermal-zones { 598571cebfeSYuantian Tang core-cluster { 599571cebfeSYuantian Tang polling-delay-passive = <1000>; 600571cebfeSYuantian Tang polling-delay = <5000>; 601571cebfeSYuantian Tang thermal-sensors = <&tmu 0>; 602571cebfeSYuantian Tang 603571cebfeSYuantian Tang trips { 604571cebfeSYuantian Tang core_cluster_alert: core-cluster-alert { 605571cebfeSYuantian Tang temperature = <85000>; 606571cebfeSYuantian Tang hysteresis = <2000>; 607571cebfeSYuantian Tang type = "passive"; 608571cebfeSYuantian Tang }; 609571cebfeSYuantian Tang 610571cebfeSYuantian Tang core_cluster_crit: core-cluster-crit { 611571cebfeSYuantian Tang temperature = <95000>; 612571cebfeSYuantian Tang hysteresis = <2000>; 613571cebfeSYuantian Tang type = "critical"; 614571cebfeSYuantian Tang }; 615571cebfeSYuantian Tang }; 616571cebfeSYuantian Tang 617571cebfeSYuantian Tang cooling-maps { 618571cebfeSYuantian Tang map0 { 619571cebfeSYuantian Tang trip = <&core_cluster_alert>; 620571cebfeSYuantian Tang cooling-device = 621571cebfeSYuantian Tang <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 622571cebfeSYuantian Tang <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 623571cebfeSYuantian Tang }; 624571cebfeSYuantian Tang }; 625571cebfeSYuantian Tang }; 626571cebfeSYuantian Tang }; 627571cebfeSYuantian Tang 628927d7f85SClaudiu Manoil pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 629927d7f85SClaudiu Manoil compatible = "pci-host-ecam-generic"; 630927d7f85SClaudiu Manoil reg = <0x01 0xf0000000 0x0 0x100000>; 631927d7f85SClaudiu Manoil #address-cells = <3>; 632927d7f85SClaudiu Manoil #size-cells = <2>; 633927d7f85SClaudiu Manoil #interrupt-cells = <1>; 634927d7f85SClaudiu Manoil msi-parent = <&its>; 635927d7f85SClaudiu Manoil device_type = "pci"; 636927d7f85SClaudiu Manoil bus-range = <0x0 0x0>; 637927d7f85SClaudiu Manoil dma-coherent; 638927d7f85SClaudiu Manoil msi-map = <0 &its 0x17 0xe>; 639927d7f85SClaudiu Manoil iommu-map = <0 &smmu 0x17 0xe>; 640927d7f85SClaudiu Manoil /* PF0-6 BAR0 - non-prefetchable memory */ 641927d7f85SClaudiu Manoil ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 642927d7f85SClaudiu Manoil /* PF0-6 BAR2 - prefetchable memory */ 643927d7f85SClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 644927d7f85SClaudiu Manoil /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 645927d7f85SClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 646927d7f85SClaudiu Manoil /* PF0: VF0-1 BAR2 - prefetchable memory */ 647927d7f85SClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 648927d7f85SClaudiu Manoil /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 649927d7f85SClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 650927d7f85SClaudiu Manoil /* PF1: VF0-1 BAR2 - prefetchable memory */ 651927d7f85SClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 652927d7f85SClaudiu Manoil 653927d7f85SClaudiu Manoil enetc_port0: ethernet@0,0 { 654927d7f85SClaudiu Manoil compatible = "fsl,enetc"; 655927d7f85SClaudiu Manoil reg = <0x000000 0 0 0 0>; 656927d7f85SClaudiu Manoil }; 657927d7f85SClaudiu Manoil enetc_port1: ethernet@0,1 { 658927d7f85SClaudiu Manoil compatible = "fsl,enetc"; 659927d7f85SClaudiu Manoil reg = <0x000100 0 0 0 0>; 660927d7f85SClaudiu Manoil }; 66149401003SY.b. Lu ethernet@0,4 { 66249401003SY.b. Lu compatible = "fsl,enetc-ptp"; 66349401003SY.b. Lu reg = <0x000400 0 0 0 0>; 66449401003SY.b. Lu clocks = <&clockgen 4 0>; 66549401003SY.b. Lu little-endian; 66649401003SY.b. Lu }; 667927d7f85SClaudiu Manoil }; 6688897f325SBhaskar Upadhaya }; 6697f538f19SWen He 6707f538f19SWen He malidp0: display@f080000 { 6717f538f19SWen He compatible = "arm,mali-dp500"; 6727f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 6737f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 6747f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 6757f538f19SWen He interrupt-names = "DE", "SE"; 67681f36887SWen He clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>; 6777f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 6787f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 6793a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 6807f538f19SWen He 6817f538f19SWen He port { 6827f538f19SWen He dp0_out: endpoint { 6837f538f19SWen He 6847f538f19SWen He }; 6857f538f19SWen He }; 6867f538f19SWen He }; 6878897f325SBhaskar Upadhaya}; 688