18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 58897f325SBhaskar Upadhaya * Copyright 2018 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 208897f325SBhaskar Upadhaya cpus { 218897f325SBhaskar Upadhaya #address-cells = <1>; 228897f325SBhaskar Upadhaya #size-cells = <0>; 238897f325SBhaskar Upadhaya 248897f325SBhaskar Upadhaya cpu0: cpu@0 { 258897f325SBhaskar Upadhaya device_type = "cpu"; 268897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 278897f325SBhaskar Upadhaya reg = <0x0>; 288897f325SBhaskar Upadhaya enable-method = "psci"; 298897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 308897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3153f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 32571cebfeSYuantian Tang #cooling-cells = <2>; 338897f325SBhaskar Upadhaya }; 348897f325SBhaskar Upadhaya 358897f325SBhaskar Upadhaya cpu1: cpu@1 { 368897f325SBhaskar Upadhaya device_type = "cpu"; 378897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 388897f325SBhaskar Upadhaya reg = <0x1>; 398897f325SBhaskar Upadhaya enable-method = "psci"; 408897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 418897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 43571cebfeSYuantian Tang #cooling-cells = <2>; 448897f325SBhaskar Upadhaya }; 458897f325SBhaskar Upadhaya 468897f325SBhaskar Upadhaya l2: l2-cache { 478897f325SBhaskar Upadhaya compatible = "cache"; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya 518897f325SBhaskar Upadhaya idle-states { 528897f325SBhaskar Upadhaya /* 538897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 548897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 558897f325SBhaskar Upadhaya */ 569b631649SLinus Walleij entry-method = "psci"; 578897f325SBhaskar Upadhaya 5853f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 598897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6053f2ac9dSRan Wang idle-state-name = "PW20"; 6153f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6253f2ac9dSRan Wang entry-latency-us = <2000>; 6353f2ac9dSRan Wang exit-latency-us = <2000>; 6453f2ac9dSRan Wang min-residency-us = <6000>; 658897f325SBhaskar Upadhaya }; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya 688897f325SBhaskar Upadhaya sysclk: clock-sysclk { 698897f325SBhaskar Upadhaya compatible = "fixed-clock"; 708897f325SBhaskar Upadhaya #clock-cells = <0>; 718897f325SBhaskar Upadhaya clock-frequency = <100000000>; 728897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 738897f325SBhaskar Upadhaya }; 748897f325SBhaskar Upadhaya 7581f36887SWen He osc_27m: clock-osc-27m { 767f538f19SWen He compatible = "fixed-clock"; 777f538f19SWen He #clock-cells = <0>; 787f538f19SWen He clock-frequency = <27000000>; 7981f36887SWen He clock-output-names = "phy_27m"; 8081f36887SWen He }; 8181f36887SWen He 8281f36887SWen He dpclk: clock-controller@f1f0000 { 8381f36887SWen He compatible = "fsl,ls1028a-plldig"; 8481f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8591035cb0SWen He #clock-cells = <0>; 8681f36887SWen He clocks = <&osc_27m>; 877f538f19SWen He }; 887f538f19SWen He 898897f325SBhaskar Upadhaya reboot { 908897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 913f0fb37bSMichael Walle regmap = <&rst>; 928897f325SBhaskar Upadhaya offset = <0xb0>; 938897f325SBhaskar Upadhaya mask = <0x02>; 948897f325SBhaskar Upadhaya }; 958897f325SBhaskar Upadhaya 968897f325SBhaskar Upadhaya timer { 978897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 988897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 998897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1008897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1018897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1028897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1038897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1048897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1058897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1068897f325SBhaskar Upadhaya }; 1078897f325SBhaskar Upadhaya 108b9eb314aSAlison Wang pmu { 109b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 110b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111b9eb314aSAlison Wang }; 112b9eb314aSAlison Wang 1138897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1148897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1158897f325SBhaskar Upadhaya #address-cells = <2>; 1168897f325SBhaskar Upadhaya #size-cells = <2>; 1178897f325SBhaskar Upadhaya ranges; 1188897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1198897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1208897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1218897f325SBhaskar Upadhaya interrupt-controller; 1228897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1238897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1248897f325SBhaskar Upadhaya its: gic-its@6020000 { 1258897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1268897f325SBhaskar Upadhaya msi-controller; 1278897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1288897f325SBhaskar Upadhaya }; 1298897f325SBhaskar Upadhaya }; 1308897f325SBhaskar Upadhaya 13168e36a42SFabio Estevam thermal-zones { 1323269c178SYuantian Tang ddr-controller { 13368e36a42SFabio Estevam polling-delay-passive = <1000>; 13468e36a42SFabio Estevam polling-delay = <5000>; 13568e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 13668e36a42SFabio Estevam 13768e36a42SFabio Estevam trips { 1383269c178SYuantian Tang ddr-ctrler-alert { 1393269c178SYuantian Tang temperature = <85000>; 1403269c178SYuantian Tang hysteresis = <2000>; 1413269c178SYuantian Tang type = "passive"; 1423269c178SYuantian Tang }; 1433269c178SYuantian Tang 1443269c178SYuantian Tang ddr-ctrler-crit { 1453269c178SYuantian Tang temperature = <95000>; 1463269c178SYuantian Tang hysteresis = <2000>; 1473269c178SYuantian Tang type = "critical"; 1483269c178SYuantian Tang }; 1493269c178SYuantian Tang }; 1503269c178SYuantian Tang }; 1513269c178SYuantian Tang 1523269c178SYuantian Tang core-cluster { 1533269c178SYuantian Tang polling-delay-passive = <1000>; 1543269c178SYuantian Tang polling-delay = <5000>; 1553269c178SYuantian Tang thermal-sensors = <&tmu 1>; 1563269c178SYuantian Tang 1573269c178SYuantian Tang trips { 15868e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 15968e36a42SFabio Estevam temperature = <85000>; 16068e36a42SFabio Estevam hysteresis = <2000>; 16168e36a42SFabio Estevam type = "passive"; 16268e36a42SFabio Estevam }; 16368e36a42SFabio Estevam 16468e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 16568e36a42SFabio Estevam temperature = <95000>; 16668e36a42SFabio Estevam hysteresis = <2000>; 16768e36a42SFabio Estevam type = "critical"; 16868e36a42SFabio Estevam }; 16968e36a42SFabio Estevam }; 17068e36a42SFabio Estevam 17168e36a42SFabio Estevam cooling-maps { 17268e36a42SFabio Estevam map0 { 17368e36a42SFabio Estevam trip = <&core_cluster_alert>; 17468e36a42SFabio Estevam cooling-device = 17568e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 17668e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 17768e36a42SFabio Estevam }; 17868e36a42SFabio Estevam }; 17968e36a42SFabio Estevam }; 18068e36a42SFabio Estevam }; 18168e36a42SFabio Estevam 1828897f325SBhaskar Upadhaya soc: soc { 1838897f325SBhaskar Upadhaya compatible = "simple-bus"; 1848897f325SBhaskar Upadhaya #address-cells = <2>; 1858897f325SBhaskar Upadhaya #size-cells = <2>; 1868897f325SBhaskar Upadhaya ranges; 1878897f325SBhaskar Upadhaya 1888897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1898897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1908897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1918897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1928897f325SBhaskar Upadhaya big-endian; 1938897f325SBhaskar Upadhaya }; 1948897f325SBhaskar Upadhaya 1958897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 1968897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 1978897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 19833eae7fbSYinbo Zhu little-endian; 1998897f325SBhaskar Upadhaya }; 2008897f325SBhaskar Upadhaya 2013f0fb37bSMichael Walle rst: syscon@1e60000 { 2023f0fb37bSMichael Walle compatible = "syscon"; 2033f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 2043f0fb37bSMichael Walle little-endian; 2053f0fb37bSMichael Walle }; 2063f0fb37bSMichael Walle 2078897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 2088897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 2098897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 2108897f325SBhaskar Upadhaya big-endian; 2118897f325SBhaskar Upadhaya }; 2128897f325SBhaskar Upadhaya 2138897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 2148897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 2158897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 2168897f325SBhaskar Upadhaya #clock-cells = <2>; 2178897f325SBhaskar Upadhaya clocks = <&sysclk>; 2188897f325SBhaskar Upadhaya }; 2198897f325SBhaskar Upadhaya 2208897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2218897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2228897f325SBhaskar Upadhaya #address-cells = <1>; 2238897f325SBhaskar Upadhaya #size-cells = <0>; 2248897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2258897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 226ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2278897f325SBhaskar Upadhaya status = "disabled"; 2288897f325SBhaskar Upadhaya }; 2298897f325SBhaskar Upadhaya 2308897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2318897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2328897f325SBhaskar Upadhaya #address-cells = <1>; 2338897f325SBhaskar Upadhaya #size-cells = <0>; 2348897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2358897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 236ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2378897f325SBhaskar Upadhaya status = "disabled"; 2388897f325SBhaskar Upadhaya }; 2398897f325SBhaskar Upadhaya 2408897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2418897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2428897f325SBhaskar Upadhaya #address-cells = <1>; 2438897f325SBhaskar Upadhaya #size-cells = <0>; 2448897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2458897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 246ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2478897f325SBhaskar Upadhaya status = "disabled"; 2488897f325SBhaskar Upadhaya }; 2498897f325SBhaskar Upadhaya 2508897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2518897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2528897f325SBhaskar Upadhaya #address-cells = <1>; 2538897f325SBhaskar Upadhaya #size-cells = <0>; 2548897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2558897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 256ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2578897f325SBhaskar Upadhaya status = "disabled"; 2588897f325SBhaskar Upadhaya }; 2598897f325SBhaskar Upadhaya 2608897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2618897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2628897f325SBhaskar Upadhaya #address-cells = <1>; 2638897f325SBhaskar Upadhaya #size-cells = <0>; 2648897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2658897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 266ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2678897f325SBhaskar Upadhaya status = "disabled"; 2688897f325SBhaskar Upadhaya }; 2698897f325SBhaskar Upadhaya 2708897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2718897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2728897f325SBhaskar Upadhaya #address-cells = <1>; 2738897f325SBhaskar Upadhaya #size-cells = <0>; 2748897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2758897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 276ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2778897f325SBhaskar Upadhaya status = "disabled"; 2788897f325SBhaskar Upadhaya }; 2798897f325SBhaskar Upadhaya 2808897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2818897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2828897f325SBhaskar Upadhaya #address-cells = <1>; 2838897f325SBhaskar Upadhaya #size-cells = <0>; 2848897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2858897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 286ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2878897f325SBhaskar Upadhaya status = "disabled"; 2888897f325SBhaskar Upadhaya }; 2898897f325SBhaskar Upadhaya 2908897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2918897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2928897f325SBhaskar Upadhaya #address-cells = <1>; 2938897f325SBhaskar Upadhaya #size-cells = <0>; 2948897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2958897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 296ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2978897f325SBhaskar Upadhaya status = "disabled"; 2988897f325SBhaskar Upadhaya }; 2998897f325SBhaskar Upadhaya 300c77fae5bSAshish Kumar fspi: spi@20c0000 { 301c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 302c77fae5bSAshish Kumar #address-cells = <1>; 303c77fae5bSAshish Kumar #size-cells = <0>; 304c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 305c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 306c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 307c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 308c77fae5bSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 309c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 310c77fae5bSAshish Kumar status = "disabled"; 311c77fae5bSAshish Kumar }; 312c77fae5bSAshish Kumar 313c2d35adaSMichael Walle dspi0: spi@2100000 { 314c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 315c2d35adaSMichael Walle #address-cells = <1>; 316c2d35adaSMichael Walle #size-cells = <0>; 317c2d35adaSMichael Walle reg = <0x0 0x2100000 0x0 0x10000>; 318c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 319c2d35adaSMichael Walle clock-names = "dspi"; 320c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 321dd12fa69SVladimir Oltean dmas = <&edma0 0 62>, <&edma0 0 60>; 322dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 323c2d35adaSMichael Walle spi-num-chipselects = <4>; 324c2d35adaSMichael Walle little-endian; 325c2d35adaSMichael Walle status = "disabled"; 326c2d35adaSMichael Walle }; 327c2d35adaSMichael Walle 328c2d35adaSMichael Walle dspi1: spi@2110000 { 329c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 330c2d35adaSMichael Walle #address-cells = <1>; 331c2d35adaSMichael Walle #size-cells = <0>; 332c2d35adaSMichael Walle reg = <0x0 0x2110000 0x0 0x10000>; 333c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 334c2d35adaSMichael Walle clock-names = "dspi"; 335c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 336dd12fa69SVladimir Oltean dmas = <&edma0 0 58>, <&edma0 0 56>; 337dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 338c2d35adaSMichael Walle spi-num-chipselects = <4>; 339c2d35adaSMichael Walle little-endian; 340c2d35adaSMichael Walle status = "disabled"; 341c2d35adaSMichael Walle }; 342c2d35adaSMichael Walle 343c2d35adaSMichael Walle dspi2: spi@2120000 { 344c2d35adaSMichael Walle compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 345c2d35adaSMichael Walle #address-cells = <1>; 346c2d35adaSMichael Walle #size-cells = <0>; 347c2d35adaSMichael Walle reg = <0x0 0x2120000 0x0 0x10000>; 348c2d35adaSMichael Walle interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 349c2d35adaSMichael Walle clock-names = "dspi"; 350c2d35adaSMichael Walle clocks = <&clockgen 4 1>; 351dd12fa69SVladimir Oltean dmas = <&edma0 0 54>, <&edma0 0 2>; 352dd12fa69SVladimir Oltean dma-names = "tx", "rx"; 353c2d35adaSMichael Walle spi-num-chipselects = <3>; 354c2d35adaSMichael Walle little-endian; 355c2d35adaSMichael Walle status = "disabled"; 356c2d35adaSMichael Walle }; 357c2d35adaSMichael Walle 358491d3a3fSAshish Kumar esdhc: mmc@2140000 { 359491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 360491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 361491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 362491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 363491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 364491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 365491d3a3fSAshish Kumar sdhci,auto-cmd12; 366491d3a3fSAshish Kumar little-endian; 367491d3a3fSAshish Kumar bus-width = <4>; 368491d3a3fSAshish Kumar status = "disabled"; 369491d3a3fSAshish Kumar }; 370491d3a3fSAshish Kumar 371491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 372491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 373491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 374491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 375491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 376491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 377491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 378491d3a3fSAshish Kumar sdhci,auto-cmd12; 379491d3a3fSAshish Kumar broken-cd; 380491d3a3fSAshish Kumar little-endian; 381491d3a3fSAshish Kumar bus-width = <4>; 382491d3a3fSAshish Kumar status = "disabled"; 383491d3a3fSAshish Kumar }; 384491d3a3fSAshish Kumar 3858897f325SBhaskar Upadhaya duart0: serial@21c0500 { 3868897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3878897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 3888897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3898897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3908897f325SBhaskar Upadhaya status = "disabled"; 3918897f325SBhaskar Upadhaya }; 3928897f325SBhaskar Upadhaya 3938897f325SBhaskar Upadhaya duart1: serial@21c0600 { 3948897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3958897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 3968897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3978897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3988897f325SBhaskar Upadhaya status = "disabled"; 3998897f325SBhaskar Upadhaya }; 4008897f325SBhaskar Upadhaya 4012607d724SMichael Walle 4022607d724SMichael Walle lpuart0: serial@2260000 { 4032607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4042607d724SMichael Walle reg = <0x0 0x2260000 0x0 0x1000>; 4052607d724SMichael Walle interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 4062607d724SMichael Walle clocks = <&clockgen 4 1>; 4072607d724SMichael Walle clock-names = "ipg"; 4082607d724SMichael Walle dma-names = "rx","tx"; 4092607d724SMichael Walle dmas = <&edma0 1 32>, 4102607d724SMichael Walle <&edma0 1 33>; 4112607d724SMichael Walle status = "disabled"; 4122607d724SMichael Walle }; 4132607d724SMichael Walle 4142607d724SMichael Walle lpuart1: serial@2270000 { 4152607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4162607d724SMichael Walle reg = <0x0 0x2270000 0x0 0x1000>; 4172607d724SMichael Walle interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 4182607d724SMichael Walle clocks = <&clockgen 4 1>; 4192607d724SMichael Walle clock-names = "ipg"; 4202607d724SMichael Walle dma-names = "rx","tx"; 4212607d724SMichael Walle dmas = <&edma0 1 30>, 4222607d724SMichael Walle <&edma0 1 31>; 4232607d724SMichael Walle status = "disabled"; 4242607d724SMichael Walle }; 4252607d724SMichael Walle 4262607d724SMichael Walle lpuart2: serial@2280000 { 4272607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4282607d724SMichael Walle reg = <0x0 0x2280000 0x0 0x1000>; 4292607d724SMichael Walle interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 4302607d724SMichael Walle clocks = <&clockgen 4 1>; 4312607d724SMichael Walle clock-names = "ipg"; 4322607d724SMichael Walle dma-names = "rx","tx"; 4332607d724SMichael Walle dmas = <&edma0 1 28>, 4342607d724SMichael Walle <&edma0 1 29>; 4352607d724SMichael Walle status = "disabled"; 4362607d724SMichael Walle }; 4372607d724SMichael Walle 4382607d724SMichael Walle lpuart3: serial@2290000 { 4392607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4402607d724SMichael Walle reg = <0x0 0x2290000 0x0 0x1000>; 4412607d724SMichael Walle interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 4422607d724SMichael Walle clocks = <&clockgen 4 1>; 4432607d724SMichael Walle clock-names = "ipg"; 4442607d724SMichael Walle dma-names = "rx","tx"; 4452607d724SMichael Walle dmas = <&edma0 1 26>, 4462607d724SMichael Walle <&edma0 1 27>; 4472607d724SMichael Walle status = "disabled"; 4482607d724SMichael Walle }; 4492607d724SMichael Walle 4502607d724SMichael Walle lpuart4: serial@22a0000 { 4512607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4522607d724SMichael Walle reg = <0x0 0x22a0000 0x0 0x1000>; 4532607d724SMichael Walle interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 4542607d724SMichael Walle clocks = <&clockgen 4 1>; 4552607d724SMichael Walle clock-names = "ipg"; 4562607d724SMichael Walle dma-names = "rx","tx"; 4572607d724SMichael Walle dmas = <&edma0 1 24>, 4582607d724SMichael Walle <&edma0 1 25>; 4592607d724SMichael Walle status = "disabled"; 4602607d724SMichael Walle }; 4612607d724SMichael Walle 4622607d724SMichael Walle lpuart5: serial@22b0000 { 4632607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 4642607d724SMichael Walle reg = <0x0 0x22b0000 0x0 0x1000>; 4652607d724SMichael Walle interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 4662607d724SMichael Walle clocks = <&clockgen 4 1>; 4672607d724SMichael Walle clock-names = "ipg"; 4682607d724SMichael Walle dma-names = "rx","tx"; 4692607d724SMichael Walle dmas = <&edma0 1 22>, 4702607d724SMichael Walle <&edma0 1 23>; 4712607d724SMichael Walle status = "disabled"; 4722607d724SMichael Walle }; 4732607d724SMichael Walle 474f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 475f54f7be5SAlison Wang #dma-cells = <2>; 476e0d7856eSMichael Walle compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 477f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 478f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 479f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 480f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 481f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 482f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 483f54f7be5SAlison Wang dma-channels = <32>; 484f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 485f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 486f54f7be5SAlison Wang <&clockgen 4 1>; 487f54f7be5SAlison Wang }; 488f54f7be5SAlison Wang 4898897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 490f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4918897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 4928897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 4938897f325SBhaskar Upadhaya gpio-controller; 4948897f325SBhaskar Upadhaya #gpio-cells = <2>; 4958897f325SBhaskar Upadhaya interrupt-controller; 4968897f325SBhaskar Upadhaya #interrupt-cells = <2>; 497f64697bdSSong Hui little-endian; 4988897f325SBhaskar Upadhaya }; 4998897f325SBhaskar Upadhaya 5008897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 501f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5028897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 5038897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 5048897f325SBhaskar Upadhaya gpio-controller; 5058897f325SBhaskar Upadhaya #gpio-cells = <2>; 5068897f325SBhaskar Upadhaya interrupt-controller; 5078897f325SBhaskar Upadhaya #interrupt-cells = <2>; 508f64697bdSSong Hui little-endian; 5098897f325SBhaskar Upadhaya }; 5108897f325SBhaskar Upadhaya 5118897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 512f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 5138897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 5148897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 5158897f325SBhaskar Upadhaya gpio-controller; 5168897f325SBhaskar Upadhaya #gpio-cells = <2>; 5178897f325SBhaskar Upadhaya interrupt-controller; 5188897f325SBhaskar Upadhaya #interrupt-cells = <2>; 519f64697bdSSong Hui little-endian; 5208897f325SBhaskar Upadhaya }; 5218897f325SBhaskar Upadhaya 522c92f56faSRan Wang usb0: usb@3100000 { 523c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 524c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 525c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 526c92f56faSRan Wang dr_mode = "host"; 527c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 528c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 529c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 530c92f56faSRan Wang }; 531c92f56faSRan Wang 532c92f56faSRan Wang usb1: usb@3110000 { 533c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 534c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 535c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 536c92f56faSRan Wang dr_mode = "host"; 537c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 538c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 539c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 5408897f325SBhaskar Upadhaya }; 5418897f325SBhaskar Upadhaya 5428897f325SBhaskar Upadhaya sata: sata@3200000 { 5438897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 5448897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 5453f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 5468897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 5478897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 5488897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 5498897f325SBhaskar Upadhaya status = "disabled"; 5508897f325SBhaskar Upadhaya }; 5518897f325SBhaskar Upadhaya 552f6ff3f6dSXiaowei Bao pcie@3400000 { 553f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 554f6ff3f6dSXiaowei Bao reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 555f6ff3f6dSXiaowei Bao 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 556f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 557f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 558f6ff3f6dSXiaowei Bao <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 559f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 560f6ff3f6dSXiaowei Bao #address-cells = <3>; 561f6ff3f6dSXiaowei Bao #size-cells = <2>; 562f6ff3f6dSXiaowei Bao device_type = "pci"; 563f6ff3f6dSXiaowei Bao dma-coherent; 564f6ff3f6dSXiaowei Bao num-viewport = <8>; 565f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 566f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 567f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 568f6ff3f6dSXiaowei Bao msi-parent = <&its>; 569f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 570f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 571f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 572f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 573f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 574f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 575f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 576f6ff3f6dSXiaowei Bao status = "disabled"; 577f6ff3f6dSXiaowei Bao }; 578f6ff3f6dSXiaowei Bao 579f6ff3f6dSXiaowei Bao pcie@3500000 { 580f6ff3f6dSXiaowei Bao compatible = "fsl,ls1028a-pcie"; 581f6ff3f6dSXiaowei Bao reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 582f6ff3f6dSXiaowei Bao 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 583f6ff3f6dSXiaowei Bao reg-names = "regs", "config"; 584f6ff3f6dSXiaowei Bao interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 585f6ff3f6dSXiaowei Bao <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 586f6ff3f6dSXiaowei Bao interrupt-names = "pme", "aer"; 587f6ff3f6dSXiaowei Bao #address-cells = <3>; 588f6ff3f6dSXiaowei Bao #size-cells = <2>; 589f6ff3f6dSXiaowei Bao device_type = "pci"; 590f6ff3f6dSXiaowei Bao dma-coherent; 591f6ff3f6dSXiaowei Bao num-viewport = <8>; 592f6ff3f6dSXiaowei Bao bus-range = <0x0 0xff>; 593f6ff3f6dSXiaowei Bao ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 594f6ff3f6dSXiaowei Bao 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 595f6ff3f6dSXiaowei Bao msi-parent = <&its>; 596f6ff3f6dSXiaowei Bao #interrupt-cells = <1>; 597f6ff3f6dSXiaowei Bao interrupt-map-mask = <0 0 0 7>; 598f6ff3f6dSXiaowei Bao interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 599f6ff3f6dSXiaowei Bao <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 600f6ff3f6dSXiaowei Bao <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 601f6ff3f6dSXiaowei Bao <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 602f6ff3f6dSXiaowei Bao iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 603f6ff3f6dSXiaowei Bao status = "disabled"; 604f6ff3f6dSXiaowei Bao }; 605f6ff3f6dSXiaowei Bao 6068897f325SBhaskar Upadhaya smmu: iommu@5000000 { 6078897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 6088897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 6098897f325SBhaskar Upadhaya #global-interrupts = <8>; 6108897f325SBhaskar Upadhaya #iommu-cells = <1>; 6118897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 6128897f325SBhaskar Upadhaya /* global secure fault */ 6138897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 6148897f325SBhaskar Upadhaya /* combined secure interrupt */ 6158897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 6168897f325SBhaskar Upadhaya /* global non-secure fault */ 6178897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 6188897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 6198897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 6208897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 6218897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 6228897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 6238897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 6248897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6258897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6268897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 6278897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 6288897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 6298897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 6308897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 6318897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 6328897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 6338897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 6348897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 6358897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 6368897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 6378897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 6388897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 6398897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 6408897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 6418897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6428897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6438897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6448897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6458897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6468897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6478897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 6488897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 6498897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 6508897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 6518897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 6528897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 6538897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 6548897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 6558897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 6568897f325SBhaskar Upadhaya }; 657927d7f85SClaudiu Manoil 6581d0becabSHoria Geantă crypto: crypto@8000000 { 6591d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 6601d0becabSHoria Geantă fsl,sec-era = <10>; 6611d0becabSHoria Geantă #address-cells = <1>; 6621d0becabSHoria Geantă #size-cells = <1>; 6631d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 6641d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 6651d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 6661d0becabSHoria Geantă dma-coherent; 6671d0becabSHoria Geantă 6681d0becabSHoria Geantă sec_jr0: jr@10000 { 6691d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6701d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6711d0becabSHoria Geantă reg = <0x10000 0x10000>; 6721d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 6731d0becabSHoria Geantă }; 6741d0becabSHoria Geantă 6751d0becabSHoria Geantă sec_jr1: jr@20000 { 6761d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6771d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6781d0becabSHoria Geantă reg = <0x20000 0x10000>; 6791d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 6801d0becabSHoria Geantă }; 6811d0becabSHoria Geantă 6821d0becabSHoria Geantă sec_jr2: jr@30000 { 6831d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6841d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6851d0becabSHoria Geantă reg = <0x30000 0x10000>; 6861d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 6871d0becabSHoria Geantă }; 6881d0becabSHoria Geantă 6891d0becabSHoria Geantă sec_jr3: jr@40000 { 6901d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 6911d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 6921d0becabSHoria Geantă reg = <0x40000 0x10000>; 6931d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 6941d0becabSHoria Geantă }; 6951d0becabSHoria Geantă }; 6961d0becabSHoria Geantă 6977802f88dSPeng Ma qdma: dma-controller@8380000 { 6987802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 6997802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 7007802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 7017802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 7027802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 7037802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 7047802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 7057802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 7067802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 7077802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 7087802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 7097802f88dSPeng Ma dma-channels = <8>; 7107802f88dSPeng Ma block-number = <1>; 7117802f88dSPeng Ma block-offset = <0x10000>; 7127802f88dSPeng Ma fsl,dma-queues = <2>; 7137802f88dSPeng Ma status-sizes = <64>; 7147802f88dSPeng Ma queue-sizes = <64 64>; 7157802f88dSPeng Ma }; 7167802f88dSPeng Ma 71757aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 71857aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 71957aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 72057aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 72157aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 72257aa1bc7SChuanhua Han }; 72357aa1bc7SChuanhua Han 72457aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 72557aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 72657aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 72757aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 72857aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 72957aa1bc7SChuanhua Han }; 73057aa1bc7SChuanhua Han 731f54f7be5SAlison Wang sai1: audio-controller@f100000 { 732f54f7be5SAlison Wang #sound-dai-cells = <0>; 733f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 734f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 735f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 736f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 737f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 738f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 739f54f7be5SAlison Wang dma-names = "tx", "rx"; 740f54f7be5SAlison Wang dmas = <&edma0 1 4>, 741f54f7be5SAlison Wang <&edma0 1 3>; 7429c015e13SMichael Walle fsl,sai-asynchronous; 743f54f7be5SAlison Wang status = "disabled"; 744f54f7be5SAlison Wang }; 745f54f7be5SAlison Wang 746f54f7be5SAlison Wang sai2: audio-controller@f110000 { 747f54f7be5SAlison Wang #sound-dai-cells = <0>; 748f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 749f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 750f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 751f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 752f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 753f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 754f54f7be5SAlison Wang dma-names = "tx", "rx"; 755f54f7be5SAlison Wang dmas = <&edma0 1 6>, 756f54f7be5SAlison Wang <&edma0 1 5>; 7579c015e13SMichael Walle fsl,sai-asynchronous; 758f54f7be5SAlison Wang status = "disabled"; 759f54f7be5SAlison Wang }; 760f54f7be5SAlison Wang 761434f9cc1SMichael Walle sai3: audio-controller@f120000 { 762434f9cc1SMichael Walle #sound-dai-cells = <0>; 763434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 764434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 765434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 766434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 767434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 768434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 769434f9cc1SMichael Walle dma-names = "tx", "rx"; 770434f9cc1SMichael Walle dmas = <&edma0 1 8>, 771434f9cc1SMichael Walle <&edma0 1 7>; 7729c015e13SMichael Walle fsl,sai-asynchronous; 773f54f7be5SAlison Wang status = "disabled"; 774f54f7be5SAlison Wang }; 775f54f7be5SAlison Wang 776f54f7be5SAlison Wang sai4: audio-controller@f130000 { 777f54f7be5SAlison Wang #sound-dai-cells = <0>; 778f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 779f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 780f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 781f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 782f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 783f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 784f54f7be5SAlison Wang dma-names = "tx", "rx"; 785f54f7be5SAlison Wang dmas = <&edma0 1 10>, 786f54f7be5SAlison Wang <&edma0 1 9>; 7879c015e13SMichael Walle fsl,sai-asynchronous; 788f54f7be5SAlison Wang status = "disabled"; 789f54f7be5SAlison Wang }; 790f54f7be5SAlison Wang 791434f9cc1SMichael Walle sai5: audio-controller@f140000 { 792434f9cc1SMichael Walle #sound-dai-cells = <0>; 793434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 794434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 795434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 796434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 797434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 798434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 799434f9cc1SMichael Walle dma-names = "tx", "rx"; 800434f9cc1SMichael Walle dmas = <&edma0 1 12>, 801434f9cc1SMichael Walle <&edma0 1 11>; 8029c015e13SMichael Walle fsl,sai-asynchronous; 803434f9cc1SMichael Walle status = "disabled"; 804434f9cc1SMichael Walle }; 805434f9cc1SMichael Walle 806434f9cc1SMichael Walle sai6: audio-controller@f150000 { 807434f9cc1SMichael Walle #sound-dai-cells = <0>; 808434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 809434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 810434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 811434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 812434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 813434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 814434f9cc1SMichael Walle dma-names = "tx", "rx"; 815434f9cc1SMichael Walle dmas = <&edma0 1 14>, 816434f9cc1SMichael Walle <&edma0 1 13>; 8179c015e13SMichael Walle fsl,sai-asynchronous; 8188897f325SBhaskar Upadhaya status = "disabled"; 8198897f325SBhaskar Upadhaya }; 8208897f325SBhaskar Upadhaya 8210b680963SFabio Estevam tmu: tmu@1f80000 { 822571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 823571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 824571cebfeSYuantian Tang interrupts = <0 23 0x4>; 825571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 826571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 827571cebfeSYuantian Tang 0x00000001 0x0000002b 828571cebfeSYuantian Tang 0x00000002 0x00000031 829571cebfeSYuantian Tang 0x00000003 0x00000038 830571cebfeSYuantian Tang 0x00000004 0x0000003f 831571cebfeSYuantian Tang 0x00000005 0x00000045 832571cebfeSYuantian Tang 0x00000006 0x0000004c 833571cebfeSYuantian Tang 0x00000007 0x00000053 834571cebfeSYuantian Tang 0x00000008 0x00000059 835571cebfeSYuantian Tang 0x00000009 0x00000060 836571cebfeSYuantian Tang 0x0000000a 0x00000066 837571cebfeSYuantian Tang 0x0000000b 0x0000006d 838571cebfeSYuantian Tang 839571cebfeSYuantian Tang 0x00010000 0x0000001c 840571cebfeSYuantian Tang 0x00010001 0x00000024 841571cebfeSYuantian Tang 0x00010002 0x0000002c 842571cebfeSYuantian Tang 0x00010003 0x00000035 843571cebfeSYuantian Tang 0x00010004 0x0000003d 844571cebfeSYuantian Tang 0x00010005 0x00000045 845571cebfeSYuantian Tang 0x00010006 0x0000004d 846961f8209SMichael Walle 0x00010007 0x00000055 847571cebfeSYuantian Tang 0x00010008 0x0000005e 848571cebfeSYuantian Tang 0x00010009 0x00000066 849571cebfeSYuantian Tang 0x0001000a 0x0000006e 850571cebfeSYuantian Tang 851571cebfeSYuantian Tang 0x00020000 0x00000018 852571cebfeSYuantian Tang 0x00020001 0x00000022 853571cebfeSYuantian Tang 0x00020002 0x0000002d 854571cebfeSYuantian Tang 0x00020003 0x00000038 855571cebfeSYuantian Tang 0x00020004 0x00000043 856571cebfeSYuantian Tang 0x00020005 0x0000004d 857571cebfeSYuantian Tang 0x00020006 0x00000058 858571cebfeSYuantian Tang 0x00020007 0x00000063 859571cebfeSYuantian Tang 0x00020008 0x0000006e 860571cebfeSYuantian Tang 861571cebfeSYuantian Tang 0x00030000 0x00000010 862571cebfeSYuantian Tang 0x00030001 0x0000001c 863571cebfeSYuantian Tang 0x00030002 0x00000029 864571cebfeSYuantian Tang 0x00030003 0x00000036 865571cebfeSYuantian Tang 0x00030004 0x00000042 866571cebfeSYuantian Tang 0x00030005 0x0000004f 867571cebfeSYuantian Tang 0x00030006 0x0000005b 868571cebfeSYuantian Tang 0x00030007 0x00000068>; 869571cebfeSYuantian Tang little-endian; 870571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 871571cebfeSYuantian Tang }; 872571cebfeSYuantian Tang 8738897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 8748897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 8758897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 8768897f325SBhaskar Upadhaya #address-cells = <3>; 8778897f325SBhaskar Upadhaya #size-cells = <2>; 8788897f325SBhaskar Upadhaya msi-parent = <&its>; 8798897f325SBhaskar Upadhaya device_type = "pci"; 8808897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 8818897f325SBhaskar Upadhaya dma-coherent; 8828897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 8838897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 8848897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 8858897f325SBhaskar Upadhaya ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 8868897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 8878897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 8888897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 8898897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 8908897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 8918897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 8928897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 8938897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 8948897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 895b1520d8bSClaudiu Manoil 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000 896b1520d8bSClaudiu Manoil /* BAR4 (PF5) - non-prefetchable memory */ 897b1520d8bSClaudiu Manoil 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>; 8988897f325SBhaskar Upadhaya 8998897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 9008897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 9018897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 9021a4bfe0fSVladimir Oltean status = "disabled"; 9038897f325SBhaskar Upadhaya }; 9041a4bfe0fSVladimir Oltean 9058897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 9068897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 9078897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 9081a4bfe0fSVladimir Oltean status = "disabled"; 9098897f325SBhaskar Upadhaya }; 9101a4bfe0fSVladimir Oltean 911b1520d8bSClaudiu Manoil enetc_port2: ethernet@0,2 { 912b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 913b1520d8bSClaudiu Manoil reg = <0x000200 0 0 0 0>; 914b1520d8bSClaudiu Manoil phy-mode = "internal"; 915b1520d8bSClaudiu Manoil status = "disabled"; 916b1520d8bSClaudiu Manoil 917b1520d8bSClaudiu Manoil fixed-link { 918b1520d8bSClaudiu Manoil speed = <1000>; 919b1520d8bSClaudiu Manoil full-duplex; 920b1520d8bSClaudiu Manoil }; 921b1520d8bSClaudiu Manoil }; 922b1520d8bSClaudiu Manoil 9238488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 9248488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 9258488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 9268488d8e9SClaudiu Manoil #address-cells = <1>; 9278488d8e9SClaudiu Manoil #size-cells = <0>; 9288488d8e9SClaudiu Manoil }; 9291a4bfe0fSVladimir Oltean 93049401003SY.b. Lu ethernet@0,4 { 93149401003SY.b. Lu compatible = "fsl,enetc-ptp"; 93249401003SY.b. Lu reg = <0x000400 0 0 0 0>; 93349401003SY.b. Lu clocks = <&clockgen 4 0>; 93449401003SY.b. Lu little-endian; 935ab84bad5SYangbo Lu fsl,extts-fifo; 93649401003SY.b. Lu }; 937b1520d8bSClaudiu Manoil 938630952e1SMichael Walle mscc_felix: ethernet-switch@0,5 { 939b1520d8bSClaudiu Manoil reg = <0x000500 0 0 0 0>; 940b1520d8bSClaudiu Manoil /* IEP INT_B */ 941b1520d8bSClaudiu Manoil interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 942630952e1SMichael Walle status = "disabled"; 943b1520d8bSClaudiu Manoil 944b1520d8bSClaudiu Manoil ports { 945b1520d8bSClaudiu Manoil #address-cells = <1>; 946b1520d8bSClaudiu Manoil #size-cells = <0>; 947b1520d8bSClaudiu Manoil 948b1520d8bSClaudiu Manoil /* External ports */ 949b1520d8bSClaudiu Manoil mscc_felix_port0: port@0 { 950b1520d8bSClaudiu Manoil reg = <0>; 951b1520d8bSClaudiu Manoil status = "disabled"; 952b1520d8bSClaudiu Manoil }; 953b1520d8bSClaudiu Manoil 954b1520d8bSClaudiu Manoil mscc_felix_port1: port@1 { 955b1520d8bSClaudiu Manoil reg = <1>; 956b1520d8bSClaudiu Manoil status = "disabled"; 957b1520d8bSClaudiu Manoil }; 958b1520d8bSClaudiu Manoil 959b1520d8bSClaudiu Manoil mscc_felix_port2: port@2 { 960b1520d8bSClaudiu Manoil reg = <2>; 961b1520d8bSClaudiu Manoil status = "disabled"; 962b1520d8bSClaudiu Manoil }; 963b1520d8bSClaudiu Manoil 964b1520d8bSClaudiu Manoil mscc_felix_port3: port@3 { 965b1520d8bSClaudiu Manoil reg = <3>; 966b1520d8bSClaudiu Manoil status = "disabled"; 967b1520d8bSClaudiu Manoil }; 968b1520d8bSClaudiu Manoil 969b1520d8bSClaudiu Manoil /* Internal ports */ 970b1520d8bSClaudiu Manoil mscc_felix_port4: port@4 { 971b1520d8bSClaudiu Manoil reg = <4>; 972b1520d8bSClaudiu Manoil phy-mode = "internal"; 973b1520d8bSClaudiu Manoil status = "disabled"; 974b1520d8bSClaudiu Manoil 975b1520d8bSClaudiu Manoil fixed-link { 976b1520d8bSClaudiu Manoil speed = <2500>; 977b1520d8bSClaudiu Manoil full-duplex; 978b1520d8bSClaudiu Manoil }; 979b1520d8bSClaudiu Manoil }; 980b1520d8bSClaudiu Manoil 981b1520d8bSClaudiu Manoil mscc_felix_port5: port@5 { 982b1520d8bSClaudiu Manoil reg = <5>; 983b1520d8bSClaudiu Manoil phy-mode = "internal"; 984b1520d8bSClaudiu Manoil status = "disabled"; 985b1520d8bSClaudiu Manoil 986b1520d8bSClaudiu Manoil fixed-link { 987b1520d8bSClaudiu Manoil speed = <1000>; 988b1520d8bSClaudiu Manoil full-duplex; 989b1520d8bSClaudiu Manoil }; 990b1520d8bSClaudiu Manoil }; 991b1520d8bSClaudiu Manoil }; 992b1520d8bSClaudiu Manoil }; 993b1520d8bSClaudiu Manoil 994b1520d8bSClaudiu Manoil enetc_port3: ethernet@0,6 { 995b1520d8bSClaudiu Manoil compatible = "fsl,enetc"; 996b1520d8bSClaudiu Manoil reg = <0x000600 0 0 0 0>; 997b1520d8bSClaudiu Manoil phy-mode = "internal"; 998b1520d8bSClaudiu Manoil status = "disabled"; 999b1520d8bSClaudiu Manoil 1000b1520d8bSClaudiu Manoil fixed-link { 1001b1520d8bSClaudiu Manoil speed = <1000>; 1002b1520d8bSClaudiu Manoil full-duplex; 1003b1520d8bSClaudiu Manoil }; 10048897f325SBhaskar Upadhaya }; 10058897f325SBhaskar Upadhaya }; 10068897f325SBhaskar Upadhaya }; 10077f538f19SWen He 10087f538f19SWen He malidp0: display@f080000 { 10097f538f19SWen He compatible = "arm,mali-dp500"; 10107f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 10117f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 10127f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 10137f538f19SWen He interrupt-names = "DE", "SE"; 101491035cb0SWen He clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 101513782597SWen He <&clockgen 2 2>; 10167f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 10177f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 10183a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 10197f538f19SWen He 10207f538f19SWen He port { 10217f538f19SWen He dp0_out: endpoint { 10227f538f19SWen He 10237f538f19SWen He }; 10247f538f19SWen He }; 10257f538f19SWen He }; 10268897f325SBhaskar Upadhaya}; 1027