18897f325SBhaskar Upadhaya// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28897f325SBhaskar Upadhaya/* 38897f325SBhaskar Upadhaya * Device Tree Include file for NXP Layerscape-1028A family SoC. 48897f325SBhaskar Upadhaya * 58897f325SBhaskar Upadhaya * Copyright 2018 NXP 68897f325SBhaskar Upadhaya * 78897f325SBhaskar Upadhaya * Harninder Rai <harninder.rai@nxp.com> 88897f325SBhaskar Upadhaya * 98897f325SBhaskar Upadhaya */ 108897f325SBhaskar Upadhaya 118897f325SBhaskar Upadhaya#include <dt-bindings/interrupt-controller/arm-gic.h> 128897f325SBhaskar Upadhaya#include <dt-bindings/thermal/thermal.h> 138897f325SBhaskar Upadhaya 148897f325SBhaskar Upadhaya/ { 158897f325SBhaskar Upadhaya compatible = "fsl,ls1028a"; 168897f325SBhaskar Upadhaya interrupt-parent = <&gic>; 178897f325SBhaskar Upadhaya #address-cells = <2>; 188897f325SBhaskar Upadhaya #size-cells = <2>; 198897f325SBhaskar Upadhaya 208897f325SBhaskar Upadhaya cpus { 218897f325SBhaskar Upadhaya #address-cells = <1>; 228897f325SBhaskar Upadhaya #size-cells = <0>; 238897f325SBhaskar Upadhaya 248897f325SBhaskar Upadhaya cpu0: cpu@0 { 258897f325SBhaskar Upadhaya device_type = "cpu"; 268897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 278897f325SBhaskar Upadhaya reg = <0x0>; 288897f325SBhaskar Upadhaya enable-method = "psci"; 298897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 308897f325SBhaskar Upadhaya next-level-cache = <&l2>; 3153f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 32571cebfeSYuantian Tang #cooling-cells = <2>; 338897f325SBhaskar Upadhaya }; 348897f325SBhaskar Upadhaya 358897f325SBhaskar Upadhaya cpu1: cpu@1 { 368897f325SBhaskar Upadhaya device_type = "cpu"; 378897f325SBhaskar Upadhaya compatible = "arm,cortex-a72"; 388897f325SBhaskar Upadhaya reg = <0x1>; 398897f325SBhaskar Upadhaya enable-method = "psci"; 408897f325SBhaskar Upadhaya clocks = <&clockgen 1 0>; 418897f325SBhaskar Upadhaya next-level-cache = <&l2>; 4253f2ac9dSRan Wang cpu-idle-states = <&CPU_PW20>; 43571cebfeSYuantian Tang #cooling-cells = <2>; 448897f325SBhaskar Upadhaya }; 458897f325SBhaskar Upadhaya 468897f325SBhaskar Upadhaya l2: l2-cache { 478897f325SBhaskar Upadhaya compatible = "cache"; 488897f325SBhaskar Upadhaya }; 498897f325SBhaskar Upadhaya }; 508897f325SBhaskar Upadhaya 518897f325SBhaskar Upadhaya idle-states { 528897f325SBhaskar Upadhaya /* 538897f325SBhaskar Upadhaya * PSCI node is not added default, U-boot will add missing 548897f325SBhaskar Upadhaya * parts if it determines to use PSCI. 558897f325SBhaskar Upadhaya */ 568897f325SBhaskar Upadhaya entry-method = "arm,psci"; 578897f325SBhaskar Upadhaya 5853f2ac9dSRan Wang CPU_PW20: cpu-pw20 { 598897f325SBhaskar Upadhaya compatible = "arm,idle-state"; 6053f2ac9dSRan Wang idle-state-name = "PW20"; 6153f2ac9dSRan Wang arm,psci-suspend-param = <0x0>; 6253f2ac9dSRan Wang entry-latency-us = <2000>; 6353f2ac9dSRan Wang exit-latency-us = <2000>; 6453f2ac9dSRan Wang min-residency-us = <6000>; 658897f325SBhaskar Upadhaya }; 668897f325SBhaskar Upadhaya }; 678897f325SBhaskar Upadhaya 688897f325SBhaskar Upadhaya sysclk: clock-sysclk { 698897f325SBhaskar Upadhaya compatible = "fixed-clock"; 708897f325SBhaskar Upadhaya #clock-cells = <0>; 718897f325SBhaskar Upadhaya clock-frequency = <100000000>; 728897f325SBhaskar Upadhaya clock-output-names = "sysclk"; 738897f325SBhaskar Upadhaya }; 748897f325SBhaskar Upadhaya 7581f36887SWen He osc_27m: clock-osc-27m { 767f538f19SWen He compatible = "fixed-clock"; 777f538f19SWen He #clock-cells = <0>; 787f538f19SWen He clock-frequency = <27000000>; 7981f36887SWen He clock-output-names = "phy_27m"; 8081f36887SWen He }; 8181f36887SWen He 8281f36887SWen He dpclk: clock-controller@f1f0000 { 8381f36887SWen He compatible = "fsl,ls1028a-plldig"; 8481f36887SWen He reg = <0x0 0xf1f0000 0x0 0xffff>; 8591035cb0SWen He #clock-cells = <0>; 8681f36887SWen He clocks = <&osc_27m>; 877f538f19SWen He }; 887f538f19SWen He 898897f325SBhaskar Upadhaya reboot { 908897f325SBhaskar Upadhaya compatible ="syscon-reboot"; 913f0fb37bSMichael Walle regmap = <&rst>; 928897f325SBhaskar Upadhaya offset = <0xb0>; 938897f325SBhaskar Upadhaya mask = <0x02>; 948897f325SBhaskar Upadhaya }; 958897f325SBhaskar Upadhaya 968897f325SBhaskar Upadhaya timer { 978897f325SBhaskar Upadhaya compatible = "arm,armv8-timer"; 988897f325SBhaskar Upadhaya interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 998897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1008897f325SBhaskar Upadhaya <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 1018897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1028897f325SBhaskar Upadhaya <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 1038897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>, 1048897f325SBhaskar Upadhaya <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 1058897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1068897f325SBhaskar Upadhaya }; 1078897f325SBhaskar Upadhaya 108b9eb314aSAlison Wang pmu { 109b9eb314aSAlison Wang compatible = "arm,cortex-a72-pmu"; 110b9eb314aSAlison Wang interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111b9eb314aSAlison Wang }; 112b9eb314aSAlison Wang 1138897f325SBhaskar Upadhaya gic: interrupt-controller@6000000 { 1148897f325SBhaskar Upadhaya compatible= "arm,gic-v3"; 1158897f325SBhaskar Upadhaya #address-cells = <2>; 1168897f325SBhaskar Upadhaya #size-cells = <2>; 1178897f325SBhaskar Upadhaya ranges; 1188897f325SBhaskar Upadhaya reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1198897f325SBhaskar Upadhaya <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 1208897f325SBhaskar Upadhaya #interrupt-cells= <3>; 1218897f325SBhaskar Upadhaya interrupt-controller; 1228897f325SBhaskar Upadhaya interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 1238897f325SBhaskar Upadhaya IRQ_TYPE_LEVEL_LOW)>; 1248897f325SBhaskar Upadhaya its: gic-its@6020000 { 1258897f325SBhaskar Upadhaya compatible = "arm,gic-v3-its"; 1268897f325SBhaskar Upadhaya msi-controller; 1278897f325SBhaskar Upadhaya reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 1288897f325SBhaskar Upadhaya }; 1298897f325SBhaskar Upadhaya }; 1308897f325SBhaskar Upadhaya 13168e36a42SFabio Estevam thermal-zones { 13268e36a42SFabio Estevam core-cluster { 13368e36a42SFabio Estevam polling-delay-passive = <1000>; 13468e36a42SFabio Estevam polling-delay = <5000>; 13568e36a42SFabio Estevam thermal-sensors = <&tmu 0>; 13668e36a42SFabio Estevam 13768e36a42SFabio Estevam trips { 13868e36a42SFabio Estevam core_cluster_alert: core-cluster-alert { 13968e36a42SFabio Estevam temperature = <85000>; 14068e36a42SFabio Estevam hysteresis = <2000>; 14168e36a42SFabio Estevam type = "passive"; 14268e36a42SFabio Estevam }; 14368e36a42SFabio Estevam 14468e36a42SFabio Estevam core_cluster_crit: core-cluster-crit { 14568e36a42SFabio Estevam temperature = <95000>; 14668e36a42SFabio Estevam hysteresis = <2000>; 14768e36a42SFabio Estevam type = "critical"; 14868e36a42SFabio Estevam }; 14968e36a42SFabio Estevam }; 15068e36a42SFabio Estevam 15168e36a42SFabio Estevam cooling-maps { 15268e36a42SFabio Estevam map0 { 15368e36a42SFabio Estevam trip = <&core_cluster_alert>; 15468e36a42SFabio Estevam cooling-device = 15568e36a42SFabio Estevam <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 15668e36a42SFabio Estevam <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 15768e36a42SFabio Estevam }; 15868e36a42SFabio Estevam }; 15968e36a42SFabio Estevam }; 16068e36a42SFabio Estevam }; 16168e36a42SFabio Estevam 1628897f325SBhaskar Upadhaya soc: soc { 1638897f325SBhaskar Upadhaya compatible = "simple-bus"; 1648897f325SBhaskar Upadhaya #address-cells = <2>; 1658897f325SBhaskar Upadhaya #size-cells = <2>; 1668897f325SBhaskar Upadhaya ranges; 1678897f325SBhaskar Upadhaya 1688897f325SBhaskar Upadhaya ddr: memory-controller@1080000 { 1698897f325SBhaskar Upadhaya compatible = "fsl,qoriq-memory-controller"; 1708897f325SBhaskar Upadhaya reg = <0x0 0x1080000 0x0 0x1000>; 1718897f325SBhaskar Upadhaya interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1728897f325SBhaskar Upadhaya big-endian; 1738897f325SBhaskar Upadhaya }; 1748897f325SBhaskar Upadhaya 1758897f325SBhaskar Upadhaya dcfg: syscon@1e00000 { 1768897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-dcfg", "syscon"; 1778897f325SBhaskar Upadhaya reg = <0x0 0x1e00000 0x0 0x10000>; 17833eae7fbSYinbo Zhu little-endian; 1798897f325SBhaskar Upadhaya }; 1808897f325SBhaskar Upadhaya 1813f0fb37bSMichael Walle rst: syscon@1e60000 { 1823f0fb37bSMichael Walle compatible = "syscon"; 1833f0fb37bSMichael Walle reg = <0x0 0x1e60000 0x0 0x10000>; 1843f0fb37bSMichael Walle little-endian; 1853f0fb37bSMichael Walle }; 1863f0fb37bSMichael Walle 1878897f325SBhaskar Upadhaya scfg: syscon@1fc0000 { 1888897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-scfg", "syscon"; 1898897f325SBhaskar Upadhaya reg = <0x0 0x1fc0000 0x0 0x10000>; 1908897f325SBhaskar Upadhaya big-endian; 1918897f325SBhaskar Upadhaya }; 1928897f325SBhaskar Upadhaya 1938897f325SBhaskar Upadhaya clockgen: clock-controller@1300000 { 1948897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-clockgen"; 1958897f325SBhaskar Upadhaya reg = <0x0 0x1300000 0x0 0xa0000>; 1968897f325SBhaskar Upadhaya #clock-cells = <2>; 1978897f325SBhaskar Upadhaya clocks = <&sysclk>; 1988897f325SBhaskar Upadhaya }; 1998897f325SBhaskar Upadhaya 2008897f325SBhaskar Upadhaya i2c0: i2c@2000000 { 2018897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2028897f325SBhaskar Upadhaya #address-cells = <1>; 2038897f325SBhaskar Upadhaya #size-cells = <0>; 2048897f325SBhaskar Upadhaya reg = <0x0 0x2000000 0x0 0x10000>; 2058897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 206ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2078897f325SBhaskar Upadhaya status = "disabled"; 2088897f325SBhaskar Upadhaya }; 2098897f325SBhaskar Upadhaya 2108897f325SBhaskar Upadhaya i2c1: i2c@2010000 { 2118897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2128897f325SBhaskar Upadhaya #address-cells = <1>; 2138897f325SBhaskar Upadhaya #size-cells = <0>; 2148897f325SBhaskar Upadhaya reg = <0x0 0x2010000 0x0 0x10000>; 2158897f325SBhaskar Upadhaya interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 216ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2178897f325SBhaskar Upadhaya status = "disabled"; 2188897f325SBhaskar Upadhaya }; 2198897f325SBhaskar Upadhaya 2208897f325SBhaskar Upadhaya i2c2: i2c@2020000 { 2218897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2228897f325SBhaskar Upadhaya #address-cells = <1>; 2238897f325SBhaskar Upadhaya #size-cells = <0>; 2248897f325SBhaskar Upadhaya reg = <0x0 0x2020000 0x0 0x10000>; 2258897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 226ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2278897f325SBhaskar Upadhaya status = "disabled"; 2288897f325SBhaskar Upadhaya }; 2298897f325SBhaskar Upadhaya 2308897f325SBhaskar Upadhaya i2c3: i2c@2030000 { 2318897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2328897f325SBhaskar Upadhaya #address-cells = <1>; 2338897f325SBhaskar Upadhaya #size-cells = <0>; 2348897f325SBhaskar Upadhaya reg = <0x0 0x2030000 0x0 0x10000>; 2358897f325SBhaskar Upadhaya interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 236ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2378897f325SBhaskar Upadhaya status = "disabled"; 2388897f325SBhaskar Upadhaya }; 2398897f325SBhaskar Upadhaya 2408897f325SBhaskar Upadhaya i2c4: i2c@2040000 { 2418897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2428897f325SBhaskar Upadhaya #address-cells = <1>; 2438897f325SBhaskar Upadhaya #size-cells = <0>; 2448897f325SBhaskar Upadhaya reg = <0x0 0x2040000 0x0 0x10000>; 2458897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 246ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2478897f325SBhaskar Upadhaya status = "disabled"; 2488897f325SBhaskar Upadhaya }; 2498897f325SBhaskar Upadhaya 2508897f325SBhaskar Upadhaya i2c5: i2c@2050000 { 2518897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2528897f325SBhaskar Upadhaya #address-cells = <1>; 2538897f325SBhaskar Upadhaya #size-cells = <0>; 2548897f325SBhaskar Upadhaya reg = <0x0 0x2050000 0x0 0x10000>; 2558897f325SBhaskar Upadhaya interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 256ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2578897f325SBhaskar Upadhaya status = "disabled"; 2588897f325SBhaskar Upadhaya }; 2598897f325SBhaskar Upadhaya 2608897f325SBhaskar Upadhaya i2c6: i2c@2060000 { 2618897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2628897f325SBhaskar Upadhaya #address-cells = <1>; 2638897f325SBhaskar Upadhaya #size-cells = <0>; 2648897f325SBhaskar Upadhaya reg = <0x0 0x2060000 0x0 0x10000>; 2658897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 266ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2678897f325SBhaskar Upadhaya status = "disabled"; 2688897f325SBhaskar Upadhaya }; 2698897f325SBhaskar Upadhaya 2708897f325SBhaskar Upadhaya i2c7: i2c@2070000 { 2718897f325SBhaskar Upadhaya compatible = "fsl,vf610-i2c"; 2728897f325SBhaskar Upadhaya #address-cells = <1>; 2738897f325SBhaskar Upadhaya #size-cells = <0>; 2748897f325SBhaskar Upadhaya reg = <0x0 0x2070000 0x0 0x10000>; 2758897f325SBhaskar Upadhaya interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 276ced41bb1SChuanhua Han clocks = <&clockgen 4 3>; 2778897f325SBhaskar Upadhaya status = "disabled"; 2788897f325SBhaskar Upadhaya }; 2798897f325SBhaskar Upadhaya 280c77fae5bSAshish Kumar fspi: spi@20c0000 { 281c77fae5bSAshish Kumar compatible = "nxp,lx2160a-fspi"; 282c77fae5bSAshish Kumar #address-cells = <1>; 283c77fae5bSAshish Kumar #size-cells = <0>; 284c77fae5bSAshish Kumar reg = <0x0 0x20c0000 0x0 0x10000>, 285c77fae5bSAshish Kumar <0x0 0x20000000 0x0 0x10000000>; 286c77fae5bSAshish Kumar reg-names = "fspi_base", "fspi_mmap"; 287c77fae5bSAshish Kumar interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 288c77fae5bSAshish Kumar clocks = <&clockgen 4 3>, <&clockgen 4 3>; 289c77fae5bSAshish Kumar clock-names = "fspi_en", "fspi"; 290c77fae5bSAshish Kumar status = "disabled"; 291c77fae5bSAshish Kumar }; 292c77fae5bSAshish Kumar 293491d3a3fSAshish Kumar esdhc: mmc@2140000 { 294491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 295491d3a3fSAshish Kumar reg = <0x0 0x2140000 0x0 0x10000>; 296491d3a3fSAshish Kumar interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 297491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 298491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 299491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 300491d3a3fSAshish Kumar sdhci,auto-cmd12; 301491d3a3fSAshish Kumar little-endian; 302491d3a3fSAshish Kumar bus-width = <4>; 303491d3a3fSAshish Kumar status = "disabled"; 304491d3a3fSAshish Kumar }; 305491d3a3fSAshish Kumar 306491d3a3fSAshish Kumar esdhc1: mmc@2150000 { 307491d3a3fSAshish Kumar compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 308491d3a3fSAshish Kumar reg = <0x0 0x2150000 0x0 0x10000>; 309491d3a3fSAshish Kumar interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 310491d3a3fSAshish Kumar clock-frequency = <0>; /* fixed up by bootloader */ 311491d3a3fSAshish Kumar clocks = <&clockgen 2 1>; 312491d3a3fSAshish Kumar voltage-ranges = <1800 1800 3300 3300>; 313491d3a3fSAshish Kumar sdhci,auto-cmd12; 314491d3a3fSAshish Kumar broken-cd; 315491d3a3fSAshish Kumar little-endian; 316491d3a3fSAshish Kumar bus-width = <4>; 317491d3a3fSAshish Kumar status = "disabled"; 318491d3a3fSAshish Kumar }; 319491d3a3fSAshish Kumar 3208897f325SBhaskar Upadhaya duart0: serial@21c0500 { 3218897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3228897f325SBhaskar Upadhaya reg = <0x00 0x21c0500 0x0 0x100>; 3238897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3248897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3258897f325SBhaskar Upadhaya status = "disabled"; 3268897f325SBhaskar Upadhaya }; 3278897f325SBhaskar Upadhaya 3288897f325SBhaskar Upadhaya duart1: serial@21c0600 { 3298897f325SBhaskar Upadhaya compatible = "fsl,ns16550", "ns16550a"; 3308897f325SBhaskar Upadhaya reg = <0x00 0x21c0600 0x0 0x100>; 3318897f325SBhaskar Upadhaya interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3328897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 3338897f325SBhaskar Upadhaya status = "disabled"; 3348897f325SBhaskar Upadhaya }; 3358897f325SBhaskar Upadhaya 3362607d724SMichael Walle 3372607d724SMichael Walle lpuart0: serial@2260000 { 3382607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 3392607d724SMichael Walle reg = <0x0 0x2260000 0x0 0x1000>; 3402607d724SMichael Walle interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 3412607d724SMichael Walle clocks = <&clockgen 4 1>; 3422607d724SMichael Walle clock-names = "ipg"; 3432607d724SMichael Walle dma-names = "rx","tx"; 3442607d724SMichael Walle dmas = <&edma0 1 32>, 3452607d724SMichael Walle <&edma0 1 33>; 3462607d724SMichael Walle status = "disabled"; 3472607d724SMichael Walle }; 3482607d724SMichael Walle 3492607d724SMichael Walle lpuart1: serial@2270000 { 3502607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 3512607d724SMichael Walle reg = <0x0 0x2270000 0x0 0x1000>; 3522607d724SMichael Walle interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 3532607d724SMichael Walle clocks = <&clockgen 4 1>; 3542607d724SMichael Walle clock-names = "ipg"; 3552607d724SMichael Walle dma-names = "rx","tx"; 3562607d724SMichael Walle dmas = <&edma0 1 30>, 3572607d724SMichael Walle <&edma0 1 31>; 3582607d724SMichael Walle status = "disabled"; 3592607d724SMichael Walle }; 3602607d724SMichael Walle 3612607d724SMichael Walle lpuart2: serial@2280000 { 3622607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 3632607d724SMichael Walle reg = <0x0 0x2280000 0x0 0x1000>; 3642607d724SMichael Walle interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 3652607d724SMichael Walle clocks = <&clockgen 4 1>; 3662607d724SMichael Walle clock-names = "ipg"; 3672607d724SMichael Walle dma-names = "rx","tx"; 3682607d724SMichael Walle dmas = <&edma0 1 28>, 3692607d724SMichael Walle <&edma0 1 29>; 3702607d724SMichael Walle status = "disabled"; 3712607d724SMichael Walle }; 3722607d724SMichael Walle 3732607d724SMichael Walle lpuart3: serial@2290000 { 3742607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 3752607d724SMichael Walle reg = <0x0 0x2290000 0x0 0x1000>; 3762607d724SMichael Walle interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 3772607d724SMichael Walle clocks = <&clockgen 4 1>; 3782607d724SMichael Walle clock-names = "ipg"; 3792607d724SMichael Walle dma-names = "rx","tx"; 3802607d724SMichael Walle dmas = <&edma0 1 26>, 3812607d724SMichael Walle <&edma0 1 27>; 3822607d724SMichael Walle status = "disabled"; 3832607d724SMichael Walle }; 3842607d724SMichael Walle 3852607d724SMichael Walle lpuart4: serial@22a0000 { 3862607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 3872607d724SMichael Walle reg = <0x0 0x22a0000 0x0 0x1000>; 3882607d724SMichael Walle interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 3892607d724SMichael Walle clocks = <&clockgen 4 1>; 3902607d724SMichael Walle clock-names = "ipg"; 3912607d724SMichael Walle dma-names = "rx","tx"; 3922607d724SMichael Walle dmas = <&edma0 1 24>, 3932607d724SMichael Walle <&edma0 1 25>; 3942607d724SMichael Walle status = "disabled"; 3952607d724SMichael Walle }; 3962607d724SMichael Walle 3972607d724SMichael Walle lpuart5: serial@22b0000 { 3982607d724SMichael Walle compatible = "fsl,ls1028a-lpuart"; 3992607d724SMichael Walle reg = <0x0 0x22b0000 0x0 0x1000>; 4002607d724SMichael Walle interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 4012607d724SMichael Walle clocks = <&clockgen 4 1>; 4022607d724SMichael Walle clock-names = "ipg"; 4032607d724SMichael Walle dma-names = "rx","tx"; 4042607d724SMichael Walle dmas = <&edma0 1 22>, 4052607d724SMichael Walle <&edma0 1 23>; 4062607d724SMichael Walle status = "disabled"; 4072607d724SMichael Walle }; 4082607d724SMichael Walle 409f54f7be5SAlison Wang edma0: dma-controller@22c0000 { 410f54f7be5SAlison Wang #dma-cells = <2>; 411869bf854SPeng Ma compatible = "fsl,ls1028a-edma"; 412f54f7be5SAlison Wang reg = <0x0 0x22c0000 0x0 0x10000>, 413f54f7be5SAlison Wang <0x0 0x22d0000 0x0 0x10000>, 414f54f7be5SAlison Wang <0x0 0x22e0000 0x0 0x10000>; 415f54f7be5SAlison Wang interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 416f54f7be5SAlison Wang <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 417f54f7be5SAlison Wang interrupt-names = "edma-tx", "edma-err"; 418f54f7be5SAlison Wang dma-channels = <32>; 419f54f7be5SAlison Wang clock-names = "dmamux0", "dmamux1"; 420f54f7be5SAlison Wang clocks = <&clockgen 4 1>, 421f54f7be5SAlison Wang <&clockgen 4 1>; 422f54f7be5SAlison Wang }; 423f54f7be5SAlison Wang 4248897f325SBhaskar Upadhaya gpio1: gpio@2300000 { 425f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4268897f325SBhaskar Upadhaya reg = <0x0 0x2300000 0x0 0x10000>; 4278897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 4288897f325SBhaskar Upadhaya gpio-controller; 4298897f325SBhaskar Upadhaya #gpio-cells = <2>; 4308897f325SBhaskar Upadhaya interrupt-controller; 4318897f325SBhaskar Upadhaya #interrupt-cells = <2>; 432f64697bdSSong Hui little-endian; 4338897f325SBhaskar Upadhaya }; 4348897f325SBhaskar Upadhaya 4358897f325SBhaskar Upadhaya gpio2: gpio@2310000 { 436f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4378897f325SBhaskar Upadhaya reg = <0x0 0x2310000 0x0 0x10000>; 4388897f325SBhaskar Upadhaya interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 4398897f325SBhaskar Upadhaya gpio-controller; 4408897f325SBhaskar Upadhaya #gpio-cells = <2>; 4418897f325SBhaskar Upadhaya interrupt-controller; 4428897f325SBhaskar Upadhaya #interrupt-cells = <2>; 443f64697bdSSong Hui little-endian; 4448897f325SBhaskar Upadhaya }; 4458897f325SBhaskar Upadhaya 4468897f325SBhaskar Upadhaya gpio3: gpio@2320000 { 447f64697bdSSong Hui compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 4488897f325SBhaskar Upadhaya reg = <0x0 0x2320000 0x0 0x10000>; 4498897f325SBhaskar Upadhaya interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 4508897f325SBhaskar Upadhaya gpio-controller; 4518897f325SBhaskar Upadhaya #gpio-cells = <2>; 4528897f325SBhaskar Upadhaya interrupt-controller; 4538897f325SBhaskar Upadhaya #interrupt-cells = <2>; 454f64697bdSSong Hui little-endian; 4558897f325SBhaskar Upadhaya }; 4568897f325SBhaskar Upadhaya 457c92f56faSRan Wang usb0: usb@3100000 { 458c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 459c92f56faSRan Wang reg = <0x0 0x3100000 0x0 0x10000>; 460c92f56faSRan Wang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 461c92f56faSRan Wang dr_mode = "host"; 462c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 463c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 464c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 465c92f56faSRan Wang }; 466c92f56faSRan Wang 467c92f56faSRan Wang usb1: usb@3110000 { 468c92f56faSRan Wang compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 469c92f56faSRan Wang reg = <0x0 0x3110000 0x0 0x10000>; 470c92f56faSRan Wang interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 471c92f56faSRan Wang dr_mode = "host"; 472c92f56faSRan Wang snps,dis_rxdet_inp3_quirk; 473c92f56faSRan Wang snps,quirk-frame-length-adjustment = <0x20>; 474c92f56faSRan Wang snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 4758897f325SBhaskar Upadhaya }; 4768897f325SBhaskar Upadhaya 4778897f325SBhaskar Upadhaya sata: sata@3200000 { 4788897f325SBhaskar Upadhaya compatible = "fsl,ls1028a-ahci"; 4798897f325SBhaskar Upadhaya reg = <0x0 0x3200000 0x0 0x10000>, 4803f3d7958SPeng Ma <0x7 0x100520 0x0 0x4>; 4818897f325SBhaskar Upadhaya reg-names = "ahci", "sata-ecc"; 4828897f325SBhaskar Upadhaya interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4838897f325SBhaskar Upadhaya clocks = <&clockgen 4 1>; 4848897f325SBhaskar Upadhaya status = "disabled"; 4858897f325SBhaskar Upadhaya }; 4868897f325SBhaskar Upadhaya 4878897f325SBhaskar Upadhaya smmu: iommu@5000000 { 4888897f325SBhaskar Upadhaya compatible = "arm,mmu-500"; 4898897f325SBhaskar Upadhaya reg = <0 0x5000000 0 0x800000>; 4908897f325SBhaskar Upadhaya #global-interrupts = <8>; 4918897f325SBhaskar Upadhaya #iommu-cells = <1>; 4928897f325SBhaskar Upadhaya stream-match-mask = <0x7c00>; 4938897f325SBhaskar Upadhaya /* global secure fault */ 4948897f325SBhaskar Upadhaya interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 4958897f325SBhaskar Upadhaya /* combined secure interrupt */ 4968897f325SBhaskar Upadhaya <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 4978897f325SBhaskar Upadhaya /* global non-secure fault */ 4988897f325SBhaskar Upadhaya <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 4998897f325SBhaskar Upadhaya /* combined non-secure interrupt */ 5008897f325SBhaskar Upadhaya <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 5018897f325SBhaskar Upadhaya /* performance counter interrupts 0-7 */ 5028897f325SBhaskar Upadhaya <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 5038897f325SBhaskar Upadhaya <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 5048897f325SBhaskar Upadhaya /* per context interrupt, 64 interrupts */ 5058897f325SBhaskar Upadhaya <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 5068897f325SBhaskar Upadhaya <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 5078897f325SBhaskar Upadhaya <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 5088897f325SBhaskar Upadhaya <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 5098897f325SBhaskar Upadhaya <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 5108897f325SBhaskar Upadhaya <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 5118897f325SBhaskar Upadhaya <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 5128897f325SBhaskar Upadhaya <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 5138897f325SBhaskar Upadhaya <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 5148897f325SBhaskar Upadhaya <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 5158897f325SBhaskar Upadhaya <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 5168897f325SBhaskar Upadhaya <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 5178897f325SBhaskar Upadhaya <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 5188897f325SBhaskar Upadhaya <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 5198897f325SBhaskar Upadhaya <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 5208897f325SBhaskar Upadhaya <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 5218897f325SBhaskar Upadhaya <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 5228897f325SBhaskar Upadhaya <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5238897f325SBhaskar Upadhaya <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5248897f325SBhaskar Upadhaya <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5258897f325SBhaskar Upadhaya <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5268897f325SBhaskar Upadhaya <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5278897f325SBhaskar Upadhaya <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5288897f325SBhaskar Upadhaya <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 5298897f325SBhaskar Upadhaya <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 5308897f325SBhaskar Upadhaya <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 5318897f325SBhaskar Upadhaya <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 5328897f325SBhaskar Upadhaya <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 5338897f325SBhaskar Upadhaya <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 5348897f325SBhaskar Upadhaya <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 5358897f325SBhaskar Upadhaya <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 5368897f325SBhaskar Upadhaya <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 5378897f325SBhaskar Upadhaya }; 538927d7f85SClaudiu Manoil 5391d0becabSHoria Geantă crypto: crypto@8000000 { 5401d0becabSHoria Geantă compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 5411d0becabSHoria Geantă fsl,sec-era = <10>; 5421d0becabSHoria Geantă #address-cells = <1>; 5431d0becabSHoria Geantă #size-cells = <1>; 5441d0becabSHoria Geantă ranges = <0x0 0x00 0x8000000 0x100000>; 5451d0becabSHoria Geantă reg = <0x00 0x8000000 0x0 0x100000>; 5461d0becabSHoria Geantă interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 5471d0becabSHoria Geantă dma-coherent; 5481d0becabSHoria Geantă 5491d0becabSHoria Geantă sec_jr0: jr@10000 { 5501d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5511d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5521d0becabSHoria Geantă reg = <0x10000 0x10000>; 5531d0becabSHoria Geantă interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 5541d0becabSHoria Geantă }; 5551d0becabSHoria Geantă 5561d0becabSHoria Geantă sec_jr1: jr@20000 { 5571d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5581d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5591d0becabSHoria Geantă reg = <0x20000 0x10000>; 5601d0becabSHoria Geantă interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 5611d0becabSHoria Geantă }; 5621d0becabSHoria Geantă 5631d0becabSHoria Geantă sec_jr2: jr@30000 { 5641d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5651d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5661d0becabSHoria Geantă reg = <0x30000 0x10000>; 5671d0becabSHoria Geantă interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 5681d0becabSHoria Geantă }; 5691d0becabSHoria Geantă 5701d0becabSHoria Geantă sec_jr3: jr@40000 { 5711d0becabSHoria Geantă compatible = "fsl,sec-v5.0-job-ring", 5721d0becabSHoria Geantă "fsl,sec-v4.0-job-ring"; 5731d0becabSHoria Geantă reg = <0x40000 0x10000>; 5741d0becabSHoria Geantă interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 5751d0becabSHoria Geantă }; 5761d0becabSHoria Geantă }; 5771d0becabSHoria Geantă 5787802f88dSPeng Ma qdma: dma-controller@8380000 { 5797802f88dSPeng Ma compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 5807802f88dSPeng Ma reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 5817802f88dSPeng Ma <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 5827802f88dSPeng Ma <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 5837802f88dSPeng Ma interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 5847802f88dSPeng Ma <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 5857802f88dSPeng Ma <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 5867802f88dSPeng Ma <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 5877802f88dSPeng Ma <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 5887802f88dSPeng Ma interrupt-names = "qdma-error", "qdma-queue0", 5897802f88dSPeng Ma "qdma-queue1", "qdma-queue2", "qdma-queue3"; 5907802f88dSPeng Ma dma-channels = <8>; 5917802f88dSPeng Ma block-number = <1>; 5927802f88dSPeng Ma block-offset = <0x10000>; 5937802f88dSPeng Ma fsl,dma-queues = <2>; 5947802f88dSPeng Ma status-sizes = <64>; 5957802f88dSPeng Ma queue-sizes = <64 64>; 5967802f88dSPeng Ma }; 5977802f88dSPeng Ma 59857aa1bc7SChuanhua Han cluster1_core0_watchdog: watchdog@c000000 { 59957aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 60057aa1bc7SChuanhua Han reg = <0x0 0xc000000 0x0 0x1000>; 60157aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 60257aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 60357aa1bc7SChuanhua Han }; 60457aa1bc7SChuanhua Han 60557aa1bc7SChuanhua Han cluster1_core1_watchdog: watchdog@c010000 { 60657aa1bc7SChuanhua Han compatible = "arm,sp805", "arm,primecell"; 60757aa1bc7SChuanhua Han reg = <0x0 0xc010000 0x0 0x1000>; 60857aa1bc7SChuanhua Han clocks = <&clockgen 4 15>, <&clockgen 4 15>; 60957aa1bc7SChuanhua Han clock-names = "apb_pclk", "wdog_clk"; 61057aa1bc7SChuanhua Han }; 61157aa1bc7SChuanhua Han 612f54f7be5SAlison Wang sai1: audio-controller@f100000 { 613f54f7be5SAlison Wang #sound-dai-cells = <0>; 614f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 615f54f7be5SAlison Wang reg = <0x0 0xf100000 0x0 0x10000>; 616f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 617f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 618f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 619f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 620f54f7be5SAlison Wang dma-names = "tx", "rx"; 621f54f7be5SAlison Wang dmas = <&edma0 1 4>, 622f54f7be5SAlison Wang <&edma0 1 3>; 6239c015e13SMichael Walle fsl,sai-asynchronous; 624f54f7be5SAlison Wang status = "disabled"; 625f54f7be5SAlison Wang }; 626f54f7be5SAlison Wang 627f54f7be5SAlison Wang sai2: audio-controller@f110000 { 628f54f7be5SAlison Wang #sound-dai-cells = <0>; 629f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 630f54f7be5SAlison Wang reg = <0x0 0xf110000 0x0 0x10000>; 631f54f7be5SAlison Wang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 632f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 633f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 634f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 635f54f7be5SAlison Wang dma-names = "tx", "rx"; 636f54f7be5SAlison Wang dmas = <&edma0 1 6>, 637f54f7be5SAlison Wang <&edma0 1 5>; 6389c015e13SMichael Walle fsl,sai-asynchronous; 639f54f7be5SAlison Wang status = "disabled"; 640f54f7be5SAlison Wang }; 641f54f7be5SAlison Wang 642434f9cc1SMichael Walle sai3: audio-controller@f120000 { 643434f9cc1SMichael Walle #sound-dai-cells = <0>; 644434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 645434f9cc1SMichael Walle reg = <0x0 0xf120000 0x0 0x10000>; 646434f9cc1SMichael Walle interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 647434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 648434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 649434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 650434f9cc1SMichael Walle dma-names = "tx", "rx"; 651434f9cc1SMichael Walle dmas = <&edma0 1 8>, 652434f9cc1SMichael Walle <&edma0 1 7>; 6539c015e13SMichael Walle fsl,sai-asynchronous; 654f54f7be5SAlison Wang status = "disabled"; 655f54f7be5SAlison Wang }; 656f54f7be5SAlison Wang 657f54f7be5SAlison Wang sai4: audio-controller@f130000 { 658f54f7be5SAlison Wang #sound-dai-cells = <0>; 659f54f7be5SAlison Wang compatible = "fsl,vf610-sai"; 660f54f7be5SAlison Wang reg = <0x0 0xf130000 0x0 0x10000>; 661f54f7be5SAlison Wang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 662f54f7be5SAlison Wang clocks = <&clockgen 4 1>, <&clockgen 4 1>, 663f54f7be5SAlison Wang <&clockgen 4 1>, <&clockgen 4 1>; 664f54f7be5SAlison Wang clock-names = "bus", "mclk1", "mclk2", "mclk3"; 665f54f7be5SAlison Wang dma-names = "tx", "rx"; 666f54f7be5SAlison Wang dmas = <&edma0 1 10>, 667f54f7be5SAlison Wang <&edma0 1 9>; 6689c015e13SMichael Walle fsl,sai-asynchronous; 669f54f7be5SAlison Wang status = "disabled"; 670f54f7be5SAlison Wang }; 671f54f7be5SAlison Wang 672434f9cc1SMichael Walle sai5: audio-controller@f140000 { 673434f9cc1SMichael Walle #sound-dai-cells = <0>; 674434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 675434f9cc1SMichael Walle reg = <0x0 0xf140000 0x0 0x10000>; 676434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 677434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 678434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 679434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 680434f9cc1SMichael Walle dma-names = "tx", "rx"; 681434f9cc1SMichael Walle dmas = <&edma0 1 12>, 682434f9cc1SMichael Walle <&edma0 1 11>; 6839c015e13SMichael Walle fsl,sai-asynchronous; 684434f9cc1SMichael Walle status = "disabled"; 685434f9cc1SMichael Walle }; 686434f9cc1SMichael Walle 687434f9cc1SMichael Walle sai6: audio-controller@f150000 { 688434f9cc1SMichael Walle #sound-dai-cells = <0>; 689434f9cc1SMichael Walle compatible = "fsl,vf610-sai"; 690434f9cc1SMichael Walle reg = <0x0 0xf150000 0x0 0x10000>; 691434f9cc1SMichael Walle interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692434f9cc1SMichael Walle clocks = <&clockgen 4 1>, <&clockgen 4 1>, 693434f9cc1SMichael Walle <&clockgen 4 1>, <&clockgen 4 1>; 694434f9cc1SMichael Walle clock-names = "bus", "mclk1", "mclk2", "mclk3"; 695434f9cc1SMichael Walle dma-names = "tx", "rx"; 696434f9cc1SMichael Walle dmas = <&edma0 1 14>, 697434f9cc1SMichael Walle <&edma0 1 13>; 6989c015e13SMichael Walle fsl,sai-asynchronous; 6998897f325SBhaskar Upadhaya status = "disabled"; 7008897f325SBhaskar Upadhaya }; 7018897f325SBhaskar Upadhaya 7020b680963SFabio Estevam tmu: tmu@1f80000 { 703571cebfeSYuantian Tang compatible = "fsl,qoriq-tmu"; 704571cebfeSYuantian Tang reg = <0x0 0x1f80000 0x0 0x10000>; 705571cebfeSYuantian Tang interrupts = <0 23 0x4>; 706571cebfeSYuantian Tang fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 707571cebfeSYuantian Tang fsl,tmu-calibration = <0x00000000 0x00000024 708571cebfeSYuantian Tang 0x00000001 0x0000002b 709571cebfeSYuantian Tang 0x00000002 0x00000031 710571cebfeSYuantian Tang 0x00000003 0x00000038 711571cebfeSYuantian Tang 0x00000004 0x0000003f 712571cebfeSYuantian Tang 0x00000005 0x00000045 713571cebfeSYuantian Tang 0x00000006 0x0000004c 714571cebfeSYuantian Tang 0x00000007 0x00000053 715571cebfeSYuantian Tang 0x00000008 0x00000059 716571cebfeSYuantian Tang 0x00000009 0x00000060 717571cebfeSYuantian Tang 0x0000000a 0x00000066 718571cebfeSYuantian Tang 0x0000000b 0x0000006d 719571cebfeSYuantian Tang 720571cebfeSYuantian Tang 0x00010000 0x0000001c 721571cebfeSYuantian Tang 0x00010001 0x00000024 722571cebfeSYuantian Tang 0x00010002 0x0000002c 723571cebfeSYuantian Tang 0x00010003 0x00000035 724571cebfeSYuantian Tang 0x00010004 0x0000003d 725571cebfeSYuantian Tang 0x00010005 0x00000045 726571cebfeSYuantian Tang 0x00010006 0x0000004d 727961f8209SMichael Walle 0x00010007 0x00000055 728571cebfeSYuantian Tang 0x00010008 0x0000005e 729571cebfeSYuantian Tang 0x00010009 0x00000066 730571cebfeSYuantian Tang 0x0001000a 0x0000006e 731571cebfeSYuantian Tang 732571cebfeSYuantian Tang 0x00020000 0x00000018 733571cebfeSYuantian Tang 0x00020001 0x00000022 734571cebfeSYuantian Tang 0x00020002 0x0000002d 735571cebfeSYuantian Tang 0x00020003 0x00000038 736571cebfeSYuantian Tang 0x00020004 0x00000043 737571cebfeSYuantian Tang 0x00020005 0x0000004d 738571cebfeSYuantian Tang 0x00020006 0x00000058 739571cebfeSYuantian Tang 0x00020007 0x00000063 740571cebfeSYuantian Tang 0x00020008 0x0000006e 741571cebfeSYuantian Tang 742571cebfeSYuantian Tang 0x00030000 0x00000010 743571cebfeSYuantian Tang 0x00030001 0x0000001c 744571cebfeSYuantian Tang 0x00030002 0x00000029 745571cebfeSYuantian Tang 0x00030003 0x00000036 746571cebfeSYuantian Tang 0x00030004 0x00000042 747571cebfeSYuantian Tang 0x00030005 0x0000004f 748571cebfeSYuantian Tang 0x00030006 0x0000005b 749571cebfeSYuantian Tang 0x00030007 0x00000068>; 750571cebfeSYuantian Tang little-endian; 751571cebfeSYuantian Tang #thermal-sensor-cells = <1>; 752571cebfeSYuantian Tang }; 753571cebfeSYuantian Tang 7548897f325SBhaskar Upadhaya pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 7558897f325SBhaskar Upadhaya compatible = "pci-host-ecam-generic"; 7568897f325SBhaskar Upadhaya reg = <0x01 0xf0000000 0x0 0x100000>; 7578897f325SBhaskar Upadhaya #address-cells = <3>; 7588897f325SBhaskar Upadhaya #size-cells = <2>; 7598897f325SBhaskar Upadhaya #interrupt-cells = <1>; 7608897f325SBhaskar Upadhaya msi-parent = <&its>; 7618897f325SBhaskar Upadhaya device_type = "pci"; 7628897f325SBhaskar Upadhaya bus-range = <0x0 0x0>; 7638897f325SBhaskar Upadhaya dma-coherent; 7648897f325SBhaskar Upadhaya msi-map = <0 &its 0x17 0xe>; 7658897f325SBhaskar Upadhaya iommu-map = <0 &smmu 0x17 0xe>; 7668897f325SBhaskar Upadhaya /* PF0-6 BAR0 - non-prefetchable memory */ 7678897f325SBhaskar Upadhaya ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 7688897f325SBhaskar Upadhaya /* PF0-6 BAR2 - prefetchable memory */ 7698897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 7708897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 7718897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 7728897f325SBhaskar Upadhaya /* PF0: VF0-1 BAR2 - prefetchable memory */ 7738897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 7748897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 7758897f325SBhaskar Upadhaya 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 7768897f325SBhaskar Upadhaya /* PF1: VF0-1 BAR2 - prefetchable memory */ 7778897f325SBhaskar Upadhaya 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 7788897f325SBhaskar Upadhaya 7798897f325SBhaskar Upadhaya enetc_port0: ethernet@0,0 { 7808897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 7818897f325SBhaskar Upadhaya reg = <0x000000 0 0 0 0>; 7828897f325SBhaskar Upadhaya }; 7838897f325SBhaskar Upadhaya enetc_port1: ethernet@0,1 { 7848897f325SBhaskar Upadhaya compatible = "fsl,enetc"; 7858897f325SBhaskar Upadhaya reg = <0x000100 0 0 0 0>; 7868897f325SBhaskar Upadhaya }; 7878488d8e9SClaudiu Manoil enetc_mdio_pf3: mdio@0,3 { 7888488d8e9SClaudiu Manoil compatible = "fsl,enetc-mdio"; 7898488d8e9SClaudiu Manoil reg = <0x000300 0 0 0 0>; 7908488d8e9SClaudiu Manoil #address-cells = <1>; 7918488d8e9SClaudiu Manoil #size-cells = <0>; 7928488d8e9SClaudiu Manoil }; 79349401003SY.b. Lu ethernet@0,4 { 79449401003SY.b. Lu compatible = "fsl,enetc-ptp"; 79549401003SY.b. Lu reg = <0x000400 0 0 0 0>; 79649401003SY.b. Lu clocks = <&clockgen 4 0>; 79749401003SY.b. Lu little-endian; 79849401003SY.b. Lu }; 7998897f325SBhaskar Upadhaya }; 8008897f325SBhaskar Upadhaya }; 8017f538f19SWen He 8027f538f19SWen He malidp0: display@f080000 { 8037f538f19SWen He compatible = "arm,mali-dp500"; 8047f538f19SWen He reg = <0x0 0xf080000 0x0 0x10000>; 8057f538f19SWen He interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 8067f538f19SWen He <0 223 IRQ_TYPE_LEVEL_HIGH>; 8077f538f19SWen He interrupt-names = "DE", "SE"; 80891035cb0SWen He clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 80913782597SWen He <&clockgen 2 2>; 8107f538f19SWen He clock-names = "pxlclk", "mclk", "aclk", "pclk"; 8117f538f19SWen He arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 8123a3f0608SWen He arm,malidp-arqos-value = <0xd000d000>; 8137f538f19SWen He 8147f538f19SWen He port { 8157f538f19SWen He dp0_out: endpoint { 8167f538f19SWen He 8177f538f19SWen He }; 8187f538f19SWen He }; 8197f538f19SWen He }; 8208897f325SBhaskar Upadhaya}; 821