1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015-2017 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34 35/ { 36 compatible = "brcm,stingray"; 37 interrupt-parent = <&gic>; 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a72"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&CLUSTER0_L2>; 51 }; 52 53 cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a72"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 next-level-cache = <&CLUSTER0_L2>; 59 }; 60 61 cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72"; 64 reg = <0x0 0x100>; 65 enable-method = "psci"; 66 next-level-cache = <&CLUSTER1_L2>; 67 }; 68 69 cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a72"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 next-level-cache = <&CLUSTER1_L2>; 75 }; 76 77 cpu@200 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a72"; 80 reg = <0x0 0x200>; 81 enable-method = "psci"; 82 next-level-cache = <&CLUSTER2_L2>; 83 }; 84 85 cpu@201 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a72"; 88 reg = <0x0 0x201>; 89 enable-method = "psci"; 90 next-level-cache = <&CLUSTER2_L2>; 91 }; 92 93 cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a72"; 96 reg = <0x0 0x300>; 97 enable-method = "psci"; 98 next-level-cache = <&CLUSTER3_L2>; 99 }; 100 101 cpu@301 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a72"; 104 reg = <0x0 0x301>; 105 enable-method = "psci"; 106 next-level-cache = <&CLUSTER3_L2>; 107 }; 108 109 CLUSTER0_L2: l2-cache@0 { 110 compatible = "cache"; 111 }; 112 113 CLUSTER1_L2: l2-cache@100 { 114 compatible = "cache"; 115 }; 116 117 CLUSTER2_L2: l2-cache@200 { 118 compatible = "cache"; 119 }; 120 121 CLUSTER3_L2: l2-cache@300 { 122 compatible = "cache"; 123 }; 124 }; 125 126 memory: memory@80000000 { 127 device_type = "memory"; 128 reg = <0x00000000 0x80000000 0 0x40000000>; 129 }; 130 131 psci { 132 compatible = "arm,psci-0.2"; 133 method = "smc"; 134 }; 135 136 pmu { 137 compatible = "arm,armv8-pmuv3"; 138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 139 }; 140 141 timer { 142 compatible = "arm,armv8-timer"; 143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 147 }; 148 149 mhb: syscon@60401000 { 150 compatible = "brcm,sr-mhb", "syscon"; 151 reg = <0 0x60401000 0 0x38c>; 152 }; 153 154 scr { 155 compatible = "simple-bus"; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges = <0x0 0x0 0x61000000 0x05000000>; 159 160 ccn: ccn@0 { 161 compatible = "arm,ccn-502"; 162 reg = <0x00000000 0x900000>; 163 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 gic: interrupt-controller@2c00000 { 167 compatible = "arm,gic-v3"; 168 #interrupt-cells = <3>; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges; 172 interrupt-controller; 173 reg = <0x02c00000 0x010000>, /* GICD */ 174 <0x02e00000 0x600000>; /* GICR */ 175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 176 177 gic_its: gic-its@63c20000 { 178 compatible = "arm,gic-v3-its"; 179 msi-controller; 180 #msi-cells = <1>; 181 reg = <0x02c20000 0x10000>; 182 }; 183 }; 184 185 smmu: mmu@3000000 { 186 compatible = "arm,mmu-500"; 187 reg = <0x03000000 0x80000>; 188 #global-interrupts = <1>; 189 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 254 #iommu-cells = <2>; 255 }; 256 }; 257 258 crmu: crmu { 259 compatible = "simple-bus"; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x0 0x0 0x66400000 0x100000>; 263 264 #include "stingray-clock.dtsi" 265 266 otp: otp@1c400 { 267 compatible = "brcm,ocotp-v2"; 268 reg = <0x0001c400 0x68>; 269 brcm,ocotp-size = <2048>; 270 status = "okay"; 271 }; 272 273 cdru: syscon@1d000 { 274 compatible = "brcm,sr-cdru", "syscon"; 275 reg = <0x0001d000 0x400>; 276 }; 277 278 gpio_crmu: gpio@24800 { 279 compatible = "brcm,iproc-gpio"; 280 reg = <0x00024800 0x4c>; 281 ngpios = <6>; 282 #gpio-cells = <2>; 283 gpio-controller; 284 }; 285 }; 286 287 #include "stingray-fs4.dtsi" 288 #include "stingray-sata.dtsi" 289 #include "stingray-pcie.dtsi" 290 #include "stingray-usb.dtsi" 291 292 hsls { 293 compatible = "simple-bus"; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges = <0x0 0x0 0x68900000 0x17700000>; 297 298 #include "stingray-pinctrl.dtsi" 299 300 mdio_mux_iproc: mdio-mux@20000 { 301 compatible = "brcm,mdio-mux-iproc"; 302 reg = <0x00020000 0x250>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 306 mdio@0 { /* PCIe serdes */ 307 reg = <0x0>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 }; 311 312 mdio@2 { /* SATA */ 313 reg = <0x2>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 318 mdio@3 { /* USB */ 319 reg = <0x3>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 }; 323 324 mdio@10 { /* RGMII */ 325 reg = <0x10>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 }; 329 }; 330 331 pwm: pwm@10000 { 332 compatible = "brcm,iproc-pwm"; 333 reg = <0x00010000 0x1000>; 334 clocks = <&crmu_ref25m>; 335 #pwm-cells = <3>; 336 status = "disabled"; 337 }; 338 339 timer0: timer@30000 { 340 compatible = "arm,sp804", "arm,primecell"; 341 reg = <0x00030000 0x1000>; 342 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&hsls_25m_div2_clk>, 344 <&hsls_25m_div2_clk>, 345 <&hsls_div4_clk>; 346 clock-names = "timer1", "timer2", "apb_pclk"; 347 status = "disabled"; 348 }; 349 350 timer1: timer@40000 { 351 compatible = "arm,sp804", "arm,primecell"; 352 reg = <0x00040000 0x1000>; 353 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&hsls_25m_div2_clk>, 355 <&hsls_25m_div2_clk>, 356 <&hsls_div4_clk>; 357 clock-names = "timer1", "timer2", "apb_pclk"; 358 }; 359 360 timer2: timer@50000 { 361 compatible = "arm,sp804", "arm,primecell"; 362 reg = <0x00050000 0x1000>; 363 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&hsls_25m_div2_clk>, 365 <&hsls_25m_div2_clk>, 366 <&hsls_div4_clk>; 367 clock-names = "timer1", "timer2", "apb_pclk"; 368 status = "disabled"; 369 }; 370 371 timer3: timer@60000 { 372 compatible = "arm,sp804", "arm,primecell"; 373 reg = <0x00060000 0x1000>; 374 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&hsls_25m_div2_clk>, 376 <&hsls_25m_div2_clk>, 377 <&hsls_div4_clk>; 378 clock-names = "timer1", "timer2", "apb_pclk"; 379 status = "disabled"; 380 }; 381 382 timer4: timer@70000 { 383 compatible = "arm,sp804", "arm,primecell"; 384 reg = <0x00070000 0x1000>; 385 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&hsls_25m_div2_clk>, 387 <&hsls_25m_div2_clk>, 388 <&hsls_div4_clk>; 389 clock-names = "timer1", "timer2", "apb_pclk"; 390 status = "disabled"; 391 }; 392 393 timer5: timer@80000 { 394 compatible = "arm,sp804", "arm,primecell"; 395 reg = <0x00080000 0x1000>; 396 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&hsls_25m_div2_clk>, 398 <&hsls_25m_div2_clk>, 399 <&hsls_div4_clk>; 400 clock-names = "timer1", "timer2", "apb_pclk"; 401 status = "disabled"; 402 }; 403 404 timer6: timer@90000 { 405 compatible = "arm,sp804", "arm,primecell"; 406 reg = <0x00090000 0x1000>; 407 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&hsls_25m_div2_clk>, 409 <&hsls_25m_div2_clk>, 410 <&hsls_div4_clk>; 411 clock-names = "timer1", "timer2", "apb_pclk"; 412 status = "disabled"; 413 }; 414 415 timer7: timer@a0000 { 416 compatible = "arm,sp804", "arm,primecell"; 417 reg = <0x000a0000 0x1000>; 418 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&hsls_25m_div2_clk>, 420 <&hsls_25m_div2_clk>, 421 <&hsls_div4_clk>; 422 clock-names = "timer1", "timer2", "apb_pclk"; 423 status = "disabled"; 424 }; 425 426 i2c0: i2c@b0000 { 427 compatible = "brcm,iproc-i2c"; 428 reg = <0x000b0000 0x100>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 432 clock-frequency = <100000>; 433 status = "disabled"; 434 }; 435 436 wdt0: watchdog@c0000 { 437 compatible = "arm,sp805", "arm,primecell"; 438 reg = <0x000c0000 0x1000>; 439 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; 441 clock-names = "wdogclk", "apb_pclk"; 442 timeout-sec = <60>; 443 }; 444 445 gpio_hsls: gpio@d0000 { 446 compatible = "brcm,iproc-gpio"; 447 reg = <0x000d0000 0x864>; 448 ngpios = <151>; 449 #gpio-cells = <2>; 450 gpio-controller; 451 interrupt-controller; 452 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 453 gpio-ranges = <&pinmux 0 0 16>, 454 <&pinmux 16 71 2>, 455 <&pinmux 18 131 8>, 456 <&pinmux 26 83 6>, 457 <&pinmux 32 123 4>, 458 <&pinmux 36 43 24>, 459 <&pinmux 60 89 2>, 460 <&pinmux 62 73 4>, 461 <&pinmux 66 95 28>, 462 <&pinmux 94 127 4>, 463 <&pinmux 98 139 10>, 464 <&pinmux 108 16 27>, 465 <&pinmux 135 77 6>, 466 <&pinmux 141 67 4>, 467 <&pinmux 145 149 6>, 468 <&pinmux 151 91 4>; 469 }; 470 471 i2c1: i2c@e0000 { 472 compatible = "brcm,iproc-i2c"; 473 reg = <0x000e0000 0x100>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 477 clock-frequency = <100000>; 478 status = "disabled"; 479 }; 480 481 uart0: uart@100000 { 482 device_type = "serial"; 483 compatible = "snps,dw-apb-uart"; 484 reg = <0x00100000 0x1000>; 485 reg-shift = <2>; 486 clock-frequency = <25000000>; 487 interrupt-parent = <&gic>; 488 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 489 status = "disabled"; 490 }; 491 492 uart1: uart@110000 { 493 device_type = "serial"; 494 compatible = "snps,dw-apb-uart"; 495 reg = <0x00110000 0x1000>; 496 reg-shift = <2>; 497 clock-frequency = <25000000>; 498 interrupt-parent = <&gic>; 499 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 500 status = "disabled"; 501 }; 502 503 uart2: uart@120000 { 504 device_type = "serial"; 505 compatible = "snps,dw-apb-uart"; 506 reg = <0x00120000 0x1000>; 507 reg-shift = <2>; 508 clock-frequency = <25000000>; 509 interrupt-parent = <&gic>; 510 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 511 status = "disabled"; 512 }; 513 514 uart3: uart@130000 { 515 device_type = "serial"; 516 compatible = "snps,dw-apb-uart"; 517 reg = <0x00130000 0x1000>; 518 reg-shift = <2>; 519 clock-frequency = <25000000>; 520 interrupt-parent = <&gic>; 521 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 522 status = "disabled"; 523 }; 524 525 ssp0: spi@180000 { 526 compatible = "arm,pl022", "arm,primecell"; 527 reg = <0x00180000 0x1000>; 528 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 530 clock-names = "spiclk", "apb_pclk"; 531 num-cs = <1>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 537 ssp1: spi@190000 { 538 compatible = "arm,pl022", "arm,primecell"; 539 reg = <0x00190000 0x1000>; 540 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 542 clock-names = "spiclk", "apb_pclk"; 543 num-cs = <1>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 status = "disabled"; 547 }; 548 549 hwrng: hwrng@220000 { 550 compatible = "brcm,iproc-rng200"; 551 reg = <0x00220000 0x28>; 552 }; 553 554 dma0: dma@310000 { 555 compatible = "arm,pl330", "arm,primecell"; 556 reg = <0x00310000 0x1000>; 557 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 566 #dma-cells = <1>; 567 #dma-channels = <8>; 568 #dma-requests = <32>; 569 clocks = <&hsls_div2_clk>; 570 clock-names = "apb_pclk"; 571 iommus = <&smmu 0x6000 0x0000>; 572 }; 573 574 enet: ethernet@340000{ 575 compatible = "brcm,amac"; 576 reg = <0x00340000 0x1000>; 577 reg-names = "amac_base"; 578 dma-coherent; 579 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 580 status= "disabled"; 581 }; 582 583 nand: nand@360000 { 584 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 585 reg = <0x00360000 0x600>, 586 <0x0050a408 0x600>, 587 <0x00360f00 0x20>; 588 reg-names = "nand", "iproc-idm", "iproc-ext"; 589 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 brcm,nand-has-wp; 593 status = "disabled"; 594 }; 595 596 sdio0: sdhci@3f1000 { 597 compatible = "brcm,sdhci-iproc"; 598 reg = <0x003f1000 0x100>; 599 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 600 bus-width = <8>; 601 clocks = <&sdio0_clk>; 602 iommus = <&smmu 0x6002 0x0000>; 603 status = "disabled"; 604 }; 605 606 sdio1: sdhci@3f2000 { 607 compatible = "brcm,sdhci-iproc"; 608 reg = <0x003f2000 0x100>; 609 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 610 bus-width = <8>; 611 clocks = <&sdio1_clk>; 612 iommus = <&smmu 0x6003 0x0000>; 613 status = "disabled"; 614 }; 615 }; 616 617 tmons { 618 compatible = "simple-bus"; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 ranges = <0x0 0x0 0x8f100000 0x100>; 622 623 tmon: tmon@0 { 624 compatible = "brcm,sr-thermal"; 625 reg = <0x0 0x40>; 626 brcm,tmon-mask = <0x3f>; 627 #thermal-sensor-cells = <1>; 628 }; 629 }; 630 631 thermal-zones { 632 ihost0_thermal: ihost0-thermal { 633 polling-delay-passive = <0>; 634 polling-delay = <1000>; 635 thermal-sensors = <&tmon 0>; 636 trips { 637 cpu-crit { 638 temperature = <105000>; 639 hysteresis = <0>; 640 type = "critical"; 641 }; 642 }; 643 }; 644 ihost1_thermal: ihost1-thermal { 645 polling-delay-passive = <0>; 646 polling-delay = <1000>; 647 thermal-sensors = <&tmon 1>; 648 trips { 649 cpu-crit { 650 temperature = <105000>; 651 hysteresis = <0>; 652 type = "critical"; 653 }; 654 }; 655 }; 656 ihost2_thermal: ihost2-thermal { 657 polling-delay-passive = <0>; 658 polling-delay = <1000>; 659 thermal-sensors = <&tmon 2>; 660 trips { 661 cpu-crit { 662 temperature = <105000>; 663 hysteresis = <0>; 664 type = "critical"; 665 }; 666 }; 667 }; 668 ihost3_thermal: ihost3-thermal { 669 polling-delay-passive = <0>; 670 polling-delay = <1000>; 671 thermal-sensors = <&tmon 3>; 672 trips { 673 cpu-crit { 674 temperature = <105000>; 675 hysteresis = <0>; 676 type = "critical"; 677 }; 678 }; 679 }; 680 crmu_thermal: crmu-thermal { 681 polling-delay-passive = <0>; 682 polling-delay = <1000>; 683 thermal-sensors = <&tmon 4>; 684 trips { 685 cpu-crit { 686 temperature = <105000>; 687 hysteresis = <0>; 688 type = "critical"; 689 }; 690 }; 691 }; 692 nitro_thermal: nitro-thermal { 693 polling-delay-passive = <0>; 694 polling-delay = <1000>; 695 thermal-sensors = <&tmon 5>; 696 trips { 697 cpu-crit { 698 temperature = <105000>; 699 hysteresis = <0>; 700 type = "critical"; 701 }; 702 }; 703 }; 704 }; 705 706 nic-hsls { 707 compatible = "simple-bus"; 708 #address-cells = <1>; 709 #size-cells = <1>; 710 ranges = <0x0 0x0 0x0 0x7fffffff>; 711 712 nic_i2c0: i2c@60826100 { 713 compatible = "brcm,iproc-nic-i2c"; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 reg = <0x60826100 0x100>, 717 <0x60e00408 0x1000>; 718 brcm,ape-hsls-addr-mask = <0x03400000>; 719 clock-frequency = <100000>; 720 status = "disabled"; 721 }; 722 }; 723}; 724