1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015-2017 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34 35/ { 36 compatible = "brcm,stingray"; 37 interrupt-parent = <&gic>; 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a72"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&CLUSTER0_L2>; 51 }; 52 53 cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a72"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 next-level-cache = <&CLUSTER0_L2>; 59 }; 60 61 cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72"; 64 reg = <0x0 0x100>; 65 enable-method = "psci"; 66 next-level-cache = <&CLUSTER1_L2>; 67 }; 68 69 cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a72"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 next-level-cache = <&CLUSTER1_L2>; 75 }; 76 77 cpu@200 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a72"; 80 reg = <0x0 0x200>; 81 enable-method = "psci"; 82 next-level-cache = <&CLUSTER2_L2>; 83 }; 84 85 cpu@201 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a72"; 88 reg = <0x0 0x201>; 89 enable-method = "psci"; 90 next-level-cache = <&CLUSTER2_L2>; 91 }; 92 93 cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a72"; 96 reg = <0x0 0x300>; 97 enable-method = "psci"; 98 next-level-cache = <&CLUSTER3_L2>; 99 }; 100 101 cpu@301 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a72"; 104 reg = <0x0 0x301>; 105 enable-method = "psci"; 106 next-level-cache = <&CLUSTER3_L2>; 107 }; 108 109 CLUSTER0_L2: l2-cache@0 { 110 compatible = "cache"; 111 }; 112 113 CLUSTER1_L2: l2-cache@100 { 114 compatible = "cache"; 115 }; 116 117 CLUSTER2_L2: l2-cache@200 { 118 compatible = "cache"; 119 }; 120 121 CLUSTER3_L2: l2-cache@300 { 122 compatible = "cache"; 123 }; 124 }; 125 126 memory: memory@80000000 { 127 device_type = "memory"; 128 reg = <0x00000000 0x80000000 0 0x40000000>; 129 }; 130 131 psci { 132 compatible = "arm,psci-0.2"; 133 method = "smc"; 134 }; 135 136 pmu { 137 compatible = "arm,armv8-pmuv3"; 138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 139 }; 140 141 timer { 142 compatible = "arm,armv8-timer"; 143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 147 }; 148 149 mhb: syscon@60401000 { 150 compatible = "brcm,sr-mhb", "syscon"; 151 reg = <0 0x60401000 0 0x38c>; 152 }; 153 154 scr { 155 compatible = "simple-bus"; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges = <0x0 0x0 0x61000000 0x05000000>; 159 160 ccn: ccn@0 { 161 compatible = "arm,ccn-502"; 162 reg = <0x00000000 0x900000>; 163 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 gic: interrupt-controller@2c00000 { 167 compatible = "arm,gic-v3"; 168 #interrupt-cells = <3>; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges; 172 interrupt-controller; 173 reg = <0x02c00000 0x010000>, /* GICD */ 174 <0x02e00000 0x600000>; /* GICR */ 175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 176 177 gic_its: gic-its@63c20000 { 178 compatible = "arm,gic-v3-its"; 179 msi-controller; 180 #msi-cells = <1>; 181 reg = <0x02c20000 0x10000>; 182 }; 183 }; 184 185 smmu: mmu@3000000 { 186 compatible = "arm,mmu-500"; 187 reg = <0x03000000 0x80000>; 188 #global-interrupts = <1>; 189 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 254 #iommu-cells = <2>; 255 }; 256 }; 257 258 crmu: crmu { 259 compatible = "simple-bus"; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x0 0x0 0x66400000 0x100000>; 263 264 #include "stingray-clock.dtsi" 265 266 otp: otp@1c400 { 267 compatible = "brcm,ocotp-v2"; 268 reg = <0x0001c400 0x68>; 269 brcm,ocotp-size = <2048>; 270 status = "okay"; 271 }; 272 273 cdru: syscon@1d000 { 274 compatible = "brcm,sr-cdru", "syscon"; 275 reg = <0x0001d000 0x400>; 276 }; 277 278 gpio_crmu: gpio@24800 { 279 compatible = "brcm,iproc-gpio"; 280 reg = <0x00024800 0x4c>; 281 ngpios = <6>; 282 #gpio-cells = <2>; 283 gpio-controller; 284 }; 285 }; 286 287 #include "stingray-fs4.dtsi" 288 #include "stingray-pcie.dtsi" 289 #include "stingray-usb.dtsi" 290 291 hsls { 292 compatible = "simple-bus"; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 ranges = <0x0 0x0 0x68900000 0x17700000>; 296 297 #include "stingray-pinctrl.dtsi" 298 299 mdio_mux_iproc: mdio-mux@20000 { 300 compatible = "brcm,mdio-mux-iproc"; 301 reg = <0x00020000 0x250>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 mdio@0 { /* PCIe serdes */ 306 reg = <0x0>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 }; 310 311 mdio@3 { /* USB */ 312 reg = <0x3>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 }; 316 317 mdio@10 { /* RGMII */ 318 reg = <0x10>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 }; 322 }; 323 324 pwm: pwm@10000 { 325 compatible = "brcm,iproc-pwm"; 326 reg = <0x00010000 0x1000>; 327 clocks = <&crmu_ref25m>; 328 #pwm-cells = <3>; 329 status = "disabled"; 330 }; 331 332 timer0: timer@30000 { 333 compatible = "arm,sp804", "arm,primecell"; 334 reg = <0x00030000 0x1000>; 335 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&hsls_25m_div2_clk>, 337 <&hsls_25m_div2_clk>, 338 <&hsls_div4_clk>; 339 clock-names = "timer1", "timer2", "apb_pclk"; 340 status = "disabled"; 341 }; 342 343 timer1: timer@40000 { 344 compatible = "arm,sp804", "arm,primecell"; 345 reg = <0x00040000 0x1000>; 346 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&hsls_25m_div2_clk>, 348 <&hsls_25m_div2_clk>, 349 <&hsls_div4_clk>; 350 clock-names = "timer1", "timer2", "apb_pclk"; 351 }; 352 353 timer2: timer@50000 { 354 compatible = "arm,sp804", "arm,primecell"; 355 reg = <0x00050000 0x1000>; 356 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&hsls_25m_div2_clk>, 358 <&hsls_25m_div2_clk>, 359 <&hsls_div4_clk>; 360 clock-names = "timer1", "timer2", "apb_pclk"; 361 status = "disabled"; 362 }; 363 364 timer3: timer@60000 { 365 compatible = "arm,sp804", "arm,primecell"; 366 reg = <0x00060000 0x1000>; 367 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&hsls_25m_div2_clk>, 369 <&hsls_25m_div2_clk>, 370 <&hsls_div4_clk>; 371 clock-names = "timer1", "timer2", "apb_pclk"; 372 status = "disabled"; 373 }; 374 375 timer4: timer@70000 { 376 compatible = "arm,sp804", "arm,primecell"; 377 reg = <0x00070000 0x1000>; 378 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&hsls_25m_div2_clk>, 380 <&hsls_25m_div2_clk>, 381 <&hsls_div4_clk>; 382 clock-names = "timer1", "timer2", "apb_pclk"; 383 status = "disabled"; 384 }; 385 386 timer5: timer@80000 { 387 compatible = "arm,sp804", "arm,primecell"; 388 reg = <0x00080000 0x1000>; 389 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&hsls_25m_div2_clk>, 391 <&hsls_25m_div2_clk>, 392 <&hsls_div4_clk>; 393 clock-names = "timer1", "timer2", "apb_pclk"; 394 status = "disabled"; 395 }; 396 397 timer6: timer@90000 { 398 compatible = "arm,sp804", "arm,primecell"; 399 reg = <0x00090000 0x1000>; 400 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&hsls_25m_div2_clk>, 402 <&hsls_25m_div2_clk>, 403 <&hsls_div4_clk>; 404 clock-names = "timer1", "timer2", "apb_pclk"; 405 status = "disabled"; 406 }; 407 408 timer7: timer@a0000 { 409 compatible = "arm,sp804", "arm,primecell"; 410 reg = <0x000a0000 0x1000>; 411 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&hsls_25m_div2_clk>, 413 <&hsls_25m_div2_clk>, 414 <&hsls_div4_clk>; 415 clock-names = "timer1", "timer2", "apb_pclk"; 416 status = "disabled"; 417 }; 418 419 i2c0: i2c@b0000 { 420 compatible = "brcm,iproc-i2c"; 421 reg = <0x000b0000 0x100>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 425 clock-frequency = <100000>; 426 status = "disabled"; 427 }; 428 429 wdt0: watchdog@c0000 { 430 compatible = "arm,sp805", "arm,primecell"; 431 reg = <0x000c0000 0x1000>; 432 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; 434 clock-names = "wdog_clk", "apb_pclk"; 435 timeout-sec = <60>; 436 }; 437 438 gpio_hsls: gpio@d0000 { 439 compatible = "brcm,iproc-gpio"; 440 reg = <0x000d0000 0x864>; 441 ngpios = <151>; 442 #gpio-cells = <2>; 443 gpio-controller; 444 interrupt-controller; 445 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 446 gpio-ranges = <&pinmux 0 0 16>, 447 <&pinmux 16 71 2>, 448 <&pinmux 18 131 8>, 449 <&pinmux 26 83 6>, 450 <&pinmux 32 123 4>, 451 <&pinmux 36 43 24>, 452 <&pinmux 60 89 2>, 453 <&pinmux 62 73 4>, 454 <&pinmux 66 95 28>, 455 <&pinmux 94 127 4>, 456 <&pinmux 98 139 10>, 457 <&pinmux 108 16 27>, 458 <&pinmux 135 77 6>, 459 <&pinmux 141 67 4>, 460 <&pinmux 145 149 6>; 461 }; 462 463 i2c1: i2c@e0000 { 464 compatible = "brcm,iproc-i2c"; 465 reg = <0x000e0000 0x100>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 469 clock-frequency = <100000>; 470 status = "disabled"; 471 }; 472 473 uart0: serial@100000 { 474 device_type = "serial"; 475 compatible = "snps,dw-apb-uart"; 476 reg = <0x00100000 0x1000>; 477 reg-shift = <2>; 478 clock-frequency = <25000000>; 479 interrupt-parent = <&gic>; 480 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 481 status = "disabled"; 482 }; 483 484 uart1: serial@110000 { 485 device_type = "serial"; 486 compatible = "snps,dw-apb-uart"; 487 reg = <0x00110000 0x1000>; 488 reg-shift = <2>; 489 clock-frequency = <25000000>; 490 interrupt-parent = <&gic>; 491 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 492 status = "disabled"; 493 }; 494 495 uart2: serial@120000 { 496 device_type = "serial"; 497 compatible = "snps,dw-apb-uart"; 498 reg = <0x00120000 0x1000>; 499 reg-shift = <2>; 500 clock-frequency = <25000000>; 501 interrupt-parent = <&gic>; 502 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 503 status = "disabled"; 504 }; 505 506 uart3: serial@130000 { 507 device_type = "serial"; 508 compatible = "snps,dw-apb-uart"; 509 reg = <0x00130000 0x1000>; 510 reg-shift = <2>; 511 clock-frequency = <25000000>; 512 interrupt-parent = <&gic>; 513 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 514 status = "disabled"; 515 }; 516 517 ssp0: spi@180000 { 518 compatible = "arm,pl022", "arm,primecell"; 519 reg = <0x00180000 0x1000>; 520 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 522 clock-names = "sspclk", "apb_pclk"; 523 num-cs = <1>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 status = "disabled"; 527 }; 528 529 ssp1: spi@190000 { 530 compatible = "arm,pl022", "arm,primecell"; 531 reg = <0x00190000 0x1000>; 532 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 534 clock-names = "sspclk", "apb_pclk"; 535 num-cs = <1>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 hwrng: hwrng@220000 { 542 compatible = "brcm,iproc-rng200"; 543 reg = <0x00220000 0x28>; 544 }; 545 546 dma0: dma-controller@310000 { 547 compatible = "arm,pl330", "arm,primecell"; 548 reg = <0x00310000 0x1000>; 549 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 558 #dma-cells = <1>; 559 clocks = <&hsls_div2_clk>; 560 clock-names = "apb_pclk"; 561 iommus = <&smmu 0x6000 0x0000>; 562 }; 563 564 enet: ethernet@340000{ 565 compatible = "brcm,amac"; 566 reg = <0x00340000 0x1000>; 567 reg-names = "amac_base"; 568 dma-coherent; 569 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 570 status= "disabled"; 571 }; 572 573 nand: nand@360000 { 574 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 575 reg = <0x00360000 0x600>, 576 <0x0050a408 0x600>, 577 <0x00360f00 0x20>; 578 reg-names = "nand", "iproc-idm", "iproc-ext"; 579 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 brcm,nand-has-wp; 583 status = "disabled"; 584 }; 585 586 sdio0: sdhci@3f1000 { 587 compatible = "brcm,sdhci-iproc"; 588 reg = <0x003f1000 0x100>; 589 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 590 bus-width = <8>; 591 clocks = <&sdio0_clk>; 592 iommus = <&smmu 0x6002 0x0000>; 593 status = "disabled"; 594 }; 595 596 sdio1: sdhci@3f2000 { 597 compatible = "brcm,sdhci-iproc"; 598 reg = <0x003f2000 0x100>; 599 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 600 bus-width = <8>; 601 clocks = <&sdio1_clk>; 602 iommus = <&smmu 0x6003 0x0000>; 603 status = "disabled"; 604 }; 605 }; 606 607 tmons { 608 compatible = "simple-bus"; 609 #address-cells = <1>; 610 #size-cells = <1>; 611 ranges = <0x0 0x0 0x8f100000 0x100>; 612 613 tmon: tmon@0 { 614 compatible = "brcm,sr-thermal"; 615 reg = <0x0 0x40>; 616 brcm,tmon-mask = <0x3f>; 617 #thermal-sensor-cells = <1>; 618 }; 619 }; 620 621 thermal-zones { 622 ihost0_thermal: ihost0-thermal { 623 polling-delay-passive = <0>; 624 polling-delay = <1000>; 625 thermal-sensors = <&tmon 0>; 626 trips { 627 cpu-crit { 628 temperature = <105000>; 629 hysteresis = <0>; 630 type = "critical"; 631 }; 632 }; 633 }; 634 ihost1_thermal: ihost1-thermal { 635 polling-delay-passive = <0>; 636 polling-delay = <1000>; 637 thermal-sensors = <&tmon 1>; 638 trips { 639 cpu-crit { 640 temperature = <105000>; 641 hysteresis = <0>; 642 type = "critical"; 643 }; 644 }; 645 }; 646 ihost2_thermal: ihost2-thermal { 647 polling-delay-passive = <0>; 648 polling-delay = <1000>; 649 thermal-sensors = <&tmon 2>; 650 trips { 651 cpu-crit { 652 temperature = <105000>; 653 hysteresis = <0>; 654 type = "critical"; 655 }; 656 }; 657 }; 658 ihost3_thermal: ihost3-thermal { 659 polling-delay-passive = <0>; 660 polling-delay = <1000>; 661 thermal-sensors = <&tmon 3>; 662 trips { 663 cpu-crit { 664 temperature = <105000>; 665 hysteresis = <0>; 666 type = "critical"; 667 }; 668 }; 669 }; 670 crmu_thermal: crmu-thermal { 671 polling-delay-passive = <0>; 672 polling-delay = <1000>; 673 thermal-sensors = <&tmon 4>; 674 trips { 675 cpu-crit { 676 temperature = <105000>; 677 hysteresis = <0>; 678 type = "critical"; 679 }; 680 }; 681 }; 682 nitro_thermal: nitro-thermal { 683 polling-delay-passive = <0>; 684 polling-delay = <1000>; 685 thermal-sensors = <&tmon 5>; 686 trips { 687 cpu-crit { 688 temperature = <105000>; 689 hysteresis = <0>; 690 type = "critical"; 691 }; 692 }; 693 }; 694 }; 695 696 nic-hsls { 697 compatible = "simple-bus"; 698 #address-cells = <1>; 699 #size-cells = <1>; 700 ranges = <0x0 0x0 0x0 0x7fffffff>; 701 702 nic_i2c0: i2c@60826100 { 703 compatible = "brcm,iproc-nic-i2c"; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 reg = <0x60826100 0x100>, 707 <0x60e00408 0x1000>; 708 brcm,ape-hsls-addr-mask = <0x03400000>; 709 clock-frequency = <100000>; 710 status = "disabled"; 711 }; 712 }; 713}; 714