1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015-2017 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34 35/ { 36 compatible = "brcm,stingray"; 37 interrupt-parent = <&gic>; 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a72", "arm,armv8"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&CLUSTER0_L2>; 51 }; 52 53 cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a72", "arm,armv8"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 next-level-cache = <&CLUSTER0_L2>; 59 }; 60 61 cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72", "arm,armv8"; 64 reg = <0x0 0x100>; 65 enable-method = "psci"; 66 next-level-cache = <&CLUSTER1_L2>; 67 }; 68 69 cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a72", "arm,armv8"; 72 reg = <0x0 0x101>; 73 enable-method = "psci"; 74 next-level-cache = <&CLUSTER1_L2>; 75 }; 76 77 cpu@200 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a72", "arm,armv8"; 80 reg = <0x0 0x200>; 81 enable-method = "psci"; 82 next-level-cache = <&CLUSTER2_L2>; 83 }; 84 85 cpu@201 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a72", "arm,armv8"; 88 reg = <0x0 0x201>; 89 enable-method = "psci"; 90 next-level-cache = <&CLUSTER2_L2>; 91 }; 92 93 cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a72", "arm,armv8"; 96 reg = <0x0 0x300>; 97 enable-method = "psci"; 98 next-level-cache = <&CLUSTER3_L2>; 99 }; 100 101 cpu@301 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a72", "arm,armv8"; 104 reg = <0x0 0x301>; 105 enable-method = "psci"; 106 next-level-cache = <&CLUSTER3_L2>; 107 }; 108 109 CLUSTER0_L2: l2-cache@0 { 110 compatible = "cache"; 111 }; 112 113 CLUSTER1_L2: l2-cache@100 { 114 compatible = "cache"; 115 }; 116 117 CLUSTER2_L2: l2-cache@200 { 118 compatible = "cache"; 119 }; 120 121 CLUSTER3_L2: l2-cache@300 { 122 compatible = "cache"; 123 }; 124 }; 125 126 memory: memory@80000000 { 127 device_type = "memory"; 128 reg = <0x00000000 0x80000000 0 0x40000000>; 129 }; 130 131 psci { 132 compatible = "arm,psci-0.2"; 133 method = "smc"; 134 }; 135 136 pmu { 137 compatible = "arm,armv8-pmuv3"; 138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 139 }; 140 141 timer { 142 compatible = "arm,armv8-timer"; 143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 147 }; 148 149 scr { 150 compatible = "simple-bus"; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x0 0x0 0x61000000 0x05000000>; 154 155 ccn: ccn@0 { 156 compatible = "arm,ccn-502"; 157 reg = <0x00000000 0x900000>; 158 interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 159 }; 160 161 gic: interrupt-controller@2c00000 { 162 compatible = "arm,gic-v3"; 163 #interrupt-cells = <3>; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges; 167 interrupt-controller; 168 reg = <0x02c00000 0x010000>, /* GICD */ 169 <0x02e00000 0x600000>; /* GICR */ 170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 171 172 gic_its: gic-its@63c20000 { 173 compatible = "arm,gic-v3-its"; 174 msi-controller; 175 #msi-cells = <1>; 176 reg = <0x02c20000 0x10000>; 177 }; 178 }; 179 180 smmu: mmu@3000000 { 181 compatible = "arm,mmu-500"; 182 reg = <0x03000000 0x80000>; 183 #global-interrupts = <1>; 184 interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; 249 #iommu-cells = <2>; 250 }; 251 }; 252 253 crmu: crmu { 254 compatible = "simple-bus"; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 ranges = <0x0 0x0 0x66400000 0x100000>; 258 259 #include "stingray-clock.dtsi" 260 261 otp: otp@1c400 { 262 compatible = "brcm,ocotp-v2"; 263 reg = <0x0001c400 0x68>; 264 brcm,ocotp-size = <2048>; 265 status = "okay"; 266 }; 267 268 gpio_crmu: gpio@24800 { 269 compatible = "brcm,iproc-gpio"; 270 reg = <0x00024800 0x4c>; 271 ngpios = <6>; 272 #gpio-cells = <2>; 273 gpio-controller; 274 }; 275 }; 276 277 #include "stingray-fs4.dtsi" 278 #include "stingray-sata.dtsi" 279 280 hsls { 281 compatible = "simple-bus"; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 ranges = <0x0 0x0 0x68900000 0x17700000>; 285 286 #include "stingray-pinctrl.dtsi" 287 288 mdio_mux_iproc: mdio-mux@2023c { 289 compatible = "brcm,mdio-mux-iproc"; 290 reg = <0x0002023c 0x14>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 mdio@0 { /* PCIe serdes */ 295 reg = <0x0>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 }; 299 300 mdio@2 { /* SATA */ 301 reg = <0x2>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 }; 305 306 mdio@3 { /* USB */ 307 reg = <0x3>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 }; 311 312 mdio@10 { /* RGMII */ 313 reg = <0x10>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 }; 317 }; 318 319 pwm: pwm@10000 { 320 compatible = "brcm,iproc-pwm"; 321 reg = <0x00010000 0x1000>; 322 clocks = <&crmu_ref25m>; 323 #pwm-cells = <3>; 324 status = "disabled"; 325 }; 326 327 timer0: timer@30000 { 328 compatible = "arm,sp804", "arm,primecell"; 329 reg = <0x00030000 0x1000>; 330 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&hsls_25m_div2_clk>, 332 <&hsls_25m_div2_clk>, 333 <&hsls_div4_clk>; 334 clock-names = "timer1", "timer2", "apb_pclk"; 335 status = "disabled"; 336 }; 337 338 timer1: timer@40000 { 339 compatible = "arm,sp804", "arm,primecell"; 340 reg = <0x00040000 0x1000>; 341 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&hsls_25m_div2_clk>, 343 <&hsls_25m_div2_clk>, 344 <&hsls_div4_clk>; 345 clock-names = "timer1", "timer2", "apb_pclk"; 346 }; 347 348 timer2: timer@50000 { 349 compatible = "arm,sp804", "arm,primecell"; 350 reg = <0x00050000 0x1000>; 351 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&hsls_25m_div2_clk>, 353 <&hsls_25m_div2_clk>, 354 <&hsls_div4_clk>; 355 clock-names = "timer1", "timer2", "apb_pclk"; 356 status = "disabled"; 357 }; 358 359 timer3: timer@60000 { 360 compatible = "arm,sp804", "arm,primecell"; 361 reg = <0x00060000 0x1000>; 362 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&hsls_25m_div2_clk>, 364 <&hsls_25m_div2_clk>, 365 <&hsls_div4_clk>; 366 clock-names = "timer1", "timer2", "apb_pclk"; 367 status = "disabled"; 368 }; 369 370 timer4: timer@70000 { 371 compatible = "arm,sp804", "arm,primecell"; 372 reg = <0x00070000 0x1000>; 373 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&hsls_25m_div2_clk>, 375 <&hsls_25m_div2_clk>, 376 <&hsls_div4_clk>; 377 clock-names = "timer1", "timer2", "apb_pclk"; 378 status = "disabled"; 379 }; 380 381 timer5: timer@80000 { 382 compatible = "arm,sp804", "arm,primecell"; 383 reg = <0x00080000 0x1000>; 384 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&hsls_25m_div2_clk>, 386 <&hsls_25m_div2_clk>, 387 <&hsls_div4_clk>; 388 clock-names = "timer1", "timer2", "apb_pclk"; 389 status = "disabled"; 390 }; 391 392 timer6: timer@90000 { 393 compatible = "arm,sp804", "arm,primecell"; 394 reg = <0x00090000 0x1000>; 395 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&hsls_25m_div2_clk>, 397 <&hsls_25m_div2_clk>, 398 <&hsls_div4_clk>; 399 clock-names = "timer1", "timer2", "apb_pclk"; 400 status = "disabled"; 401 }; 402 403 timer7: timer@a0000 { 404 compatible = "arm,sp804", "arm,primecell"; 405 reg = <0x000a0000 0x1000>; 406 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&hsls_25m_div2_clk>, 408 <&hsls_25m_div2_clk>, 409 <&hsls_div4_clk>; 410 clock-names = "timer1", "timer2", "apb_pclk"; 411 status = "disabled"; 412 }; 413 414 i2c0: i2c@b0000 { 415 compatible = "brcm,iproc-i2c"; 416 reg = <0x000b0000 0x100>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>; 420 clock-frequency = <100000>; 421 status = "disabled"; 422 }; 423 424 wdt0: watchdog@c0000 { 425 compatible = "arm,sp805", "arm,primecell"; 426 reg = <0x000c0000 0x1000>; 427 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; 429 clock-names = "wdogclk", "apb_pclk"; 430 timeout-sec = <60>; 431 }; 432 433 gpio_hsls: gpio@d0000 { 434 compatible = "brcm,iproc-gpio"; 435 reg = <0x000d0000 0x864>; 436 ngpios = <151>; 437 #gpio-cells = <2>; 438 gpio-controller; 439 interrupt-controller; 440 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 441 gpio-ranges = <&pinmux 0 0 16>, 442 <&pinmux 16 71 2>, 443 <&pinmux 18 131 8>, 444 <&pinmux 26 83 6>, 445 <&pinmux 32 123 4>, 446 <&pinmux 36 43 24>, 447 <&pinmux 60 89 2>, 448 <&pinmux 62 73 4>, 449 <&pinmux 66 95 28>, 450 <&pinmux 94 127 4>, 451 <&pinmux 98 139 10>, 452 <&pinmux 108 16 27>, 453 <&pinmux 135 77 6>, 454 <&pinmux 141 67 4>, 455 <&pinmux 145 149 6>, 456 <&pinmux 151 91 4>; 457 }; 458 459 i2c1: i2c@e0000 { 460 compatible = "brcm,iproc-i2c"; 461 reg = <0x000e0000 0x100>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>; 465 clock-frequency = <100000>; 466 status = "disabled"; 467 }; 468 469 uart0: uart@100000 { 470 device_type = "serial"; 471 compatible = "snps,dw-apb-uart"; 472 reg = <0x00100000 0x1000>; 473 reg-shift = <2>; 474 clock-frequency = <25000000>; 475 interrupt-parent = <&gic>; 476 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 477 status = "disabled"; 478 }; 479 480 uart1: uart@110000 { 481 device_type = "serial"; 482 compatible = "snps,dw-apb-uart"; 483 reg = <0x00110000 0x1000>; 484 reg-shift = <2>; 485 clock-frequency = <25000000>; 486 interrupt-parent = <&gic>; 487 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 488 status = "disabled"; 489 }; 490 491 uart2: uart@120000 { 492 device_type = "serial"; 493 compatible = "snps,dw-apb-uart"; 494 reg = <0x00120000 0x1000>; 495 reg-shift = <2>; 496 clock-frequency = <25000000>; 497 interrupt-parent = <&gic>; 498 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 499 status = "disabled"; 500 }; 501 502 uart3: uart@130000 { 503 device_type = "serial"; 504 compatible = "snps,dw-apb-uart"; 505 reg = <0x00130000 0x1000>; 506 reg-shift = <2>; 507 clock-frequency = <25000000>; 508 interrupt-parent = <&gic>; 509 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 510 status = "disabled"; 511 }; 512 513 ssp0: ssp@180000 { 514 compatible = "arm,pl022", "arm,primecell"; 515 reg = <0x00180000 0x1000>; 516 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 518 clock-names = "spiclk", "apb_pclk"; 519 num-cs = <1>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 }; 524 525 ssp1: ssp@190000 { 526 compatible = "arm,pl022", "arm,primecell"; 527 reg = <0x00190000 0x1000>; 528 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; 530 clock-names = "spiclk", "apb_pclk"; 531 num-cs = <1>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 status = "disabled"; 535 }; 536 537 hwrng: hwrng@220000 { 538 compatible = "brcm,iproc-rng200"; 539 reg = <0x00220000 0x28>; 540 }; 541 542 dma0: dma@310000 { 543 compatible = "arm,pl330", "arm,primecell"; 544 reg = <0x00310000 0x1000>; 545 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 554 #dma-cells = <1>; 555 #dma-channels = <8>; 556 #dma-requests = <32>; 557 clocks = <&hsls_div2_clk>; 558 clock-names = "apb_pclk"; 559 iommus = <&smmu 0x6000 0x0000>; 560 }; 561 562 enet: ethernet@340000{ 563 compatible = "brcm,amac"; 564 reg = <0x00340000 0x1000>; 565 reg-names = "amac_base"; 566 dma-coherent; 567 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 568 status= "disabled"; 569 }; 570 571 nand: nand@360000 { 572 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 573 reg = <0x00360000 0x600>, 574 <0x0050a408 0x600>, 575 <0x00360f00 0x20>; 576 reg-names = "nand", "iproc-idm", "iproc-ext"; 577 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 brcm,nand-has-wp; 581 status = "disabled"; 582 }; 583 584 sdio0: sdhci@3f1000 { 585 compatible = "brcm,sdhci-iproc"; 586 reg = <0x003f1000 0x100>; 587 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 588 bus-width = <8>; 589 clocks = <&sdio0_clk>; 590 iommus = <&smmu 0x6002 0x0000>; 591 status = "disabled"; 592 }; 593 594 sdio1: sdhci@3f2000 { 595 compatible = "brcm,sdhci-iproc"; 596 reg = <0x003f2000 0x100>; 597 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 598 bus-width = <8>; 599 clocks = <&sdio1_clk>; 600 iommus = <&smmu 0x6003 0x0000>; 601 status = "disabled"; 602 }; 603 }; 604}; 605