1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Andreas Färber
4 */
5
6#include "meson-gx.dtsi"
7#include <dt-bindings/gpio/meson-gxbb-gpio.h>
8#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9#include <dt-bindings/clock/gxbb-clkc.h>
10#include <dt-bindings/clock/gxbb-aoclkc.h>
11#include <dt-bindings/reset/gxbb-aoclkc.h>
12
13/ {
14	compatible = "amlogic,meson-gxbb";
15
16	soc {
17		usb0_phy: phy@c0000000 {
18			compatible = "amlogic,meson-gxbb-usb2-phy";
19			#phy-cells = <0>;
20			reg = <0x0 0xc0000000 0x0 0x20>;
21			resets = <&reset RESET_USB_OTG>;
22			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23			clock-names = "usb_general", "usb";
24			status = "disabled";
25		};
26
27		usb1_phy: phy@c0000020 {
28			compatible = "amlogic,meson-gxbb-usb2-phy";
29			#phy-cells = <0>;
30			reg = <0x0 0xc0000020 0x0 0x20>;
31			resets = <&reset RESET_USB_OTG>;
32			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33			clock-names = "usb_general", "usb";
34			status = "disabled";
35		};
36
37		usb0: usb@c9000000 {
38			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39			reg = <0x0 0xc9000000 0x0 0x40000>;
40			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42			clock-names = "otg";
43			phys = <&usb0_phy>;
44			phy-names = "usb2-phy";
45			dr_mode = "host";
46			status = "disabled";
47		};
48
49		usb1: usb@c9100000 {
50			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51			reg = <0x0 0xc9100000 0x0 0x40000>;
52			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54			clock-names = "otg";
55			phys = <&usb1_phy>;
56			phy-names = "usb2-phy";
57			dr_mode = "host";
58			status = "disabled";
59		};
60	};
61};
62
63&aobus {
64	pinctrl_aobus: pinctrl@14 {
65		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		gpio_ao: bank@14 {
71			reg = <0x0 0x00014 0x0 0x8>,
72			      <0x0 0x0002c 0x0 0x4>,
73			      <0x0 0x00024 0x0 0x8>;
74			reg-names = "mux", "pull", "gpio";
75			gpio-controller;
76			#gpio-cells = <2>;
77			gpio-ranges = <&pinctrl_aobus 0 0 14>;
78		};
79
80		uart_ao_a_pins: uart_ao_a {
81			mux {
82				groups = "uart_tx_ao_a", "uart_rx_ao_a";
83				function = "uart_ao";
84				bias-disable;
85			};
86		};
87
88		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
89			mux {
90				groups = "uart_cts_ao_a",
91				       "uart_rts_ao_a";
92				function = "uart_ao";
93				bias-disable;
94			};
95		};
96
97		uart_ao_b_pins: uart_ao_b {
98			mux {
99				groups = "uart_tx_ao_b", "uart_rx_ao_b";
100				function = "uart_ao_b";
101				bias-disable;
102			};
103		};
104
105		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
106			mux {
107				groups = "uart_cts_ao_b",
108				       "uart_rts_ao_b";
109				function = "uart_ao_b";
110				bias-disable;
111			};
112		};
113
114		remote_input_ao_pins: remote_input_ao {
115			mux {
116				groups = "remote_input_ao";
117				function = "remote_input_ao";
118				bias-disable;
119			};
120		};
121
122		i2c_ao_pins: i2c_ao {
123			mux {
124				groups = "i2c_sck_ao",
125				       "i2c_sda_ao";
126				function = "i2c_ao";
127				bias-disable;
128			};
129		};
130
131		pwm_ao_a_3_pins: pwm_ao_a_3 {
132			mux {
133				groups = "pwm_ao_a_3";
134				function = "pwm_ao_a_3";
135				bias-disable;
136			};
137		};
138
139		pwm_ao_a_6_pins: pwm_ao_a_6 {
140			mux {
141				groups = "pwm_ao_a_6";
142				function = "pwm_ao_a_6";
143				bias-disable;
144			};
145		};
146
147		pwm_ao_a_12_pins: pwm_ao_a_12 {
148			mux {
149				groups = "pwm_ao_a_12";
150				function = "pwm_ao_a_12";
151				bias-disable;
152			};
153		};
154
155		pwm_ao_b_pins: pwm_ao_b {
156			mux {
157				groups = "pwm_ao_b";
158				function = "pwm_ao_b";
159				bias-disable;
160			};
161		};
162
163		i2s_am_clk_pins: i2s_am_clk {
164			mux {
165				groups = "i2s_am_clk";
166				function = "i2s_out_ao";
167				bias-disable;
168			};
169		};
170
171		i2s_out_ao_clk_pins: i2s_out_ao_clk {
172			mux {
173				groups = "i2s_out_ao_clk";
174				function = "i2s_out_ao";
175				bias-disable;
176			};
177		};
178
179		i2s_out_lr_clk_pins: i2s_out_lr_clk {
180			mux {
181				groups = "i2s_out_lr_clk";
182				function = "i2s_out_ao";
183				bias-disable;
184			};
185		};
186
187		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
188			mux {
189				groups = "i2s_out_ch01_ao";
190				function = "i2s_out_ao";
191				bias-disable;
192			};
193		};
194
195		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
196			mux {
197				groups = "i2s_out_ch23_ao";
198				function = "i2s_out_ao";
199				bias-disable;
200			};
201		};
202
203		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
204			mux {
205				groups = "i2s_out_ch45_ao";
206				function = "i2s_out_ao";
207				bias-disable;
208			};
209		};
210
211		spdif_out_ao_6_pins: spdif_out_ao_6 {
212			mux {
213				groups = "spdif_out_ao_6";
214				function = "spdif_out_ao";
215			};
216		};
217
218		spdif_out_ao_13_pins: spdif_out_ao_13 {
219			mux {
220				groups = "spdif_out_ao_13";
221				function = "spdif_out_ao";
222				bias-disable;
223			};
224		};
225
226		ao_cec_pins: ao_cec {
227			mux {
228				groups = "ao_cec";
229				function = "cec_ao";
230				bias-disable;
231			};
232		};
233
234		ee_cec_pins: ee_cec {
235			mux {
236				groups = "ee_cec";
237				function = "cec_ao";
238				bias-disable;
239			};
240		};
241	};
242};
243
244&apb {
245	mali: gpu@c0000 {
246		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
247		reg = <0x0 0xc0000 0x0 0x40000>;
248		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
249			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
250			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
251			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
252			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
253			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
254			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
255			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
256			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
257			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
258		interrupt-names = "gp", "gpmmu", "pp", "pmu",
259			"pp0", "ppmmu0", "pp1", "ppmmu1",
260			"pp2", "ppmmu2";
261		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
262		clock-names = "bus", "core";
263
264		/*
265		 * Mali clocking is provided by two identical clock paths
266		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
267		 * free mux to safely change frequency while running.
268		 */
269		assigned-clocks = <&clkc CLKID_GP0_PLL>,
270				  <&clkc CLKID_MALI_0_SEL>,
271				  <&clkc CLKID_MALI_0>,
272				  <&clkc CLKID_MALI>; /* Glitch free mux */
273		assigned-clock-parents = <0>, /* Do Nothing */
274					 <&clkc CLKID_GP0_PLL>,
275					 <0>, /* Do Nothing */
276					 <&clkc CLKID_MALI_0>;
277		assigned-clock-rates = <744000000>,
278				       <0>, /* Do Nothing */
279				       <744000000>,
280				       <0>; /* Do Nothing */
281	};
282};
283
284&cbus {
285	spifc: spi@8c80 {
286		compatible = "amlogic,meson-gxbb-spifc";
287		reg = <0x0 0x08c80 0x0 0x80>;
288		#address-cells = <1>;
289		#size-cells = <0>;
290		clocks = <&clkc CLKID_SPI>;
291		status = "disabled";
292	};
293};
294
295&cec_AO {
296	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
297	clock-names = "core";
298};
299
300&clkc_AO {
301	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
302	clocks = <&xtal>, <&clkc CLKID_CLK81>;
303	clock-names = "xtal", "mpeg-clk";
304};
305
306&efuse {
307	clocks = <&clkc CLKID_EFUSE>;
308};
309
310&ethmac {
311	clocks = <&clkc CLKID_ETH>,
312		 <&clkc CLKID_FCLK_DIV2>,
313		 <&clkc CLKID_MPLL2>;
314	clock-names = "stmmaceth", "clkin0", "clkin1";
315};
316
317&gpio_intc {
318	compatible = "amlogic,meson-gpio-intc",
319		     "amlogic,meson-gxbb-gpio-intc";
320	status = "okay";
321};
322
323&hdmi_tx {
324	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
325	resets = <&reset RESET_HDMITX_CAPB3>,
326		 <&reset RESET_HDMI_SYSTEM_RESET>,
327		 <&reset RESET_HDMI_TX>;
328	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
329	clocks = <&clkc CLKID_HDMI_PCLK>,
330		 <&clkc CLKID_CLK81>,
331		 <&clkc CLKID_GCLK_VENCI_INT0>;
332	clock-names = "isfr", "iahb", "venci";
333};
334
335&sysctrl {
336	clkc: clock-controller {
337		compatible = "amlogic,gxbb-clkc";
338		#clock-cells = <1>;
339		clocks = <&xtal>;
340		clock-names = "xtal";
341	};
342};
343
344&hwrng {
345	clocks = <&clkc CLKID_RNG0>;
346	clock-names = "core";
347};
348
349&i2c_A {
350	clocks = <&clkc CLKID_I2C>;
351};
352
353&i2c_AO {
354	clocks = <&clkc CLKID_AO_I2C>;
355};
356
357&i2c_B {
358	clocks = <&clkc CLKID_I2C>;
359};
360
361&i2c_C {
362	clocks = <&clkc CLKID_I2C>;
363};
364
365&periphs {
366	pinctrl_periphs: pinctrl@4b0 {
367		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
368		#address-cells = <2>;
369		#size-cells = <2>;
370		ranges;
371
372		gpio: bank@4b0 {
373			reg = <0x0 0x004b0 0x0 0x28>,
374			      <0x0 0x004e8 0x0 0x14>,
375			      <0x0 0x00520 0x0 0x14>,
376			      <0x0 0x00430 0x0 0x40>;
377			reg-names = "mux", "pull", "pull-enable", "gpio";
378			gpio-controller;
379			#gpio-cells = <2>;
380			gpio-ranges = <&pinctrl_periphs 0 0 119>;
381		};
382
383		emmc_pins: emmc {
384			mux-0 {
385				groups = "emmc_nand_d07",
386				       "emmc_cmd";
387				function = "emmc";
388				bias-pull-up;
389			};
390
391			mux-1 {
392				groups = "emmc_clk";
393				function = "emmc";
394				bias-disable;
395			};
396		};
397
398		emmc_ds_pins: emmc-ds {
399			mux {
400				groups = "emmc_ds";
401				function = "emmc";
402				bias-pull-down;
403			};
404		};
405
406		emmc_clk_gate_pins: emmc_clk_gate {
407			mux {
408				groups = "BOOT_8";
409				function = "gpio_periphs";
410				bias-pull-down;
411			};
412		};
413
414		nor_pins: nor {
415			mux {
416				groups = "nor_d",
417				       "nor_q",
418				       "nor_c",
419				       "nor_cs";
420				function = "nor";
421				bias-disable;
422			};
423		};
424
425		spi_pins: spi-pins {
426			mux {
427				groups = "spi_miso",
428					"spi_mosi",
429					"spi_sclk";
430				function = "spi";
431				bias-disable;
432			};
433		};
434
435		spi_ss0_pins: spi-ss0 {
436			mux {
437				groups = "spi_ss0";
438				function = "spi";
439				bias-disable;
440			};
441		};
442
443		sdcard_pins: sdcard {
444			mux-0 {
445				groups = "sdcard_d0",
446				       "sdcard_d1",
447				       "sdcard_d2",
448				       "sdcard_d3",
449				       "sdcard_cmd";
450				function = "sdcard";
451				bias-pull-up;
452			};
453
454			mux-1 {
455				groups = "sdcard_clk";
456				function = "sdcard";
457				bias-disable;
458			};
459		};
460
461		sdcard_clk_gate_pins: sdcard_clk_gate {
462			mux {
463				groups = "CARD_2";
464				function = "gpio_periphs";
465				bias-pull-down;
466			};
467		};
468
469		sdio_pins: sdio {
470			mux-0 {
471				groups = "sdio_d0",
472				       "sdio_d1",
473				       "sdio_d2",
474				       "sdio_d3",
475				       "sdio_cmd";
476				function = "sdio";
477				bias-pull-up;
478			};
479
480			mux-1 {
481				groups = "sdio_clk";
482				function = "sdio";
483				bias-disable;
484			};
485		};
486
487		sdio_clk_gate_pins: sdio_clk_gate {
488			mux {
489				groups = "GPIOX_4";
490				function = "gpio_periphs";
491				bias-pull-down;
492			};
493		};
494
495		sdio_irq_pins: sdio_irq {
496			mux {
497				groups = "sdio_irq";
498				function = "sdio";
499				bias-disable;
500			};
501		};
502
503		uart_a_pins: uart_a {
504			mux {
505				groups = "uart_tx_a",
506				       "uart_rx_a";
507				function = "uart_a";
508				bias-disable;
509			};
510		};
511
512		uart_a_cts_rts_pins: uart_a_cts_rts {
513			mux {
514				groups = "uart_cts_a",
515				       "uart_rts_a";
516				function = "uart_a";
517				bias-disable;
518			};
519		};
520
521		uart_b_pins: uart_b {
522			mux {
523				groups = "uart_tx_b",
524				       "uart_rx_b";
525				function = "uart_b";
526				bias-disable;
527			};
528		};
529
530		uart_b_cts_rts_pins: uart_b_cts_rts {
531			mux {
532				groups = "uart_cts_b",
533				       "uart_rts_b";
534				function = "uart_b";
535				bias-disable;
536			};
537		};
538
539		uart_c_pins: uart_c {
540			mux {
541				groups = "uart_tx_c",
542				       "uart_rx_c";
543				function = "uart_c";
544				bias-disable;
545			};
546		};
547
548		uart_c_cts_rts_pins: uart_c_cts_rts {
549			mux {
550				groups = "uart_cts_c",
551				       "uart_rts_c";
552				function = "uart_c";
553				bias-disable;
554			};
555		};
556
557		i2c_a_pins: i2c_a {
558			mux {
559				groups = "i2c_sck_a",
560				       "i2c_sda_a";
561				function = "i2c_a";
562				bias-disable;
563			};
564		};
565
566		i2c_b_pins: i2c_b {
567			mux {
568				groups = "i2c_sck_b",
569				       "i2c_sda_b";
570				function = "i2c_b";
571				bias-disable;
572			};
573		};
574
575		i2c_c_pins: i2c_c {
576			mux {
577				groups = "i2c_sck_c",
578				       "i2c_sda_c";
579				function = "i2c_c";
580				bias-disable;
581			};
582		};
583
584		eth_rgmii_pins: eth-rgmii {
585			mux {
586				groups = "eth_mdio",
587				       "eth_mdc",
588				       "eth_clk_rx_clk",
589				       "eth_rx_dv",
590				       "eth_rxd0",
591				       "eth_rxd1",
592				       "eth_rxd2",
593				       "eth_rxd3",
594				       "eth_rgmii_tx_clk",
595				       "eth_tx_en",
596				       "eth_txd0",
597				       "eth_txd1",
598				       "eth_txd2",
599				       "eth_txd3";
600				function = "eth";
601				bias-disable;
602			};
603		};
604
605		eth_rmii_pins: eth-rmii {
606			mux {
607				groups = "eth_mdio",
608				       "eth_mdc",
609				       "eth_clk_rx_clk",
610				       "eth_rx_dv",
611				       "eth_rxd0",
612				       "eth_rxd1",
613				       "eth_tx_en",
614				       "eth_txd0",
615				       "eth_txd1";
616				function = "eth";
617				bias-disable;
618			};
619		};
620
621		pwm_a_x_pins: pwm_a_x {
622			mux {
623				groups = "pwm_a_x";
624				function = "pwm_a_x";
625				bias-disable;
626			};
627		};
628
629		pwm_a_y_pins: pwm_a_y {
630			mux {
631				groups = "pwm_a_y";
632				function = "pwm_a_y";
633				bias-disable;
634			};
635		};
636
637		pwm_b_pins: pwm_b {
638			mux {
639				groups = "pwm_b";
640				function = "pwm_b";
641				bias-disable;
642			};
643		};
644
645		pwm_d_pins: pwm_d {
646			mux {
647				groups = "pwm_d";
648				function = "pwm_d";
649				bias-disable;
650			};
651		};
652
653		pwm_e_pins: pwm_e {
654			mux {
655				groups = "pwm_e";
656				function = "pwm_e";
657				bias-disable;
658			};
659		};
660
661		pwm_f_x_pins: pwm_f_x {
662			mux {
663				groups = "pwm_f_x";
664				function = "pwm_f_x";
665				bias-disable;
666			};
667		};
668
669		pwm_f_y_pins: pwm_f_y {
670			mux {
671				groups = "pwm_f_y";
672				function = "pwm_f_y";
673				bias-disable;
674			};
675		};
676
677		hdmi_hpd_pins: hdmi_hpd {
678			mux {
679				groups = "hdmi_hpd";
680				function = "hdmi_hpd";
681				bias-disable;
682			};
683		};
684
685		hdmi_i2c_pins: hdmi_i2c {
686			mux {
687				groups = "hdmi_sda", "hdmi_scl";
688				function = "hdmi_i2c";
689				bias-disable;
690			};
691		};
692
693		i2sout_ch23_y_pins: i2sout_ch23_y {
694			mux {
695				groups = "i2sout_ch23_y";
696				function = "i2s_out";
697				bias-disable;
698			};
699		};
700
701		i2sout_ch45_y_pins: i2sout_ch45_y {
702			mux {
703				groups = "i2sout_ch45_y";
704				function = "i2s_out";
705				bias-disable;
706			};
707		};
708
709		i2sout_ch67_y_pins: i2sout_ch67_y {
710			mux {
711				groups = "i2sout_ch67_y";
712				function = "i2s_out";
713				bias-disable;
714			};
715		};
716
717		spdif_out_y_pins: spdif_out_y {
718			mux {
719				groups = "spdif_out_y";
720				function = "spdif_out";
721				bias-disable;
722			};
723		};
724	};
725};
726
727&pwrc_vpu {
728	resets = <&reset RESET_VIU>,
729		 <&reset RESET_VENC>,
730		 <&reset RESET_VCBUS>,
731		 <&reset RESET_BT656>,
732		 <&reset RESET_DVIN_RESET>,
733		 <&reset RESET_RDMA>,
734		 <&reset RESET_VENCI>,
735		 <&reset RESET_VENCP>,
736		 <&reset RESET_VDAC>,
737		 <&reset RESET_VDI6>,
738		 <&reset RESET_VENCL>,
739		 <&reset RESET_VID_LOCK>;
740	clocks = <&clkc CLKID_VPU>,
741	         <&clkc CLKID_VAPB>;
742	clock-names = "vpu", "vapb";
743	/*
744	 * VPU clocking is provided by two identical clock paths
745	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
746	 * free mux to safely change frequency while running.
747	 * Same for VAPB but with a final gate after the glitch free mux.
748	 */
749	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
750			  <&clkc CLKID_VPU_0>,
751			  <&clkc CLKID_VPU>, /* Glitch free mux */
752			  <&clkc CLKID_VAPB_0_SEL>,
753			  <&clkc CLKID_VAPB_0>,
754			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
755	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
756				 <0>, /* Do Nothing */
757				 <&clkc CLKID_VPU_0>,
758				 <&clkc CLKID_FCLK_DIV4>,
759				 <0>, /* Do Nothing */
760				 <&clkc CLKID_VAPB_0>;
761	assigned-clock-rates = <0>, /* Do Nothing */
762			       <666666666>,
763			       <0>, /* Do Nothing */
764			       <0>, /* Do Nothing */
765			       <250000000>,
766			       <0>; /* Do Nothing */
767};
768
769&saradc {
770	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
771	clocks = <&xtal>,
772		 <&clkc CLKID_SAR_ADC>,
773		 <&clkc CLKID_SAR_ADC_CLK>,
774		 <&clkc CLKID_SAR_ADC_SEL>;
775	clock-names = "clkin", "core", "adc_clk", "adc_sel";
776};
777
778&sd_emmc_a {
779	clocks = <&clkc CLKID_SD_EMMC_A>,
780		 <&clkc CLKID_SD_EMMC_A_CLK0>,
781		 <&clkc CLKID_FCLK_DIV2>;
782	clock-names = "core", "clkin0", "clkin1";
783	resets = <&reset RESET_SD_EMMC_A>;
784};
785
786&sd_emmc_b {
787	clocks = <&clkc CLKID_SD_EMMC_B>,
788		 <&clkc CLKID_SD_EMMC_B_CLK0>,
789		 <&clkc CLKID_FCLK_DIV2>;
790	clock-names = "core", "clkin0", "clkin1";
791	resets = <&reset RESET_SD_EMMC_B>;
792};
793
794&sd_emmc_c {
795	clocks = <&clkc CLKID_SD_EMMC_C>,
796		 <&clkc CLKID_SD_EMMC_C_CLK0>,
797		 <&clkc CLKID_FCLK_DIV2>;
798	clock-names = "core", "clkin0", "clkin1";
799	resets = <&reset RESET_SD_EMMC_C>;
800};
801
802&simplefb_hdmi {
803	clocks = <&clkc CLKID_HDMI_PCLK>,
804		 <&clkc CLKID_CLK81>,
805		 <&clkc CLKID_GCLK_VENCI_INT0>;
806};
807
808&spicc {
809	clocks = <&clkc CLKID_SPICC>;
810	clock-names = "core";
811	resets = <&reset RESET_PERIPHS_SPICC>;
812	num-cs = <1>;
813};
814
815&spifc {
816	clocks = <&clkc CLKID_SPI>;
817};
818
819&uart_A {
820	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
821	clock-names = "xtal", "pclk", "baud";
822};
823
824&uart_AO {
825	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
826	clock-names = "xtal", "pclk", "baud";
827};
828
829&uart_AO_B {
830	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
831	clock-names = "xtal", "pclk", "baud";
832};
833
834&uart_B {
835	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
836	clock-names = "xtal", "pclk", "baud";
837};
838
839&uart_C {
840	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
841	clock-names = "xtal", "pclk", "baud";
842};
843
844&vpu {
845	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
846	power-domains = <&pwrc_vpu>;
847};
848
849&vdec {
850	compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
851	clocks = <&clkc CLKID_DOS_PARSER>,
852		 <&clkc CLKID_DOS>,
853		 <&clkc CLKID_VDEC_1>,
854		 <&clkc CLKID_VDEC_HEVC>;
855	clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
856	resets = <&reset RESET_PARSER>;
857	reset-names = "esparser";
858};
859