1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "meson-gx.dtsi" 44#include <dt-bindings/gpio/meson-gxbb-gpio.h> 45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 46#include <dt-bindings/clock/gxbb-clkc.h> 47#include <dt-bindings/clock/gxbb-aoclkc.h> 48#include <dt-bindings/reset/gxbb-aoclkc.h> 49 50/ { 51 compatible = "amlogic,meson-gxbb"; 52 53 soc { 54 usb0_phy: phy@c0000000 { 55 compatible = "amlogic,meson-gxbb-usb2-phy"; 56 #phy-cells = <0>; 57 reg = <0x0 0xc0000000 0x0 0x20>; 58 resets = <&reset RESET_USB_OTG>; 59 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 60 clock-names = "usb_general", "usb"; 61 status = "disabled"; 62 }; 63 64 usb1_phy: phy@c0000020 { 65 compatible = "amlogic,meson-gxbb-usb2-phy"; 66 #phy-cells = <0>; 67 reg = <0x0 0xc0000020 0x0 0x20>; 68 resets = <&reset RESET_USB_OTG>; 69 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 70 clock-names = "usb_general", "usb"; 71 status = "disabled"; 72 }; 73 74 usb0: usb@c9000000 { 75 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 76 reg = <0x0 0xc9000000 0x0 0x40000>; 77 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 79 clock-names = "otg"; 80 phys = <&usb0_phy>; 81 phy-names = "usb2-phy"; 82 dr_mode = "host"; 83 status = "disabled"; 84 }; 85 86 usb1: usb@c9100000 { 87 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 88 reg = <0x0 0xc9100000 0x0 0x40000>; 89 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 91 clock-names = "otg"; 92 phys = <&usb1_phy>; 93 phy-names = "usb2-phy"; 94 dr_mode = "host"; 95 status = "disabled"; 96 }; 97 }; 98}; 99 100&aobus { 101 pinctrl_aobus: pinctrl@14 { 102 compatible = "amlogic,meson-gxbb-aobus-pinctrl"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 gpio_ao: bank@14 { 108 reg = <0x0 0x00014 0x0 0x8>, 109 <0x0 0x0002c 0x0 0x4>, 110 <0x0 0x00024 0x0 0x8>; 111 reg-names = "mux", "pull", "gpio"; 112 gpio-controller; 113 #gpio-cells = <2>; 114 gpio-ranges = <&pinctrl_aobus 0 0 14>; 115 }; 116 117 uart_ao_a_pins: uart_ao_a { 118 mux { 119 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 120 function = "uart_ao"; 121 }; 122 }; 123 124 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 125 mux { 126 groups = "uart_cts_ao_a", 127 "uart_rts_ao_a"; 128 function = "uart_ao"; 129 }; 130 }; 131 132 uart_ao_b_pins: uart_ao_b { 133 mux { 134 groups = "uart_tx_ao_b", "uart_rx_ao_b"; 135 function = "uart_ao_b"; 136 }; 137 }; 138 139 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 140 mux { 141 groups = "uart_cts_ao_b", 142 "uart_rts_ao_b"; 143 function = "uart_ao_b"; 144 }; 145 }; 146 147 remote_input_ao_pins: remote_input_ao { 148 mux { 149 groups = "remote_input_ao"; 150 function = "remote_input_ao"; 151 }; 152 }; 153 154 i2c_ao_pins: i2c_ao { 155 mux { 156 groups = "i2c_sck_ao", 157 "i2c_sda_ao"; 158 function = "i2c_ao"; 159 }; 160 }; 161 162 pwm_ao_a_3_pins: pwm_ao_a_3 { 163 mux { 164 groups = "pwm_ao_a_3"; 165 function = "pwm_ao_a_3"; 166 }; 167 }; 168 169 pwm_ao_a_6_pins: pwm_ao_a_6 { 170 mux { 171 groups = "pwm_ao_a_6"; 172 function = "pwm_ao_a_6"; 173 }; 174 }; 175 176 pwm_ao_a_12_pins: pwm_ao_a_12 { 177 mux { 178 groups = "pwm_ao_a_12"; 179 function = "pwm_ao_a_12"; 180 }; 181 }; 182 183 pwm_ao_b_pins: pwm_ao_b { 184 mux { 185 groups = "pwm_ao_b"; 186 function = "pwm_ao_b"; 187 }; 188 }; 189 190 i2s_am_clk_pins: i2s_am_clk { 191 mux { 192 groups = "i2s_am_clk"; 193 function = "i2s_out_ao"; 194 }; 195 }; 196 197 i2s_out_ao_clk_pins: i2s_out_ao_clk { 198 mux { 199 groups = "i2s_out_ao_clk"; 200 function = "i2s_out_ao"; 201 }; 202 }; 203 204 i2s_out_lr_clk_pins: i2s_out_lr_clk { 205 mux { 206 groups = "i2s_out_lr_clk"; 207 function = "i2s_out_ao"; 208 }; 209 }; 210 211 i2s_out_ch01_ao_pins: i2s_out_ch01_ao { 212 mux { 213 groups = "i2s_out_ch01_ao"; 214 function = "i2s_out_ao"; 215 }; 216 }; 217 218 i2s_out_ch23_ao_pins: i2s_out_ch23_ao { 219 mux { 220 groups = "i2s_out_ch23_ao"; 221 function = "i2s_out_ao"; 222 }; 223 }; 224 225 i2s_out_ch45_ao_pins: i2s_out_ch45_ao { 226 mux { 227 groups = "i2s_out_ch45_ao"; 228 function = "i2s_out_ao"; 229 }; 230 }; 231 232 spdif_out_ao_6_pins: spdif_out_ao_6 { 233 mux { 234 groups = "spdif_out_ao_6"; 235 function = "spdif_out_ao"; 236 }; 237 }; 238 239 spdif_out_ao_13_pins: spdif_out_ao_13 { 240 mux { 241 groups = "spdif_out_ao_13"; 242 function = "spdif_out_ao"; 243 }; 244 }; 245 }; 246}; 247 248&apb { 249 mali: gpu@c0000 { 250 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; 251 reg = <0x0 0xc0000 0x0 0x40000>; 252 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-names = "gp", "gpmmu", "pp", "pmu", 263 "pp0", "ppmmu0", "pp1", "ppmmu1", 264 "pp2", "ppmmu2"; 265 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 266 clock-names = "bus", "core"; 267 268 /* 269 * Mali clocking is provided by two identical clock paths 270 * MALI_0 and MALI_1 muxed to a single clock by a glitch 271 * free mux to safely change frequency while running. 272 */ 273 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 274 <&clkc CLKID_MALI_0>, 275 <&clkc CLKID_MALI>; /* Glitch free mux */ 276 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 277 <0>, /* Do Nothing */ 278 <&clkc CLKID_MALI_0>; 279 assigned-clock-rates = <0>, /* Do Nothing */ 280 <666666666>, 281 <0>; /* Do Nothing */ 282 }; 283}; 284 285&cbus { 286 spifc: spi@8c80 { 287 compatible = "amlogic,meson-gxbb-spifc"; 288 reg = <0x0 0x08c80 0x0 0x80>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 clocks = <&clkc CLKID_SPI>; 292 status = "disabled"; 293 }; 294}; 295 296ðmac { 297 clocks = <&clkc CLKID_ETH>, 298 <&clkc CLKID_FCLK_DIV2>, 299 <&clkc CLKID_MPLL2>; 300 clock-names = "stmmaceth", "clkin0", "clkin1"; 301}; 302 303&hdmi_tx { 304 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; 305 resets = <&reset RESET_HDMITX_CAPB3>, 306 <&reset RESET_HDMI_SYSTEM_RESET>, 307 <&reset RESET_HDMI_TX>; 308 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 309 clocks = <&clkc CLKID_HDMI_PCLK>, 310 <&clkc CLKID_CLK81>, 311 <&clkc CLKID_GCLK_VENCI_INT0>; 312 clock-names = "isfr", "iahb", "venci"; 313}; 314 315&hiubus { 316 clkc: clock-controller@0 { 317 compatible = "amlogic,gxbb-clkc"; 318 #clock-cells = <1>; 319 reg = <0x0 0x0 0x0 0x3db>; 320 }; 321}; 322 323&hwrng { 324 clocks = <&clkc CLKID_RNG0>; 325 clock-names = "core"; 326}; 327 328&i2c_A { 329 clocks = <&clkc CLKID_I2C>; 330}; 331 332&i2c_AO { 333 clocks = <&clkc CLKID_AO_I2C>; 334}; 335 336&i2c_B { 337 clocks = <&clkc CLKID_I2C>; 338}; 339 340&i2c_C { 341 clocks = <&clkc CLKID_I2C>; 342}; 343 344&periphs { 345 pinctrl_periphs: pinctrl@4b0 { 346 compatible = "amlogic,meson-gxbb-periphs-pinctrl"; 347 #address-cells = <2>; 348 #size-cells = <2>; 349 ranges; 350 351 gpio: bank@4b0 { 352 reg = <0x0 0x004b0 0x0 0x28>, 353 <0x0 0x004e8 0x0 0x14>, 354 <0x0 0x00520 0x0 0x14>, 355 <0x0 0x00430 0x0 0x40>; 356 reg-names = "mux", "pull", "pull-enable", "gpio"; 357 gpio-controller; 358 #gpio-cells = <2>; 359 gpio-ranges = <&pinctrl_periphs 0 14 120>; 360 }; 361 362 emmc_pins: emmc { 363 mux { 364 groups = "emmc_nand_d07", 365 "emmc_cmd", 366 "emmc_clk", 367 "emmc_ds"; 368 function = "emmc"; 369 }; 370 }; 371 372 nor_pins: nor { 373 mux { 374 groups = "nor_d", 375 "nor_q", 376 "nor_c", 377 "nor_cs"; 378 function = "nor"; 379 }; 380 }; 381 382 sdcard_pins: sdcard { 383 mux { 384 groups = "sdcard_d0", 385 "sdcard_d1", 386 "sdcard_d2", 387 "sdcard_d3", 388 "sdcard_cmd", 389 "sdcard_clk"; 390 function = "sdcard"; 391 }; 392 }; 393 394 sdio_pins: sdio { 395 mux { 396 groups = "sdio_d0", 397 "sdio_d1", 398 "sdio_d2", 399 "sdio_d3", 400 "sdio_cmd", 401 "sdio_clk"; 402 function = "sdio"; 403 }; 404 }; 405 406 sdio_irq_pins: sdio_irq { 407 mux { 408 groups = "sdio_irq"; 409 function = "sdio"; 410 }; 411 }; 412 413 uart_a_pins: uart_a { 414 mux { 415 groups = "uart_tx_a", 416 "uart_rx_a"; 417 function = "uart_a"; 418 }; 419 }; 420 421 uart_a_cts_rts_pins: uart_a_cts_rts { 422 mux { 423 groups = "uart_cts_a", 424 "uart_rts_a"; 425 function = "uart_a"; 426 }; 427 }; 428 429 uart_b_pins: uart_b { 430 mux { 431 groups = "uart_tx_b", 432 "uart_rx_b"; 433 function = "uart_b"; 434 }; 435 }; 436 437 uart_b_cts_rts_pins: uart_b_cts_rts { 438 mux { 439 groups = "uart_cts_b", 440 "uart_rts_b"; 441 function = "uart_b"; 442 }; 443 }; 444 445 uart_c_pins: uart_c { 446 mux { 447 groups = "uart_tx_c", 448 "uart_rx_c"; 449 function = "uart_c"; 450 }; 451 }; 452 453 uart_c_cts_rts_pins: uart_c_cts_rts { 454 mux { 455 groups = "uart_cts_c", 456 "uart_rts_c"; 457 function = "uart_c"; 458 }; 459 }; 460 461 i2c_a_pins: i2c_a { 462 mux { 463 groups = "i2c_sck_a", 464 "i2c_sda_a"; 465 function = "i2c_a"; 466 }; 467 }; 468 469 i2c_b_pins: i2c_b { 470 mux { 471 groups = "i2c_sck_b", 472 "i2c_sda_b"; 473 function = "i2c_b"; 474 }; 475 }; 476 477 i2c_c_pins: i2c_c { 478 mux { 479 groups = "i2c_sck_c", 480 "i2c_sda_c"; 481 function = "i2c_c"; 482 }; 483 }; 484 485 eth_rgmii_pins: eth-rgmii { 486 mux { 487 groups = "eth_mdio", 488 "eth_mdc", 489 "eth_clk_rx_clk", 490 "eth_rx_dv", 491 "eth_rxd0", 492 "eth_rxd1", 493 "eth_rxd2", 494 "eth_rxd3", 495 "eth_rgmii_tx_clk", 496 "eth_tx_en", 497 "eth_txd0", 498 "eth_txd1", 499 "eth_txd2", 500 "eth_txd3"; 501 function = "eth"; 502 }; 503 }; 504 505 eth_rmii_pins: eth-rmii { 506 mux { 507 groups = "eth_mdio", 508 "eth_mdc", 509 "eth_clk_rx_clk", 510 "eth_rx_dv", 511 "eth_rxd0", 512 "eth_rxd1", 513 "eth_tx_en", 514 "eth_txd0", 515 "eth_txd1"; 516 function = "eth"; 517 }; 518 }; 519 520 pwm_a_x_pins: pwm_a_x { 521 mux { 522 groups = "pwm_a_x"; 523 function = "pwm_a_x"; 524 }; 525 }; 526 527 pwm_a_y_pins: pwm_a_y { 528 mux { 529 groups = "pwm_a_y"; 530 function = "pwm_a_y"; 531 }; 532 }; 533 534 pwm_b_pins: pwm_b { 535 mux { 536 groups = "pwm_b"; 537 function = "pwm_b"; 538 }; 539 }; 540 541 pwm_d_pins: pwm_d { 542 mux { 543 groups = "pwm_d"; 544 function = "pwm_d"; 545 }; 546 }; 547 548 pwm_e_pins: pwm_e { 549 mux { 550 groups = "pwm_e"; 551 function = "pwm_e"; 552 }; 553 }; 554 555 pwm_f_x_pins: pwm_f_x { 556 mux { 557 groups = "pwm_f_x"; 558 function = "pwm_f_x"; 559 }; 560 }; 561 562 pwm_f_y_pins: pwm_f_y { 563 mux { 564 groups = "pwm_f_y"; 565 function = "pwm_f_y"; 566 }; 567 }; 568 569 hdmi_hpd_pins: hdmi_hpd { 570 mux { 571 groups = "hdmi_hpd"; 572 function = "hdmi_hpd"; 573 }; 574 }; 575 576 hdmi_i2c_pins: hdmi_i2c { 577 mux { 578 groups = "hdmi_sda", "hdmi_scl"; 579 function = "hdmi_i2c"; 580 }; 581 }; 582 583 i2sout_ch23_y_pins: i2sout_ch23_y { 584 mux { 585 groups = "i2sout_ch23_y"; 586 function = "i2s_out"; 587 }; 588 }; 589 590 i2sout_ch45_y_pins: i2sout_ch45_y { 591 mux { 592 groups = "i2sout_ch45_y"; 593 function = "i2s_out"; 594 }; 595 }; 596 597 i2sout_ch67_y_pins: i2sout_ch67_y { 598 mux { 599 groups = "i2sout_ch67_y"; 600 function = "i2s_out"; 601 }; 602 }; 603 604 spdif_out_y_pins: spdif_out_y { 605 mux { 606 groups = "spdif_out_y"; 607 function = "spdif_out"; 608 }; 609 }; 610 }; 611}; 612 613&saradc { 614 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; 615 clocks = <&xtal>, 616 <&clkc CLKID_SAR_ADC>, 617 <&clkc CLKID_SANA>, 618 <&clkc CLKID_SAR_ADC_CLK>, 619 <&clkc CLKID_SAR_ADC_SEL>; 620 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 621}; 622 623&sd_emmc_a { 624 clocks = <&clkc CLKID_SD_EMMC_A>, 625 <&xtal>, 626 <&clkc CLKID_FCLK_DIV2>; 627 clock-names = "core", "clkin0", "clkin1"; 628}; 629 630&sd_emmc_b { 631 clocks = <&clkc CLKID_SD_EMMC_B>, 632 <&xtal>, 633 <&clkc CLKID_FCLK_DIV2>; 634 clock-names = "core", "clkin0", "clkin1"; 635}; 636 637&sd_emmc_c { 638 clocks = <&clkc CLKID_SD_EMMC_C>, 639 <&xtal>, 640 <&clkc CLKID_FCLK_DIV2>; 641 clock-names = "core", "clkin0", "clkin1"; 642}; 643 644&spifc { 645 clocks = <&clkc CLKID_SPI>; 646}; 647 648&vpu { 649 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; 650}; 651