1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "meson-gx.dtsi" 44#include <dt-bindings/gpio/meson-gxbb-gpio.h> 45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 46#include <dt-bindings/clock/gxbb-clkc.h> 47#include <dt-bindings/clock/gxbb-aoclkc.h> 48#include <dt-bindings/reset/gxbb-aoclkc.h> 49 50/ { 51 compatible = "amlogic,meson-gxbb"; 52 53 soc { 54 usb0_phy: phy@c0000000 { 55 compatible = "amlogic,meson-gxbb-usb2-phy"; 56 #phy-cells = <0>; 57 reg = <0x0 0xc0000000 0x0 0x20>; 58 resets = <&reset RESET_USB_OTG>; 59 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 60 clock-names = "usb_general", "usb"; 61 status = "disabled"; 62 }; 63 64 usb1_phy: phy@c0000020 { 65 compatible = "amlogic,meson-gxbb-usb2-phy"; 66 #phy-cells = <0>; 67 reg = <0x0 0xc0000020 0x0 0x20>; 68 resets = <&reset RESET_USB_OTG>; 69 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 70 clock-names = "usb_general", "usb"; 71 status = "disabled"; 72 }; 73 74 usb0: usb@c9000000 { 75 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 76 reg = <0x0 0xc9000000 0x0 0x40000>; 77 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 79 clock-names = "otg"; 80 phys = <&usb0_phy>; 81 phy-names = "usb2-phy"; 82 dr_mode = "host"; 83 status = "disabled"; 84 }; 85 86 usb1: usb@c9100000 { 87 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 88 reg = <0x0 0xc9100000 0x0 0x40000>; 89 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 91 clock-names = "otg"; 92 phys = <&usb1_phy>; 93 phy-names = "usb2-phy"; 94 dr_mode = "host"; 95 status = "disabled"; 96 }; 97 }; 98}; 99 100ðmac { 101 clocks = <&clkc CLKID_ETH>, 102 <&clkc CLKID_FCLK_DIV2>, 103 <&clkc CLKID_MPLL2>; 104 clock-names = "stmmaceth", "clkin0", "clkin1"; 105}; 106 107&aobus { 108 pinctrl_aobus: pinctrl@14 { 109 compatible = "amlogic,meson-gxbb-aobus-pinctrl"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges; 113 114 gpio_ao: bank@14 { 115 reg = <0x0 0x00014 0x0 0x8>, 116 <0x0 0x0002c 0x0 0x4>, 117 <0x0 0x00024 0x0 0x8>; 118 reg-names = "mux", "pull", "gpio"; 119 gpio-controller; 120 #gpio-cells = <2>; 121 }; 122 123 uart_ao_a_pins: uart_ao_a { 124 mux { 125 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 126 function = "uart_ao"; 127 }; 128 }; 129 130 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 131 mux { 132 groups = "uart_cts_ao_a", 133 "uart_rts_ao_a"; 134 function = "uart_ao"; 135 }; 136 }; 137 138 uart_ao_b_pins: uart_ao_b { 139 mux { 140 groups = "uart_tx_ao_b", "uart_rx_ao_b"; 141 function = "uart_ao_b"; 142 }; 143 }; 144 145 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 146 mux { 147 groups = "uart_cts_ao_b", 148 "uart_rts_ao_b"; 149 function = "uart_ao_b"; 150 }; 151 }; 152 153 remote_input_ao_pins: remote_input_ao { 154 mux { 155 groups = "remote_input_ao"; 156 function = "remote_input_ao"; 157 }; 158 }; 159 160 i2c_ao_pins: i2c_ao { 161 mux { 162 groups = "i2c_sck_ao", 163 "i2c_sda_ao"; 164 function = "i2c_ao"; 165 }; 166 }; 167 168 pwm_ao_a_3_pins: pwm_ao_a_3 { 169 mux { 170 groups = "pwm_ao_a_3"; 171 function = "pwm_ao_a_3"; 172 }; 173 }; 174 175 pwm_ao_a_6_pins: pwm_ao_a_6 { 176 mux { 177 groups = "pwm_ao_a_6"; 178 function = "pwm_ao_a_6"; 179 }; 180 }; 181 182 pwm_ao_a_12_pins: pwm_ao_a_12 { 183 mux { 184 groups = "pwm_ao_a_12"; 185 function = "pwm_ao_a_12"; 186 }; 187 }; 188 189 pwm_ao_b_pins: pwm_ao_b { 190 mux { 191 groups = "pwm_ao_b"; 192 function = "pwm_ao_b"; 193 }; 194 }; 195 }; 196}; 197 198&periphs { 199 pinctrl_periphs: pinctrl@4b0 { 200 compatible = "amlogic,meson-gxbb-periphs-pinctrl"; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 gpio: bank@4b0 { 206 reg = <0x0 0x004b0 0x0 0x28>, 207 <0x0 0x004e8 0x0 0x14>, 208 <0x0 0x00120 0x0 0x14>, 209 <0x0 0x00430 0x0 0x40>; 210 reg-names = "mux", "pull", "pull-enable", "gpio"; 211 gpio-controller; 212 #gpio-cells = <2>; 213 }; 214 215 emmc_pins: emmc { 216 mux { 217 groups = "emmc_nand_d07", 218 "emmc_cmd", 219 "emmc_clk", 220 "emmc_ds"; 221 function = "emmc"; 222 }; 223 }; 224 225 nor_pins: nor { 226 mux { 227 groups = "nor_d", 228 "nor_q", 229 "nor_c", 230 "nor_cs"; 231 function = "nor"; 232 }; 233 }; 234 235 sdcard_pins: sdcard { 236 mux { 237 groups = "sdcard_d0", 238 "sdcard_d1", 239 "sdcard_d2", 240 "sdcard_d3", 241 "sdcard_cmd", 242 "sdcard_clk"; 243 function = "sdcard"; 244 }; 245 }; 246 247 sdio_pins: sdio { 248 mux { 249 groups = "sdio_d0", 250 "sdio_d1", 251 "sdio_d2", 252 "sdio_d3", 253 "sdio_cmd", 254 "sdio_clk"; 255 function = "sdio"; 256 }; 257 }; 258 259 sdio_irq_pins: sdio_irq { 260 mux { 261 groups = "sdio_irq"; 262 function = "sdio"; 263 }; 264 }; 265 266 uart_a_pins: uart_a { 267 mux { 268 groups = "uart_tx_a", 269 "uart_rx_a"; 270 function = "uart_a"; 271 }; 272 }; 273 274 uart_a_cts_rts_pins: uart_a_cts_rts { 275 mux { 276 groups = "uart_cts_a", 277 "uart_rts_a"; 278 function = "uart_a"; 279 }; 280 }; 281 282 uart_b_pins: uart_b { 283 mux { 284 groups = "uart_tx_b", 285 "uart_rx_b"; 286 function = "uart_b"; 287 }; 288 }; 289 290 uart_b_cts_rts_pins: uart_b_cts_rts { 291 mux { 292 groups = "uart_cts_b", 293 "uart_rts_b"; 294 function = "uart_b"; 295 }; 296 }; 297 298 uart_c_pins: uart_c { 299 mux { 300 groups = "uart_tx_c", 301 "uart_rx_c"; 302 function = "uart_c"; 303 }; 304 }; 305 306 uart_c_cts_rts_pins: uart_c_cts_rts { 307 mux { 308 groups = "uart_cts_c", 309 "uart_rts_c"; 310 function = "uart_c"; 311 }; 312 }; 313 314 i2c_a_pins: i2c_a { 315 mux { 316 groups = "i2c_sck_a", 317 "i2c_sda_a"; 318 function = "i2c_a"; 319 }; 320 }; 321 322 i2c_b_pins: i2c_b { 323 mux { 324 groups = "i2c_sck_b", 325 "i2c_sda_b"; 326 function = "i2c_b"; 327 }; 328 }; 329 330 i2c_c_pins: i2c_c { 331 mux { 332 groups = "i2c_sck_c", 333 "i2c_sda_c"; 334 function = "i2c_c"; 335 }; 336 }; 337 338 eth_rgmii_pins: eth-rgmii { 339 mux { 340 groups = "eth_mdio", 341 "eth_mdc", 342 "eth_clk_rx_clk", 343 "eth_rx_dv", 344 "eth_rxd0", 345 "eth_rxd1", 346 "eth_rxd2", 347 "eth_rxd3", 348 "eth_rgmii_tx_clk", 349 "eth_tx_en", 350 "eth_txd0", 351 "eth_txd1", 352 "eth_txd2", 353 "eth_txd3"; 354 function = "eth"; 355 }; 356 }; 357 358 eth_rmii_pins: eth-rmii { 359 mux { 360 groups = "eth_mdio", 361 "eth_mdc", 362 "eth_clk_rx_clk", 363 "eth_rx_dv", 364 "eth_rxd0", 365 "eth_rxd1", 366 "eth_tx_en", 367 "eth_txd0", 368 "eth_txd1"; 369 function = "eth"; 370 }; 371 }; 372 373 pwm_a_x_pins: pwm_a_x { 374 mux { 375 groups = "pwm_a_x"; 376 function = "pwm_a_x"; 377 }; 378 }; 379 380 pwm_a_y_pins: pwm_a_y { 381 mux { 382 groups = "pwm_a_y"; 383 function = "pwm_a_y"; 384 }; 385 }; 386 387 pwm_b_pins: pwm_b { 388 mux { 389 groups = "pwm_b"; 390 function = "pwm_b"; 391 }; 392 }; 393 394 pwm_d_pins: pwm_d { 395 mux { 396 groups = "pwm_d"; 397 function = "pwm_d"; 398 }; 399 }; 400 401 pwm_e_pins: pwm_e { 402 mux { 403 groups = "pwm_e"; 404 function = "pwm_e"; 405 }; 406 }; 407 408 pwm_f_x_pins: pwm_f_x { 409 mux { 410 groups = "pwm_f_x"; 411 function = "pwm_f_x"; 412 }; 413 }; 414 415 pwm_f_y_pins: pwm_f_y { 416 mux { 417 groups = "pwm_f_y"; 418 function = "pwm_f_y"; 419 }; 420 }; 421 422 hdmi_hpd_pins: hdmi_hpd { 423 mux { 424 groups = "hdmi_hpd"; 425 function = "hdmi_hpd"; 426 }; 427 }; 428 429 hdmi_i2c_pins: hdmi_i2c { 430 mux { 431 groups = "hdmi_sda", "hdmi_scl"; 432 function = "hdmi_i2c"; 433 }; 434 }; 435 }; 436}; 437 438&hiubus { 439 clkc: clock-controller@0 { 440 compatible = "amlogic,gxbb-clkc"; 441 #clock-cells = <1>; 442 reg = <0x0 0x0 0x0 0x3db>; 443 }; 444}; 445 446&apb { 447 mali: gpu@c0000 { 448 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; 449 reg = <0x0 0xc0000 0x0 0x40000>; 450 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 460 interrupt-names = "gp", "gpmmu", "pp", "pmu", 461 "pp0", "ppmmu0", "pp1", "ppmmu1", 462 "pp2", "ppmmu2"; 463 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 464 clock-names = "bus", "core"; 465 466 /* 467 * Mali clocking is provided by two identical clock paths 468 * MALI_0 and MALI_1 muxed to a single clock by a glitch 469 * free mux to safely change frequency while running. 470 */ 471 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 472 <&clkc CLKID_MALI_0>, 473 <&clkc CLKID_MALI>; /* Glitch free mux */ 474 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 475 <0>, /* Do Nothing */ 476 <&clkc CLKID_MALI_0>; 477 assigned-clock-rates = <0>, /* Do Nothing */ 478 <666666666>, 479 <0>; /* Do Nothing */ 480 }; 481}; 482 483&i2c_A { 484 clocks = <&clkc CLKID_I2C>; 485}; 486 487&i2c_AO { 488 clocks = <&clkc CLKID_AO_I2C>; 489}; 490 491&i2c_B { 492 clocks = <&clkc CLKID_I2C>; 493}; 494 495&i2c_C { 496 clocks = <&clkc CLKID_I2C>; 497}; 498 499&saradc { 500 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; 501 clocks = <&xtal>, 502 <&clkc CLKID_SAR_ADC>, 503 <&clkc CLKID_SANA>, 504 <&clkc CLKID_SAR_ADC_CLK>, 505 <&clkc CLKID_SAR_ADC_SEL>; 506 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 507}; 508 509&sd_emmc_a { 510 clocks = <&clkc CLKID_SD_EMMC_A>, 511 <&xtal>, 512 <&clkc CLKID_FCLK_DIV2>; 513 clock-names = "core", "clkin0", "clkin1"; 514}; 515 516&sd_emmc_b { 517 clocks = <&clkc CLKID_SD_EMMC_B>, 518 <&xtal>, 519 <&clkc CLKID_FCLK_DIV2>; 520 clock-names = "core", "clkin0", "clkin1"; 521}; 522 523&sd_emmc_c { 524 clocks = <&clkc CLKID_SD_EMMC_C>, 525 <&xtal>, 526 <&clkc CLKID_FCLK_DIV2>; 527 clock-names = "core", "clkin0", "clkin1"; 528}; 529 530&spifc { 531 clocks = <&clkc CLKID_SPI>; 532}; 533 534&vpu { 535 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; 536}; 537