1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "meson-gx.dtsi" 44#include <dt-bindings/gpio/meson-gxbb-gpio.h> 45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 46#include <dt-bindings/clock/gxbb-clkc.h> 47#include <dt-bindings/clock/gxbb-aoclkc.h> 48#include <dt-bindings/reset/gxbb-aoclkc.h> 49 50/ { 51 compatible = "amlogic,meson-gxbb"; 52 53 soc { 54 usb0_phy: phy@c0000000 { 55 compatible = "amlogic,meson-gxbb-usb2-phy"; 56 #phy-cells = <0>; 57 reg = <0x0 0xc0000000 0x0 0x20>; 58 resets = <&reset RESET_USB_OTG>; 59 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 60 clock-names = "usb_general", "usb"; 61 status = "disabled"; 62 }; 63 64 usb1_phy: phy@c0000020 { 65 compatible = "amlogic,meson-gxbb-usb2-phy"; 66 #phy-cells = <0>; 67 reg = <0x0 0xc0000020 0x0 0x20>; 68 resets = <&reset RESET_USB_OTG>; 69 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 70 clock-names = "usb_general", "usb"; 71 status = "disabled"; 72 }; 73 74 usb0: usb@c9000000 { 75 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 76 reg = <0x0 0xc9000000 0x0 0x40000>; 77 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 79 clock-names = "otg"; 80 phys = <&usb0_phy>; 81 phy-names = "usb2-phy"; 82 dr_mode = "host"; 83 status = "disabled"; 84 }; 85 86 usb1: usb@c9100000 { 87 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 88 reg = <0x0 0xc9100000 0x0 0x40000>; 89 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 91 clock-names = "otg"; 92 phys = <&usb1_phy>; 93 phy-names = "usb2-phy"; 94 dr_mode = "host"; 95 status = "disabled"; 96 }; 97 }; 98}; 99 100ðmac { 101 clocks = <&clkc CLKID_ETH>, 102 <&clkc CLKID_FCLK_DIV2>, 103 <&clkc CLKID_MPLL2>; 104 clock-names = "stmmaceth", "clkin0", "clkin1"; 105}; 106 107&aobus { 108 pinctrl_aobus: pinctrl@14 { 109 compatible = "amlogic,meson-gxbb-aobus-pinctrl"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges; 113 114 gpio_ao: bank@14 { 115 reg = <0x0 0x00014 0x0 0x8>, 116 <0x0 0x0002c 0x0 0x4>, 117 <0x0 0x00024 0x0 0x8>; 118 reg-names = "mux", "pull", "gpio"; 119 gpio-controller; 120 #gpio-cells = <2>; 121 gpio-ranges = <&pinctrl_aobus 0 0 14>; 122 }; 123 124 uart_ao_a_pins: uart_ao_a { 125 mux { 126 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 127 function = "uart_ao"; 128 }; 129 }; 130 131 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 132 mux { 133 groups = "uart_cts_ao_a", 134 "uart_rts_ao_a"; 135 function = "uart_ao"; 136 }; 137 }; 138 139 uart_ao_b_pins: uart_ao_b { 140 mux { 141 groups = "uart_tx_ao_b", "uart_rx_ao_b"; 142 function = "uart_ao_b"; 143 }; 144 }; 145 146 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 147 mux { 148 groups = "uart_cts_ao_b", 149 "uart_rts_ao_b"; 150 function = "uart_ao_b"; 151 }; 152 }; 153 154 remote_input_ao_pins: remote_input_ao { 155 mux { 156 groups = "remote_input_ao"; 157 function = "remote_input_ao"; 158 }; 159 }; 160 161 i2c_ao_pins: i2c_ao { 162 mux { 163 groups = "i2c_sck_ao", 164 "i2c_sda_ao"; 165 function = "i2c_ao"; 166 }; 167 }; 168 169 pwm_ao_a_3_pins: pwm_ao_a_3 { 170 mux { 171 groups = "pwm_ao_a_3"; 172 function = "pwm_ao_a_3"; 173 }; 174 }; 175 176 pwm_ao_a_6_pins: pwm_ao_a_6 { 177 mux { 178 groups = "pwm_ao_a_6"; 179 function = "pwm_ao_a_6"; 180 }; 181 }; 182 183 pwm_ao_a_12_pins: pwm_ao_a_12 { 184 mux { 185 groups = "pwm_ao_a_12"; 186 function = "pwm_ao_a_12"; 187 }; 188 }; 189 190 pwm_ao_b_pins: pwm_ao_b { 191 mux { 192 groups = "pwm_ao_b"; 193 function = "pwm_ao_b"; 194 }; 195 }; 196 197 i2s_am_clk_pins: i2s_am_clk { 198 mux { 199 groups = "i2s_am_clk"; 200 function = "i2s_out_ao"; 201 }; 202 }; 203 204 i2s_out_ao_clk_pins: i2s_out_ao_clk { 205 mux { 206 groups = "i2s_out_ao_clk"; 207 function = "i2s_out_ao"; 208 }; 209 }; 210 211 i2s_out_lr_clk_pins: i2s_out_lr_clk { 212 mux { 213 groups = "i2s_out_lr_clk"; 214 function = "i2s_out_ao"; 215 }; 216 }; 217 218 i2s_out_ch01_ao_pins: i2s_out_ch01_ao { 219 mux { 220 groups = "i2s_out_ch01_ao"; 221 function = "i2s_out_ao"; 222 }; 223 }; 224 225 i2s_out_ch23_ao_pins: i2s_out_ch23_ao { 226 mux { 227 groups = "i2s_out_ch23_ao"; 228 function = "i2s_out_ao"; 229 }; 230 }; 231 232 i2s_out_ch45_ao_pins: i2s_out_ch45_ao { 233 mux { 234 groups = "i2s_out_ch45_ao"; 235 function = "i2s_out_ao"; 236 }; 237 }; 238 }; 239}; 240 241&periphs { 242 pinctrl_periphs: pinctrl@4b0 { 243 compatible = "amlogic,meson-gxbb-periphs-pinctrl"; 244 #address-cells = <2>; 245 #size-cells = <2>; 246 ranges; 247 248 gpio: bank@4b0 { 249 reg = <0x0 0x004b0 0x0 0x28>, 250 <0x0 0x004e8 0x0 0x14>, 251 <0x0 0x00120 0x0 0x14>, 252 <0x0 0x00430 0x0 0x40>; 253 reg-names = "mux", "pull", "pull-enable", "gpio"; 254 gpio-controller; 255 #gpio-cells = <2>; 256 gpio-ranges = <&pinctrl_periphs 0 14 120>; 257 }; 258 259 emmc_pins: emmc { 260 mux { 261 groups = "emmc_nand_d07", 262 "emmc_cmd", 263 "emmc_clk", 264 "emmc_ds"; 265 function = "emmc"; 266 }; 267 }; 268 269 nor_pins: nor { 270 mux { 271 groups = "nor_d", 272 "nor_q", 273 "nor_c", 274 "nor_cs"; 275 function = "nor"; 276 }; 277 }; 278 279 sdcard_pins: sdcard { 280 mux { 281 groups = "sdcard_d0", 282 "sdcard_d1", 283 "sdcard_d2", 284 "sdcard_d3", 285 "sdcard_cmd", 286 "sdcard_clk"; 287 function = "sdcard"; 288 }; 289 }; 290 291 sdio_pins: sdio { 292 mux { 293 groups = "sdio_d0", 294 "sdio_d1", 295 "sdio_d2", 296 "sdio_d3", 297 "sdio_cmd", 298 "sdio_clk"; 299 function = "sdio"; 300 }; 301 }; 302 303 sdio_irq_pins: sdio_irq { 304 mux { 305 groups = "sdio_irq"; 306 function = "sdio"; 307 }; 308 }; 309 310 uart_a_pins: uart_a { 311 mux { 312 groups = "uart_tx_a", 313 "uart_rx_a"; 314 function = "uart_a"; 315 }; 316 }; 317 318 uart_a_cts_rts_pins: uart_a_cts_rts { 319 mux { 320 groups = "uart_cts_a", 321 "uart_rts_a"; 322 function = "uart_a"; 323 }; 324 }; 325 326 uart_b_pins: uart_b { 327 mux { 328 groups = "uart_tx_b", 329 "uart_rx_b"; 330 function = "uart_b"; 331 }; 332 }; 333 334 uart_b_cts_rts_pins: uart_b_cts_rts { 335 mux { 336 groups = "uart_cts_b", 337 "uart_rts_b"; 338 function = "uart_b"; 339 }; 340 }; 341 342 uart_c_pins: uart_c { 343 mux { 344 groups = "uart_tx_c", 345 "uart_rx_c"; 346 function = "uart_c"; 347 }; 348 }; 349 350 uart_c_cts_rts_pins: uart_c_cts_rts { 351 mux { 352 groups = "uart_cts_c", 353 "uart_rts_c"; 354 function = "uart_c"; 355 }; 356 }; 357 358 i2c_a_pins: i2c_a { 359 mux { 360 groups = "i2c_sck_a", 361 "i2c_sda_a"; 362 function = "i2c_a"; 363 }; 364 }; 365 366 i2c_b_pins: i2c_b { 367 mux { 368 groups = "i2c_sck_b", 369 "i2c_sda_b"; 370 function = "i2c_b"; 371 }; 372 }; 373 374 i2c_c_pins: i2c_c { 375 mux { 376 groups = "i2c_sck_c", 377 "i2c_sda_c"; 378 function = "i2c_c"; 379 }; 380 }; 381 382 eth_rgmii_pins: eth-rgmii { 383 mux { 384 groups = "eth_mdio", 385 "eth_mdc", 386 "eth_clk_rx_clk", 387 "eth_rx_dv", 388 "eth_rxd0", 389 "eth_rxd1", 390 "eth_rxd2", 391 "eth_rxd3", 392 "eth_rgmii_tx_clk", 393 "eth_tx_en", 394 "eth_txd0", 395 "eth_txd1", 396 "eth_txd2", 397 "eth_txd3"; 398 function = "eth"; 399 }; 400 }; 401 402 eth_rmii_pins: eth-rmii { 403 mux { 404 groups = "eth_mdio", 405 "eth_mdc", 406 "eth_clk_rx_clk", 407 "eth_rx_dv", 408 "eth_rxd0", 409 "eth_rxd1", 410 "eth_tx_en", 411 "eth_txd0", 412 "eth_txd1"; 413 function = "eth"; 414 }; 415 }; 416 417 pwm_a_x_pins: pwm_a_x { 418 mux { 419 groups = "pwm_a_x"; 420 function = "pwm_a_x"; 421 }; 422 }; 423 424 pwm_a_y_pins: pwm_a_y { 425 mux { 426 groups = "pwm_a_y"; 427 function = "pwm_a_y"; 428 }; 429 }; 430 431 pwm_b_pins: pwm_b { 432 mux { 433 groups = "pwm_b"; 434 function = "pwm_b"; 435 }; 436 }; 437 438 pwm_d_pins: pwm_d { 439 mux { 440 groups = "pwm_d"; 441 function = "pwm_d"; 442 }; 443 }; 444 445 pwm_e_pins: pwm_e { 446 mux { 447 groups = "pwm_e"; 448 function = "pwm_e"; 449 }; 450 }; 451 452 pwm_f_x_pins: pwm_f_x { 453 mux { 454 groups = "pwm_f_x"; 455 function = "pwm_f_x"; 456 }; 457 }; 458 459 pwm_f_y_pins: pwm_f_y { 460 mux { 461 groups = "pwm_f_y"; 462 function = "pwm_f_y"; 463 }; 464 }; 465 466 hdmi_hpd_pins: hdmi_hpd { 467 mux { 468 groups = "hdmi_hpd"; 469 function = "hdmi_hpd"; 470 }; 471 }; 472 473 hdmi_i2c_pins: hdmi_i2c { 474 mux { 475 groups = "hdmi_sda", "hdmi_scl"; 476 function = "hdmi_i2c"; 477 }; 478 }; 479 480 i2sout_ch23_y_pins: i2sout_ch23_y { 481 mux { 482 groups = "i2sout_ch23_y"; 483 function = "i2s_out"; 484 }; 485 }; 486 487 i2sout_ch45_y_pins: i2sout_ch45_y { 488 mux { 489 groups = "i2sout_ch45_y"; 490 function = "i2s_out"; 491 }; 492 }; 493 494 i2sout_ch67_y_pins: i2sout_ch67_y { 495 mux { 496 groups = "i2sout_ch67_y"; 497 function = "i2s_out"; 498 }; 499 }; 500 }; 501}; 502 503&hiubus { 504 clkc: clock-controller@0 { 505 compatible = "amlogic,gxbb-clkc"; 506 #clock-cells = <1>; 507 reg = <0x0 0x0 0x0 0x3db>; 508 }; 509}; 510 511&apb { 512 mali: gpu@c0000 { 513 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; 514 reg = <0x0 0xc0000 0x0 0x40000>; 515 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "gp", "gpmmu", "pp", "pmu", 526 "pp0", "ppmmu0", "pp1", "ppmmu1", 527 "pp2", "ppmmu2"; 528 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 529 clock-names = "bus", "core"; 530 531 /* 532 * Mali clocking is provided by two identical clock paths 533 * MALI_0 and MALI_1 muxed to a single clock by a glitch 534 * free mux to safely change frequency while running. 535 */ 536 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 537 <&clkc CLKID_MALI_0>, 538 <&clkc CLKID_MALI>; /* Glitch free mux */ 539 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 540 <0>, /* Do Nothing */ 541 <&clkc CLKID_MALI_0>; 542 assigned-clock-rates = <0>, /* Do Nothing */ 543 <666666666>, 544 <0>; /* Do Nothing */ 545 }; 546}; 547 548&i2c_A { 549 clocks = <&clkc CLKID_I2C>; 550}; 551 552&i2c_AO { 553 clocks = <&clkc CLKID_AO_I2C>; 554}; 555 556&i2c_B { 557 clocks = <&clkc CLKID_I2C>; 558}; 559 560&i2c_C { 561 clocks = <&clkc CLKID_I2C>; 562}; 563 564&saradc { 565 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; 566 clocks = <&xtal>, 567 <&clkc CLKID_SAR_ADC>, 568 <&clkc CLKID_SANA>, 569 <&clkc CLKID_SAR_ADC_CLK>, 570 <&clkc CLKID_SAR_ADC_SEL>; 571 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 572}; 573 574&sd_emmc_a { 575 clocks = <&clkc CLKID_SD_EMMC_A>, 576 <&xtal>, 577 <&clkc CLKID_FCLK_DIV2>; 578 clock-names = "core", "clkin0", "clkin1"; 579}; 580 581&sd_emmc_b { 582 clocks = <&clkc CLKID_SD_EMMC_B>, 583 <&xtal>, 584 <&clkc CLKID_FCLK_DIV2>; 585 clock-names = "core", "clkin0", "clkin1"; 586}; 587 588&sd_emmc_c { 589 clocks = <&clkc CLKID_SD_EMMC_C>, 590 <&xtal>, 591 <&clkc CLKID_FCLK_DIV2>; 592 clock-names = "core", "clkin0", "clkin1"; 593}; 594 595&spifc { 596 clocks = <&clkc CLKID_SPI>; 597}; 598 599&vpu { 600 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; 601}; 602