1/* 2 * Copyright (c) 2016 Andreas Färber 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "meson-gx.dtsi" 44#include <dt-bindings/gpio/meson-gxbb-gpio.h> 45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 46#include <dt-bindings/clock/gxbb-clkc.h> 47#include <dt-bindings/clock/gxbb-aoclkc.h> 48#include <dt-bindings/reset/gxbb-aoclkc.h> 49 50/ { 51 compatible = "amlogic,meson-gxbb"; 52 53 soc { 54 usb0_phy: phy@c0000000 { 55 compatible = "amlogic,meson-gxbb-usb2-phy"; 56 #phy-cells = <0>; 57 reg = <0x0 0xc0000000 0x0 0x20>; 58 resets = <&reset RESET_USB_OTG>; 59 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 60 clock-names = "usb_general", "usb"; 61 status = "disabled"; 62 }; 63 64 usb1_phy: phy@c0000020 { 65 compatible = "amlogic,meson-gxbb-usb2-phy"; 66 #phy-cells = <0>; 67 reg = <0x0 0xc0000020 0x0 0x20>; 68 resets = <&reset RESET_USB_OTG>; 69 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 70 clock-names = "usb_general", "usb"; 71 status = "disabled"; 72 }; 73 74 usb0: usb@c9000000 { 75 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 76 reg = <0x0 0xc9000000 0x0 0x40000>; 77 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 79 clock-names = "otg"; 80 phys = <&usb0_phy>; 81 phy-names = "usb2-phy"; 82 dr_mode = "host"; 83 status = "disabled"; 84 }; 85 86 usb1: usb@c9100000 { 87 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; 88 reg = <0x0 0xc9100000 0x0 0x40000>; 89 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 91 clock-names = "otg"; 92 phys = <&usb1_phy>; 93 phy-names = "usb2-phy"; 94 dr_mode = "host"; 95 status = "disabled"; 96 }; 97 }; 98}; 99 100ðmac { 101 clocks = <&clkc CLKID_ETH>, 102 <&clkc CLKID_FCLK_DIV2>, 103 <&clkc CLKID_MPLL2>; 104 clock-names = "stmmaceth", "clkin0", "clkin1"; 105}; 106 107&aobus { 108 pinctrl_aobus: pinctrl@14 { 109 compatible = "amlogic,meson-gxbb-aobus-pinctrl"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges; 113 114 gpio_ao: bank@14 { 115 reg = <0x0 0x00014 0x0 0x8>, 116 <0x0 0x0002c 0x0 0x4>, 117 <0x0 0x00024 0x0 0x8>; 118 reg-names = "mux", "pull", "gpio"; 119 gpio-controller; 120 #gpio-cells = <2>; 121 gpio-ranges = <&pinctrl_aobus 0 0 14>; 122 }; 123 124 uart_ao_a_pins: uart_ao_a { 125 mux { 126 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 127 function = "uart_ao"; 128 }; 129 }; 130 131 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 132 mux { 133 groups = "uart_cts_ao_a", 134 "uart_rts_ao_a"; 135 function = "uart_ao"; 136 }; 137 }; 138 139 uart_ao_b_pins: uart_ao_b { 140 mux { 141 groups = "uart_tx_ao_b", "uart_rx_ao_b"; 142 function = "uart_ao_b"; 143 }; 144 }; 145 146 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 147 mux { 148 groups = "uart_cts_ao_b", 149 "uart_rts_ao_b"; 150 function = "uart_ao_b"; 151 }; 152 }; 153 154 remote_input_ao_pins: remote_input_ao { 155 mux { 156 groups = "remote_input_ao"; 157 function = "remote_input_ao"; 158 }; 159 }; 160 161 i2c_ao_pins: i2c_ao { 162 mux { 163 groups = "i2c_sck_ao", 164 "i2c_sda_ao"; 165 function = "i2c_ao"; 166 }; 167 }; 168 169 pwm_ao_a_3_pins: pwm_ao_a_3 { 170 mux { 171 groups = "pwm_ao_a_3"; 172 function = "pwm_ao_a_3"; 173 }; 174 }; 175 176 pwm_ao_a_6_pins: pwm_ao_a_6 { 177 mux { 178 groups = "pwm_ao_a_6"; 179 function = "pwm_ao_a_6"; 180 }; 181 }; 182 183 pwm_ao_a_12_pins: pwm_ao_a_12 { 184 mux { 185 groups = "pwm_ao_a_12"; 186 function = "pwm_ao_a_12"; 187 }; 188 }; 189 190 pwm_ao_b_pins: pwm_ao_b { 191 mux { 192 groups = "pwm_ao_b"; 193 function = "pwm_ao_b"; 194 }; 195 }; 196 }; 197}; 198 199&periphs { 200 pinctrl_periphs: pinctrl@4b0 { 201 compatible = "amlogic,meson-gxbb-periphs-pinctrl"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 gpio: bank@4b0 { 207 reg = <0x0 0x004b0 0x0 0x28>, 208 <0x0 0x004e8 0x0 0x14>, 209 <0x0 0x00120 0x0 0x14>, 210 <0x0 0x00430 0x0 0x40>; 211 reg-names = "mux", "pull", "pull-enable", "gpio"; 212 gpio-controller; 213 #gpio-cells = <2>; 214 gpio-ranges = <&pinctrl_periphs 0 14 120>; 215 }; 216 217 emmc_pins: emmc { 218 mux { 219 groups = "emmc_nand_d07", 220 "emmc_cmd", 221 "emmc_clk", 222 "emmc_ds"; 223 function = "emmc"; 224 }; 225 }; 226 227 nor_pins: nor { 228 mux { 229 groups = "nor_d", 230 "nor_q", 231 "nor_c", 232 "nor_cs"; 233 function = "nor"; 234 }; 235 }; 236 237 sdcard_pins: sdcard { 238 mux { 239 groups = "sdcard_d0", 240 "sdcard_d1", 241 "sdcard_d2", 242 "sdcard_d3", 243 "sdcard_cmd", 244 "sdcard_clk"; 245 function = "sdcard"; 246 }; 247 }; 248 249 sdio_pins: sdio { 250 mux { 251 groups = "sdio_d0", 252 "sdio_d1", 253 "sdio_d2", 254 "sdio_d3", 255 "sdio_cmd", 256 "sdio_clk"; 257 function = "sdio"; 258 }; 259 }; 260 261 sdio_irq_pins: sdio_irq { 262 mux { 263 groups = "sdio_irq"; 264 function = "sdio"; 265 }; 266 }; 267 268 uart_a_pins: uart_a { 269 mux { 270 groups = "uart_tx_a", 271 "uart_rx_a"; 272 function = "uart_a"; 273 }; 274 }; 275 276 uart_a_cts_rts_pins: uart_a_cts_rts { 277 mux { 278 groups = "uart_cts_a", 279 "uart_rts_a"; 280 function = "uart_a"; 281 }; 282 }; 283 284 uart_b_pins: uart_b { 285 mux { 286 groups = "uart_tx_b", 287 "uart_rx_b"; 288 function = "uart_b"; 289 }; 290 }; 291 292 uart_b_cts_rts_pins: uart_b_cts_rts { 293 mux { 294 groups = "uart_cts_b", 295 "uart_rts_b"; 296 function = "uart_b"; 297 }; 298 }; 299 300 uart_c_pins: uart_c { 301 mux { 302 groups = "uart_tx_c", 303 "uart_rx_c"; 304 function = "uart_c"; 305 }; 306 }; 307 308 uart_c_cts_rts_pins: uart_c_cts_rts { 309 mux { 310 groups = "uart_cts_c", 311 "uart_rts_c"; 312 function = "uart_c"; 313 }; 314 }; 315 316 i2c_a_pins: i2c_a { 317 mux { 318 groups = "i2c_sck_a", 319 "i2c_sda_a"; 320 function = "i2c_a"; 321 }; 322 }; 323 324 i2c_b_pins: i2c_b { 325 mux { 326 groups = "i2c_sck_b", 327 "i2c_sda_b"; 328 function = "i2c_b"; 329 }; 330 }; 331 332 i2c_c_pins: i2c_c { 333 mux { 334 groups = "i2c_sck_c", 335 "i2c_sda_c"; 336 function = "i2c_c"; 337 }; 338 }; 339 340 eth_rgmii_pins: eth-rgmii { 341 mux { 342 groups = "eth_mdio", 343 "eth_mdc", 344 "eth_clk_rx_clk", 345 "eth_rx_dv", 346 "eth_rxd0", 347 "eth_rxd1", 348 "eth_rxd2", 349 "eth_rxd3", 350 "eth_rgmii_tx_clk", 351 "eth_tx_en", 352 "eth_txd0", 353 "eth_txd1", 354 "eth_txd2", 355 "eth_txd3"; 356 function = "eth"; 357 }; 358 }; 359 360 eth_rmii_pins: eth-rmii { 361 mux { 362 groups = "eth_mdio", 363 "eth_mdc", 364 "eth_clk_rx_clk", 365 "eth_rx_dv", 366 "eth_rxd0", 367 "eth_rxd1", 368 "eth_tx_en", 369 "eth_txd0", 370 "eth_txd1"; 371 function = "eth"; 372 }; 373 }; 374 375 pwm_a_x_pins: pwm_a_x { 376 mux { 377 groups = "pwm_a_x"; 378 function = "pwm_a_x"; 379 }; 380 }; 381 382 pwm_a_y_pins: pwm_a_y { 383 mux { 384 groups = "pwm_a_y"; 385 function = "pwm_a_y"; 386 }; 387 }; 388 389 pwm_b_pins: pwm_b { 390 mux { 391 groups = "pwm_b"; 392 function = "pwm_b"; 393 }; 394 }; 395 396 pwm_d_pins: pwm_d { 397 mux { 398 groups = "pwm_d"; 399 function = "pwm_d"; 400 }; 401 }; 402 403 pwm_e_pins: pwm_e { 404 mux { 405 groups = "pwm_e"; 406 function = "pwm_e"; 407 }; 408 }; 409 410 pwm_f_x_pins: pwm_f_x { 411 mux { 412 groups = "pwm_f_x"; 413 function = "pwm_f_x"; 414 }; 415 }; 416 417 pwm_f_y_pins: pwm_f_y { 418 mux { 419 groups = "pwm_f_y"; 420 function = "pwm_f_y"; 421 }; 422 }; 423 424 hdmi_hpd_pins: hdmi_hpd { 425 mux { 426 groups = "hdmi_hpd"; 427 function = "hdmi_hpd"; 428 }; 429 }; 430 431 hdmi_i2c_pins: hdmi_i2c { 432 mux { 433 groups = "hdmi_sda", "hdmi_scl"; 434 function = "hdmi_i2c"; 435 }; 436 }; 437 }; 438}; 439 440&hiubus { 441 clkc: clock-controller@0 { 442 compatible = "amlogic,gxbb-clkc"; 443 #clock-cells = <1>; 444 reg = <0x0 0x0 0x0 0x3db>; 445 }; 446}; 447 448&apb { 449 mali: gpu@c0000 { 450 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; 451 reg = <0x0 0xc0000 0x0 0x40000>; 452 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "gp", "gpmmu", "pp", "pmu", 463 "pp0", "ppmmu0", "pp1", "ppmmu1", 464 "pp2", "ppmmu2"; 465 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 466 clock-names = "bus", "core"; 467 468 /* 469 * Mali clocking is provided by two identical clock paths 470 * MALI_0 and MALI_1 muxed to a single clock by a glitch 471 * free mux to safely change frequency while running. 472 */ 473 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 474 <&clkc CLKID_MALI_0>, 475 <&clkc CLKID_MALI>; /* Glitch free mux */ 476 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 477 <0>, /* Do Nothing */ 478 <&clkc CLKID_MALI_0>; 479 assigned-clock-rates = <0>, /* Do Nothing */ 480 <666666666>, 481 <0>; /* Do Nothing */ 482 }; 483}; 484 485&i2c_A { 486 clocks = <&clkc CLKID_I2C>; 487}; 488 489&i2c_AO { 490 clocks = <&clkc CLKID_AO_I2C>; 491}; 492 493&i2c_B { 494 clocks = <&clkc CLKID_I2C>; 495}; 496 497&i2c_C { 498 clocks = <&clkc CLKID_I2C>; 499}; 500 501&saradc { 502 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc"; 503 clocks = <&xtal>, 504 <&clkc CLKID_SAR_ADC>, 505 <&clkc CLKID_SANA>, 506 <&clkc CLKID_SAR_ADC_CLK>, 507 <&clkc CLKID_SAR_ADC_SEL>; 508 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 509}; 510 511&sd_emmc_a { 512 clocks = <&clkc CLKID_SD_EMMC_A>, 513 <&xtal>, 514 <&clkc CLKID_FCLK_DIV2>; 515 clock-names = "core", "clkin0", "clkin1"; 516}; 517 518&sd_emmc_b { 519 clocks = <&clkc CLKID_SD_EMMC_B>, 520 <&xtal>, 521 <&clkc CLKID_FCLK_DIV2>; 522 clock-names = "core", "clkin0", "clkin1"; 523}; 524 525&sd_emmc_c { 526 clocks = <&clkc CLKID_SD_EMMC_C>, 527 <&xtal>, 528 <&clkc CLKID_FCLK_DIV2>; 529 clock-names = "core", "clkin0", "clkin1"; 530}; 531 532&spifc { 533 clocks = <&clkc CLKID_SPI>; 534}; 535 536&vpu { 537 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; 538}; 539